Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T7,T39
1	0	Covered	T2,T7,T28

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T12,T38
0	1	Covered	T6,T12,T38
1	0	Covered	T77,T234

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T12,T38
1	-	Covered	T6,T12,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T7
DetectSt	168	Covered	T2,T6,T7
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T12,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T7
DebounceSt->IdleSt	163	Covered	T77,T213,T214
DetectSt->IdleSt	186	Covered	T2,T7,T39
DetectSt->StableSt	191	Covered	T6,T12,T38
IdleSt->DebounceSt	148	Covered	T2,T6,T7
StableSt->IdleSt	206	Covered	T6,T12,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T2,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T77,T213,T214
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T2,T7,T39
DetectSt	-	-	-	-	0	1	-	Covered	T6,T12,T38
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T6,T12,T38
StableSt	-	-	-	-	-	-	0	Covered	T6,T12,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	3115	0	0
CntIncr_A	7138179	107718	0	0
CntNoWrap_A	7138179	6468936	0	0
DetectStDropOut_A	7138179	385	0	0
DetectedOut_A	7138179	78428	0	0
DetectedPulseOut_A	7138179	932	0	0
DisabledIdleSt_A	7138179	6024793	0	0
DisabledNoDetection_A	7138179	6026978	0	0
EnterDebounceSt_A	7138179	1566	0	0
EnterDetectSt_A	7138179	1550	0	0
EnterStableSt_A	7138179	932	0	0
PulseIsPulse_A	7138179	932	0	0
StayInStableSt	7138179	77382	0	0
gen_high_event_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_high_level_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	816	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	3115	0	0
T2	13902	16	0	0
T3	16928	0	0	0
T6	15299	24	0	0
T7	0	24	0	0
T12	0	48	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	44	0	0
T38	0	56	0	0
T39	0	36	0	0
T42	0	18	0	0
T50	782	0	0	0
T69	0	48	0	0
T70	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	107718	0	0
T2	13902	407	0	0
T3	16928	0	0	0
T6	15299	1032	0	0
T7	0	670	0	0
T12	0	864	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	2839	0	0
T38	0	1736	0	0
T39	0	1242	0	0
T42	0	572	0	0
T50	782	0	0	0
T69	0	1080	0	0
T70	0	1474	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6468936	0	0
T1	21441	14653	0	0
T2	13902	13457	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	385	0	0
T2	13902	5	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T7	0	6	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T39	0	18	0	0
T42	0	9	0	0
T50	782	0	0	0
T70	0	25	0	0
T77	0	1	0	0
T79	0	15	0	0
T88	0	2	0	0
T91	0	30	0	0
T92	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	78428	0	0
T6	15299	828	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	869	0	0
T24	20701	0	0	0
T38	0	1877	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T69	0	1797	0	0
T77	0	267	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	1071	0	0
T215	0	2658	0	0
T216	0	1564	0	0
T217	0	3820	0	0
T219	0	56	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	932	0	0
T6	15299	12	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	24	0	0
T24	20701	0	0	0
T38	0	28	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T69	0	24	0	0
T77	0	5	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	27	0	0
T215	0	25	0	0
T216	0	14	0	0
T217	0	16	0	0
T219	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6024793	0	0
T1	21441	14653	0	0
T2	13902	10704	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6026978	0	0
T1	21441	14672	0	0
T2	13902	10708	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	1566	0	0
T2	13902	8	0	0
T3	16928	0	0	0
T6	15299	12	0	0
T7	0	12	0	0
T12	0	24	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	22	0	0
T38	0	28	0	0
T39	0	18	0	0
T42	0	9	0	0
T50	782	0	0	0
T69	0	24	0	0
T70	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	1550	0	0
T2	13902	8	0	0
T3	16928	0	0	0
T6	15299	12	0	0
T7	0	12	0	0
T12	0	24	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	22	0	0
T38	0	28	0	0
T39	0	18	0	0
T42	0	9	0	0
T50	782	0	0	0
T69	0	24	0	0
T70	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	932	0	0
T6	15299	12	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	24	0	0
T24	20701	0	0	0
T38	0	28	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T69	0	24	0	0
T77	0	5	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	27	0	0
T215	0	25	0	0
T216	0	14	0	0
T217	0	16	0	0
T219	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	932	0	0
T6	15299	12	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	24	0	0
T24	20701	0	0	0
T38	0	28	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T69	0	24	0	0
T77	0	5	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	27	0	0
T215	0	25	0	0
T216	0	14	0	0
T217	0	16	0	0
T219	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	77382	0	0
T6	15299	815	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	844	0	0
T24	20701	0	0	0
T38	0	1849	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T69	0	1771	0	0
T77	0	262	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	1044	0	0
T215	0	2626	0	0
T216	0	1542	0	0
T217	0	3797	0	0
T219	0	54	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	816	0	0
T6	15299	11	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	23	0	0
T24	20701	0	0	0
T38	0	28	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T69	0	22	0	0
T77	0	4	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	27	0	0
T215	0	18	0	0
T216	0	6	0	0
T217	0	9	0	0
T219	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T3,T185,T228
1	0	Covered	T77,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T12
0	1	Covered	T1,T6,T12
1	0	Covered	T77,T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T12
1	-	Covered	T1,T6,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T6
DetectSt	168	Covered	T1,T3,T6
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T6,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T6
DebounceSt->IdleSt	163	Covered	T1,T3,T30
DetectSt->IdleSt	186	Covered	T3,T185,T228
DetectSt->StableSt	191	Covered	T1,T6,T12
IdleSt->DebounceSt	148	Covered	T1,T3,T6
StableSt->IdleSt	206	Covered	T1,T6,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T3,T30
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T3,T185,T228
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	937	0	0
CntIncr_A	7138179	53724	0	0
CntNoWrap_A	7138179	6471114	0	0
DetectStDropOut_A	7138179	69	0	0
DetectedOut_A	7138179	17030	0	0
DetectedPulseOut_A	7138179	371	0	0
DisabledIdleSt_A	7138179	6052155	0	0
DisabledNoDetection_A	7138179	6053879	0	0
EnterDebounceSt_A	7138179	494	0	0
EnterDetectSt_A	7138179	445	0	0
EnterStableSt_A	7138179	371	0	0
PulseIsPulse_A	7138179	371	0	0
StayInStableSt	7138179	16621	0	0
gen_high_level_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	330	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	937	0	0
T1	21441	27	0	0
T2	13902	0	0	0
T3	16928	16	0	0
T6	15299	4	0	0
T12	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T29	0	4	0	0
T30	0	17	0	0
T41	0	2	0	0
T64	0	12	0	0
T76	0	2	0	0
T185	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	53724	0	0
T1	21441	1166	0	0
T2	13902	0	0	0
T3	16928	1290	0	0
T6	15299	118	0	0
T12	0	51	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T29	0	284	0	0
T30	0	957	0	0
T41	0	84	0	0
T64	0	768	0	0
T76	0	141	0	0
T185	0	472	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471114	0	0
T1	21441	14626	0	0
T2	13902	13473	0	0
T3	16928	16471	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	69	0	0
T3	16928	7	0	0
T6	15299	0	0	0
T7	6881	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T50	782	0	0	0
T110	0	2	0	0
T185	0	3	0	0
T188	0	21	0	0
T220	0	2	0	0
T223	0	8	0	0
T225	0	2	0	0
T228	0	11	0	0
T235	0	4	0	0
T236	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	17030	0	0
T1	21441	1002	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	151	0	0
T12	0	66	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T29	0	9	0	0
T30	0	88	0	0
T41	0	42	0	0
T64	0	283	0	0
T69	0	188	0	0
T76	0	8	0	0
T215	0	378	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	371	0	0
T1	21441	13	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	2	0	0
T12	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T29	0	2	0	0
T30	0	8	0	0
T41	0	1	0	0
T64	0	6	0	0
T69	0	2	0	0
T76	0	1	0	0
T215	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6052155	0	0
T1	21441	9359	0	0
T2	13902	13473	0	0
T3	16928	12088	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6053879	0	0
T1	21441	9375	0	0
T2	13902	13478	0	0
T3	16928	12088	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	494	0	0
T1	21441	14	0	0
T2	13902	0	0	0
T3	16928	9	0	0
T6	15299	2	0	0
T12	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T29	0	2	0	0
T30	0	9	0	0
T41	0	1	0	0
T64	0	6	0	0
T76	0	1	0	0
T185	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	445	0	0
T1	21441	13	0	0
T2	13902	0	0	0
T3	16928	7	0	0
T6	15299	2	0	0
T12	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T29	0	2	0	0
T30	0	8	0	0
T41	0	1	0	0
T64	0	6	0	0
T76	0	1	0	0
T185	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	371	0	0
T1	21441	13	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	2	0	0
T12	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T29	0	2	0	0
T30	0	8	0	0
T41	0	1	0	0
T64	0	6	0	0
T69	0	2	0	0
T76	0	1	0	0
T215	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	371	0	0
T1	21441	13	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	2	0	0
T12	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T29	0	2	0	0
T30	0	8	0	0
T41	0	1	0	0
T64	0	6	0	0
T69	0	2	0	0
T76	0	1	0	0
T215	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	16621	0	0
T1	21441	989	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	149	0	0
T12	0	65	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T29	0	7	0	0
T30	0	80	0	0
T41	0	41	0	0
T64	0	277	0	0
T69	0	186	0	0
T76	0	7	0	0
T215	0	372	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	330	0	0
T1	21441	13	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	2	0	0
T12	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T29	0	2	0	0
T30	0	8	0	0
T41	0	1	0	0
T64	0	6	0	0
T69	0	2	0	0
T76	0	1	0	0
T215	0	4	0	0