SYSRST_CTRL Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: `4fd94db59a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.600s	2.109ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	7.680s	2.455ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	7.260s	2.430ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	6.100s	2.246ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	16.960s	6.034ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.430s	2.033ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	3.635m	76.257ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	12.620s	3.112ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.710s	2.118ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.430s	2.033ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.620s	3.112ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	7.679m	185.541ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	9.145m	195.053ms	89	100	89.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	13.646m	308.246ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	14.770s	5.387ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.720s	2.513ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.650s	2.209ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	23.596m	546.906ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.880s	2.612ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	9.589m	1.824s	47	50	94.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.246m	30.827ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	12.671m	324.335ms	49	50	98.00
V2	alert_test	sysrst_ctrl_alert_test	6.000s	2.011ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.200s	2.010ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	6.990s	2.072ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	6.990s	2.072ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	16.960s	6.034ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.430s	2.033ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.620s	3.112ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	34.480s	9.875ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	16.960s	6.034ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.430s	2.033ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.620s	3.112ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	34.480s	9.875ms	20	20	100.00
V2		TOTAL			677	692	97.83
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.868m	42.012ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.970m	42.427ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.970m	42.427ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	10.482m	2.241s	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			914	932	98.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.29	99.38	96.41	100.00	97.44	98.85	99.61	89.33

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 4 failures:

Test sysrst_ctrl_ultra_low_pwr has 3 failures.

14.sysrst_ctrl_ultra_low_pwr.102872817858523985020360101068290843179720158716933554394450728219070773680753
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2320781966 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 5588281966 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5588281966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.sysrst_ctrl_ultra_low_pwr.54076054447880432093351728055871312222129959195421330400925191392495918208920
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 3799204230 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 3901704230 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 6121704230 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 6159368976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test sysrst_ctrl_stress_all has 1 failures.

17.sysrst_ctrl_stress_all.57943356954566946712477881498662244623318191594187244753779948336500131299342
Line 565, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 9902251541 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 10294751541 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 10294751541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 4 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 4 failures.

15.sysrst_ctrl_combo_detect_with_pre_cond.52370769887103975924405674819159261704750995004312638452162241971153836015899
Line 567, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 14020206858 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 14020206858 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 14020206858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.sysrst_ctrl_combo_detect_with_pre_cond.26682409975417731780387847136154497073521593788434652154016894107896989295042
Line 589, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 38710140219 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 38710140219 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 38710140219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

0.sysrst_ctrl_stress_all_with_rand_reset.104976513119357603556174169859853585464542942039234498970856855420382193839493
Line 598, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16969301712 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 16969301712 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 16969301712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

8.sysrst_ctrl_combo_detect_with_pre_cond.71171643978506276055978326683136013098283361683481075749542895938947026087402
Line 571, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 15137755677 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-4
  UVM_INFO @ 15332755677 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 15352755677 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 25439602162 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2a
  UVM_INFO @ 25439689118 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x32

UVM_FATAL (cip_base_vseq.sv:104) [sysrst_ctrl_common_vseq] wait timeout occurred! has 1 failures:
- Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
  - 10.sysrst_ctrl_stress_all_with_rand_reset.11988762415368973773834735701353648094958359946734407272620584733176362609666
    Line 615, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 19367724610 ps: (cip_base_vseq.sv:104) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] wait timeout occurred!
  UVM_INFO @ 19367724610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == *) Unexpected L2H transition of ec_rst_l_o has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

17.sysrst_ctrl_combo_detect_with_pre_cond.85686894161397693877460087796866493752694498896982456139985262804515290341213
Line 609, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 50120495625 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == 1) Unexpected L2H transition of ec_rst_l_o
  UVM_INFO @ 50135495625 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 50155495625 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 60324501099 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2f
  UVM_INFO @ 60324884085 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1c

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

38.sysrst_ctrl_combo_detect_with_pre_cond.14006651033522548875226898089352034203881081605355720729637763522513178820874
Line 566, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13248883280 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-4
  UVM_ERROR @ 13248883280 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(3) +/-4
  UVM_INFO @ 13248883280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

39.sysrst_ctrl_combo_detect_with_pre_cond.7987986482458430904444601068286119287796629883887908886407955870620100706291
Line 642, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 97782930962 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(3) +/-4
  UVM_ERROR @ 97782930962 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-4
  UVM_INFO @ 97782930962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == *) Unexpected H2L transition of ec_rst_l_o has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

41.sysrst_ctrl_combo_detect_with_pre_cond.111524146813525221931547474838051086622536581232190581746176840925440610794502
Line 572, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 15399812442 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == 1) Unexpected H2L transition of ec_rst_l_o
  UVM_INFO @ 15444812442 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :0
  UVM_INFO @ 15444812442 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :1
  UVM_INFO @ 15444812442 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :2
  UVM_INFO @ 15614812442 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

49.sysrst_ctrl_stress_all_with_rand_reset.80573335938357928585996103921638148325796682447759672413777303803085904864419
Line 578, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9405284346 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 9405284346 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 9405284346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

70.sysrst_ctrl_combo_detect_with_pre_cond.14536278571021400116432081200181437135769432699410314879116751065880761803954
Line 606, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 36377789947 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 36507789947 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 36527789947 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_ERROR @ 36582811515 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 36582811515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

84.sysrst_ctrl_combo_detect_with_pre_cond.23009960563540428746951197157194062348805269056261291863625781924656904604332
Line 568, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 12946390555 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4
  UVM_INFO @ 12951390555 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
  UVM_INFO @ 13146390555 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 13166390555 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 13642263193 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2