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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.35 98.73 96.73 100.00 94.87 98.23 99.23 93.68


Total test records in report: 920
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

T585 /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.2007995600 Apr 28 12:23:58 PM PDT 24 Apr 28 12:24:08 PM PDT 24 2454559551 ps
T586 /workspace/coverage/default/14.sysrst_ctrl_stress_all.2976707149 Apr 28 12:22:49 PM PDT 24 Apr 28 12:24:18 PM PDT 24 109045352603 ps
T587 /workspace/coverage/default/14.sysrst_ctrl_combo_detect.1525627424 Apr 28 12:22:04 PM PDT 24 Apr 28 12:23:22 PM PDT 24 106229632602 ps
T588 /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1817839153 Apr 28 12:21:23 PM PDT 24 Apr 28 12:23:05 PM PDT 24 71966775195 ps
T589 /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.130392424 Apr 28 12:22:55 PM PDT 24 Apr 28 12:23:19 PM PDT 24 18432584898 ps
T590 /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2756220271 Apr 28 12:23:30 PM PDT 24 Apr 28 12:23:34 PM PDT 24 9153287372 ps
T260 /workspace/coverage/default/2.sysrst_ctrl_sec_cm.1766653090 Apr 28 12:22:50 PM PDT 24 Apr 28 12:23:24 PM PDT 24 42152576772 ps
T181 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.643822721 Apr 28 12:23:22 PM PDT 24 Apr 28 12:23:31 PM PDT 24 2682210938 ps
T591 /workspace/coverage/default/4.sysrst_ctrl_alert_test.2839755289 Apr 28 12:21:53 PM PDT 24 Apr 28 12:22:04 PM PDT 24 2012750301 ps
T592 /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2049927505 Apr 28 12:22:14 PM PDT 24 Apr 28 12:22:20 PM PDT 24 2969626368 ps
T593 /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1566368679 Apr 28 12:22:54 PM PDT 24 Apr 28 12:23:07 PM PDT 24 3793543254 ps
T240 /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1688715422 Apr 28 12:23:05 PM PDT 24 Apr 28 12:23:53 PM PDT 24 68501133336 ps
T594 /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.965663491 Apr 28 12:22:52 PM PDT 24 Apr 28 12:23:08 PM PDT 24 3219287336 ps
T595 /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.2097677811 Apr 28 12:18:08 PM PDT 24 Apr 28 12:18:11 PM PDT 24 2816962637 ps
T180 /workspace/coverage/default/35.sysrst_ctrl_stress_all.3428542749 Apr 28 12:22:49 PM PDT 24 Apr 28 12:24:19 PM PDT 24 276225821031 ps
T596 /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3778586712 Apr 28 12:22:47 PM PDT 24 Apr 28 12:23:05 PM PDT 24 2611817605 ps
T214 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2075864603 Apr 28 12:22:48 PM PDT 24 Apr 28 12:25:52 PM PDT 24 59720717168 ps
T597 /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.1981755282 Apr 28 12:22:54 PM PDT 24 Apr 28 12:23:11 PM PDT 24 2464805069 ps
T598 /workspace/coverage/default/1.sysrst_ctrl_alert_test.1858670427 Apr 28 12:20:21 PM PDT 24 Apr 28 12:20:25 PM PDT 24 2016929013 ps
T599 /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.458515334 Apr 28 12:22:54 PM PDT 24 Apr 28 12:23:12 PM PDT 24 7978497387 ps
T353 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.4204603422 Apr 28 12:23:50 PM PDT 24 Apr 28 12:24:42 PM PDT 24 74418400608 ps
T165 /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.596052861 Apr 28 12:22:43 PM PDT 24 Apr 28 12:23:23 PM PDT 24 215929834098 ps
T600 /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.2736058763 Apr 28 12:20:45 PM PDT 24 Apr 28 12:20:48 PM PDT 24 2491912822 ps
T601 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.2978682984 Apr 28 12:22:49 PM PDT 24 Apr 28 12:23:05 PM PDT 24 2457322836 ps
T602 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3533435874 Apr 28 12:23:25 PM PDT 24 Apr 28 12:25:43 PM PDT 24 55753001083 ps
T191 /workspace/coverage/default/30.sysrst_ctrl_edge_detect.2312000798 Apr 28 12:22:45 PM PDT 24 Apr 28 12:23:04 PM PDT 24 4703582236 ps
T603 /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1056164874 Apr 28 12:22:50 PM PDT 24 Apr 28 12:23:12 PM PDT 24 3780325105 ps
T604 /workspace/coverage/default/19.sysrst_ctrl_smoke.906905632 Apr 28 12:21:22 PM PDT 24 Apr 28 12:21:26 PM PDT 24 2117660162 ps
T605 /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.3585210717 Apr 28 12:21:55 PM PDT 24 Apr 28 12:22:06 PM PDT 24 2507885289 ps
T606 /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1671964999 Apr 28 12:23:46 PM PDT 24 Apr 28 12:26:22 PM PDT 24 59646414109 ps
T607 /workspace/coverage/default/23.sysrst_ctrl_stress_all.2259342573 Apr 28 12:22:42 PM PDT 24 Apr 28 12:22:53 PM PDT 24 8334794789 ps
T608 /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.582247609 Apr 28 12:18:57 PM PDT 24 Apr 28 12:18:59 PM PDT 24 3451689343 ps
T352 /workspace/coverage/default/22.sysrst_ctrl_combo_detect.1150513675 Apr 28 12:22:03 PM PDT 24 Apr 28 12:27:01 PM PDT 24 105043360835 ps
T609 /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.4064297557 Apr 28 12:22:49 PM PDT 24 Apr 28 12:23:05 PM PDT 24 2616572398 ps
T610 /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2161698614 Apr 28 12:23:45 PM PDT 24 Apr 28 12:24:55 PM PDT 24 26081458655 ps
T611 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1609993662 Apr 28 12:21:55 PM PDT 24 Apr 28 12:22:03 PM PDT 24 2341376441 ps
T612 /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1872506089 Apr 28 12:21:08 PM PDT 24 Apr 28 12:35:06 PM PDT 24 297114061243 ps
T233 /workspace/coverage/default/13.sysrst_ctrl_combo_detect.1962519945 Apr 28 12:20:28 PM PDT 24 Apr 28 12:26:04 PM PDT 24 124154094889 ps
T613 /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1949255796 Apr 28 12:22:47 PM PDT 24 Apr 28 12:23:00 PM PDT 24 2480936720 ps
T614 /workspace/coverage/default/4.sysrst_ctrl_edge_detect.658500028 Apr 28 12:22:13 PM PDT 24 Apr 28 12:22:24 PM PDT 24 2944630109 ps
T615 /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3059847256 Apr 28 12:23:03 PM PDT 24 Apr 28 12:23:16 PM PDT 24 3849439558 ps
T616 /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3442259913 Apr 28 12:24:31 PM PDT 24 Apr 28 12:24:41 PM PDT 24 3832157435 ps
T617 /workspace/coverage/default/34.sysrst_ctrl_alert_test.989358720 Apr 28 12:23:09 PM PDT 24 Apr 28 12:23:14 PM PDT 24 2042540448 ps
T618 /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.1925123604 Apr 28 12:22:44 PM PDT 24 Apr 28 12:22:58 PM PDT 24 2508240413 ps
T619 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.1568852895 Apr 28 12:22:52 PM PDT 24 Apr 28 12:26:18 PM PDT 24 143906043111 ps
T620 /workspace/coverage/default/49.sysrst_ctrl_alert_test.553734135 Apr 28 12:23:56 PM PDT 24 Apr 28 12:24:04 PM PDT 24 2035490970 ps
T621 /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.3414820231 Apr 28 12:19:57 PM PDT 24 Apr 28 12:20:01 PM PDT 24 2517935617 ps
T342 /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.837596433 Apr 28 12:23:24 PM PDT 24 Apr 28 12:26:59 PM PDT 24 165563588351 ps
T349 /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.30560089 Apr 28 12:24:10 PM PDT 24 Apr 28 12:25:51 PM PDT 24 34207192050 ps
T622 /workspace/coverage/default/26.sysrst_ctrl_smoke.4225432636 Apr 28 12:22:39 PM PDT 24 Apr 28 12:22:51 PM PDT 24 2111890447 ps
T623 /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.420690419 Apr 28 12:21:54 PM PDT 24 Apr 28 12:22:01 PM PDT 24 2616454841 ps
T624 /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1701745145 Apr 28 12:22:47 PM PDT 24 Apr 28 12:22:59 PM PDT 24 3871616345 ps
T200 /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.309001705 Apr 28 12:22:11 PM PDT 24 Apr 28 12:24:10 PM PDT 24 47319924898 ps
T625 /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1992548635 Apr 28 12:23:02 PM PDT 24 Apr 28 12:23:18 PM PDT 24 2938155910 ps
T626 /workspace/coverage/default/8.sysrst_ctrl_edge_detect.3284676081 Apr 28 12:22:47 PM PDT 24 Apr 28 12:23:02 PM PDT 24 3837413824 ps
T627 /workspace/coverage/default/46.sysrst_ctrl_edge_detect.3172664632 Apr 28 12:23:17 PM PDT 24 Apr 28 12:23:19 PM PDT 24 3104770829 ps
T628 /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3943041080 Apr 28 12:21:49 PM PDT 24 Apr 28 12:21:52 PM PDT 24 2621441926 ps
T629 /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.1500998673 Apr 28 12:21:47 PM PDT 24 Apr 28 12:21:50 PM PDT 24 2533585389 ps
T630 /workspace/coverage/default/15.sysrst_ctrl_alert_test.1341120326 Apr 28 12:21:05 PM PDT 24 Apr 28 12:21:08 PM PDT 24 2026570433 ps
T631 /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3929306584 Apr 28 12:22:25 PM PDT 24 Apr 28 12:22:28 PM PDT 24 2621548509 ps
T632 /workspace/coverage/default/26.sysrst_ctrl_stress_all.1782016022 Apr 28 12:23:44 PM PDT 24 Apr 28 12:24:15 PM PDT 24 80542237861 ps
T633 /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1276568963 Apr 28 12:23:03 PM PDT 24 Apr 28 12:23:15 PM PDT 24 2113837584 ps
T634 /workspace/coverage/default/10.sysrst_ctrl_smoke.2219359134 Apr 28 12:22:48 PM PDT 24 Apr 28 12:23:02 PM PDT 24 2114218566 ps
T635 /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1163655273 Apr 28 12:19:10 PM PDT 24 Apr 28 12:19:13 PM PDT 24 3787732412 ps
T636 /workspace/coverage/default/43.sysrst_ctrl_alert_test.2728831497 Apr 28 12:23:25 PM PDT 24 Apr 28 12:23:30 PM PDT 24 2019272480 ps
T637 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1806732254 Apr 28 12:19:45 PM PDT 24 Apr 28 12:19:50 PM PDT 24 2314615717 ps
T638 /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.617392855 Apr 28 12:23:34 PM PDT 24 Apr 28 12:23:36 PM PDT 24 3196034632 ps
T639 /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.1838132355 Apr 28 12:22:03 PM PDT 24 Apr 28 12:22:10 PM PDT 24 2515154763 ps
T640 /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1554931444 Apr 28 12:23:20 PM PDT 24 Apr 28 12:23:24 PM PDT 24 2526539210 ps
T641 /workspace/coverage/default/43.sysrst_ctrl_edge_detect.3629269096 Apr 28 12:23:22 PM PDT 24 Apr 28 12:23:26 PM PDT 24 3021392866 ps
T642 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1132549559 Apr 28 12:18:54 PM PDT 24 Apr 28 12:19:24 PM PDT 24 22512459252 ps
T643 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1456755658 Apr 28 12:24:25 PM PDT 24 Apr 28 12:26:23 PM PDT 24 46298935859 ps
T644 /workspace/coverage/default/33.sysrst_ctrl_alert_test.1022740632 Apr 28 12:22:56 PM PDT 24 Apr 28 12:23:07 PM PDT 24 2094821339 ps
T136 /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2456323926 Apr 28 12:21:51 PM PDT 24 Apr 28 12:22:39 PM PDT 24 761021577118 ps
T645 /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3232513318 Apr 28 12:21:21 PM PDT 24 Apr 28 12:21:24 PM PDT 24 7056140572 ps
T646 /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.542662413 Apr 28 12:22:49 PM PDT 24 Apr 28 12:23:03 PM PDT 24 2112539787 ps
T647 /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.2918707356 Apr 28 12:21:06 PM PDT 24 Apr 28 12:21:13 PM PDT 24 2462677846 ps
T648 /workspace/coverage/default/6.sysrst_ctrl_alert_test.2748527514 Apr 28 12:21:54 PM PDT 24 Apr 28 12:22:00 PM PDT 24 2030544449 ps
T649 /workspace/coverage/default/34.sysrst_ctrl_stress_all.2334608768 Apr 28 12:23:00 PM PDT 24 Apr 28 12:23:42 PM PDT 24 15548453685 ps
T650 /workspace/coverage/default/23.sysrst_ctrl_smoke.1816399339 Apr 28 12:22:11 PM PDT 24 Apr 28 12:22:20 PM PDT 24 2110760885 ps
T651 /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3553559271 Apr 28 12:23:00 PM PDT 24 Apr 28 12:23:14 PM PDT 24 3838374729 ps
T652 /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.4154941718 Apr 28 12:23:55 PM PDT 24 Apr 28 12:24:03 PM PDT 24 2485639258 ps
T241 /workspace/coverage/default/2.sysrst_ctrl_stress_all.3142848116 Apr 28 12:20:11 PM PDT 24 Apr 28 12:21:49 PM PDT 24 39386328515 ps
T324 /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1884208801 Apr 28 12:21:51 PM PDT 24 Apr 28 12:23:00 PM PDT 24 99137372917 ps
T653 /workspace/coverage/default/3.sysrst_ctrl_edge_detect.2151302792 Apr 28 12:19:55 PM PDT 24 Apr 28 12:19:59 PM PDT 24 2758412258 ps
T654 /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1420102530 Apr 28 12:23:26 PM PDT 24 Apr 28 12:23:30 PM PDT 24 3414979299 ps
T655 /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.1468290780 Apr 28 12:21:11 PM PDT 24 Apr 28 12:21:18 PM PDT 24 2467009298 ps
T656 /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.3945954225 Apr 28 12:23:59 PM PDT 24 Apr 28 12:24:08 PM PDT 24 2518817839 ps
T657 /workspace/coverage/default/45.sysrst_ctrl_stress_all.2678164208 Apr 28 12:23:09 PM PDT 24 Apr 28 12:23:26 PM PDT 24 8849074056 ps
T658 /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.3744110953 Apr 28 12:21:53 PM PDT 24 Apr 28 12:21:59 PM PDT 24 2529399930 ps
T659 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.3468284149 Apr 28 12:19:45 PM PDT 24 Apr 28 12:19:54 PM PDT 24 2508080035 ps
T660 /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.1843458493 Apr 28 12:23:19 PM PDT 24 Apr 28 12:23:29 PM PDT 24 2452096973 ps
T661 /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.2641490488 Apr 28 12:22:17 PM PDT 24 Apr 28 12:22:21 PM PDT 24 2076637928 ps
T662 /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1099502547 Apr 28 12:19:45 PM PDT 24 Apr 28 12:19:49 PM PDT 24 3879647311 ps
T663 /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.167372089 Apr 28 12:23:14 PM PDT 24 Apr 28 12:23:18 PM PDT 24 2974394094 ps
T664 /workspace/coverage/default/4.sysrst_ctrl_stress_all.3084130966 Apr 28 12:21:52 PM PDT 24 Apr 28 12:22:01 PM PDT 24 9057802109 ps
T665 /workspace/coverage/default/39.sysrst_ctrl_alert_test.2410392154 Apr 28 12:24:25 PM PDT 24 Apr 28 12:24:28 PM PDT 24 2027354720 ps
T318 /workspace/coverage/default/0.sysrst_ctrl_combo_detect.2736356587 Apr 28 12:22:13 PM PDT 24 Apr 28 12:24:46 PM PDT 24 225569995025 ps
T666 /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.2333606256 Apr 28 12:21:26 PM PDT 24 Apr 28 12:21:34 PM PDT 24 2255363688 ps
T667 /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.167799270 Apr 28 12:23:28 PM PDT 24 Apr 28 12:23:34 PM PDT 24 2472257617 ps
T668 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.545754461 Apr 28 12:23:50 PM PDT 24 Apr 28 12:25:41 PM PDT 24 39701203719 ps
T234 /workspace/coverage/default/28.sysrst_ctrl_combo_detect.2168538113 Apr 28 12:22:44 PM PDT 24 Apr 28 12:25:43 PM PDT 24 66774648797 ps
T669 /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.2805940602 Apr 28 12:22:01 PM PDT 24 Apr 28 12:22:04 PM PDT 24 4362999651 ps
T54 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.755311497 Apr 28 12:22:14 PM PDT 24 Apr 28 12:23:43 PM PDT 24 33589763052 ps
T670 /workspace/coverage/default/36.sysrst_ctrl_edge_detect.3427474502 Apr 28 12:22:54 PM PDT 24 Apr 28 12:23:06 PM PDT 24 3020257854 ps
T671 /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.727878687 Apr 28 12:23:02 PM PDT 24 Apr 28 12:23:12 PM PDT 24 3198953810 ps
T672 /workspace/coverage/default/44.sysrst_ctrl_smoke.1976091156 Apr 28 12:23:13 PM PDT 24 Apr 28 12:23:17 PM PDT 24 2134290135 ps
T673 /workspace/coverage/default/41.sysrst_ctrl_edge_detect.740527830 Apr 28 12:23:07 PM PDT 24 Apr 28 12:23:14 PM PDT 24 2838529808 ps
T201 /workspace/coverage/default/23.sysrst_ctrl_edge_detect.2568952854 Apr 28 12:22:28 PM PDT 24 Apr 28 12:22:31 PM PDT 24 3322132084 ps
T674 /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1394247009 Apr 28 12:23:29 PM PDT 24 Apr 28 12:23:39 PM PDT 24 3478094389 ps
T675 /workspace/coverage/default/47.sysrst_ctrl_smoke.3300162396 Apr 28 12:23:25 PM PDT 24 Apr 28 12:23:28 PM PDT 24 2136459311 ps
T676 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.4070545830 Apr 28 12:20:37 PM PDT 24 Apr 28 12:20:45 PM PDT 24 2417090486 ps
T677 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.414276778 Apr 28 12:20:54 PM PDT 24 Apr 28 12:21:54 PM PDT 24 40310928487 ps
T678 /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2851954935 Apr 28 12:23:13 PM PDT 24 Apr 28 12:23:17 PM PDT 24 2637173757 ps
T679 /workspace/coverage/default/4.sysrst_ctrl_combo_detect.600399335 Apr 28 12:22:45 PM PDT 24 Apr 28 12:29:22 PM PDT 24 150423993558 ps
T680 /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.4266520933 Apr 28 12:20:43 PM PDT 24 Apr 28 12:20:51 PM PDT 24 2507025731 ps
T681 /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.1603889846 Apr 28 12:22:22 PM PDT 24 Apr 28 12:22:25 PM PDT 24 2629651677 ps
T682 /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3025278682 Apr 28 12:23:41 PM PDT 24 Apr 28 12:24:32 PM PDT 24 25836093675 ps
T683 /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.528048371 Apr 28 12:24:06 PM PDT 24 Apr 28 12:24:15 PM PDT 24 2614191982 ps
T684 /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.2800867308 Apr 28 12:22:10 PM PDT 24 Apr 28 12:22:14 PM PDT 24 2133340802 ps
T685 /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.823133993 Apr 28 12:21:16 PM PDT 24 Apr 28 12:21:19 PM PDT 24 2526761576 ps
T137 /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2496245165 Apr 28 12:23:27 PM PDT 24 Apr 28 12:23:29 PM PDT 24 6191662876 ps
T686 /workspace/coverage/default/45.sysrst_ctrl_edge_detect.2064173717 Apr 28 12:23:14 PM PDT 24 Apr 28 12:23:22 PM PDT 24 4343447839 ps
T687 /workspace/coverage/default/47.sysrst_ctrl_edge_detect.1746701604 Apr 28 12:23:40 PM PDT 24 Apr 28 12:23:46 PM PDT 24 2818040239 ps
T688 /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2681425989 Apr 28 12:22:53 PM PDT 24 Apr 28 12:23:06 PM PDT 24 4031632465 ps
T689 /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.472451148 Apr 28 12:22:47 PM PDT 24 Apr 28 12:23:03 PM PDT 24 2466231742 ps
T690 /workspace/coverage/default/16.sysrst_ctrl_smoke.661562463 Apr 28 12:21:02 PM PDT 24 Apr 28 12:21:04 PM PDT 24 2150292702 ps
T691 /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3808156571 Apr 28 12:21:24 PM PDT 24 Apr 28 12:21:33 PM PDT 24 2608187893 ps
T355 /workspace/coverage/default/36.sysrst_ctrl_combo_detect.1260456206 Apr 28 12:24:00 PM PDT 24 Apr 28 12:28:43 PM PDT 24 106255285947 ps
T345 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1792635744 Apr 28 12:22:35 PM PDT 24 Apr 28 12:23:14 PM PDT 24 51775425393 ps
T692 /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1839649022 Apr 28 12:22:49 PM PDT 24 Apr 28 12:23:11 PM PDT 24 3396541981 ps
T242 /workspace/coverage/default/46.sysrst_ctrl_combo_detect.1379643490 Apr 28 12:23:22 PM PDT 24 Apr 28 12:23:51 PM PDT 24 91372758947 ps
T693 /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.509289755 Apr 28 12:23:37 PM PDT 24 Apr 28 12:23:44 PM PDT 24 5652111556 ps
T121 /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1998382907 Apr 28 12:23:07 PM PDT 24 Apr 28 12:24:33 PM PDT 24 273368755133 ps
T694 /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.4027271815 Apr 28 12:23:19 PM PDT 24 Apr 28 12:23:22 PM PDT 24 2085540949 ps
T695 /workspace/coverage/default/48.sysrst_ctrl_smoke.3789431193 Apr 28 12:23:43 PM PDT 24 Apr 28 12:23:51 PM PDT 24 2114636927 ps
T696 /workspace/coverage/default/25.sysrst_ctrl_edge_detect.1069537626 Apr 28 12:22:44 PM PDT 24 Apr 28 12:22:58 PM PDT 24 2549304718 ps
T697 /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3241718171 Apr 28 12:23:35 PM PDT 24 Apr 28 12:23:39 PM PDT 24 2519405415 ps
T698 /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2427108064 Apr 28 12:23:04 PM PDT 24 Apr 28 12:23:17 PM PDT 24 3306340016 ps
T699 /workspace/coverage/default/12.sysrst_ctrl_smoke.3661527683 Apr 28 12:20:21 PM PDT 24 Apr 28 12:20:28 PM PDT 24 2114129828 ps
T700 /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.794340888 Apr 28 12:22:44 PM PDT 24 Apr 28 12:22:56 PM PDT 24 4651788671 ps
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T289 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1244078105 Apr 28 12:18:09 PM PDT 24 Apr 28 12:19:49 PM PDT 24 80629398071 ps
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T721 /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2665530907 Apr 28 12:21:56 PM PDT 24 Apr 28 12:22:02 PM PDT 24 2634991163 ps
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T733 /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.868433827 Apr 28 12:21:44 PM PDT 24 Apr 28 12:21:47 PM PDT 24 2634165819 ps
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T735 /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.3387906465 Apr 28 12:21:58 PM PDT 24 Apr 28 12:22:05 PM PDT 24 2522380551 ps
T736 /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2739662958 Apr 28 12:22:10 PM PDT 24 Apr 28 12:22:14 PM PDT 24 6972768323 ps
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T739 /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2139345306 Apr 28 12:23:58 PM PDT 24 Apr 28 12:24:09 PM PDT 24 3687272097 ps
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T741 /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1452740063 Apr 28 12:23:50 PM PDT 24 Apr 28 12:26:49 PM PDT 24 67576451437 ps
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T743 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2347766829 Apr 28 12:24:08 PM PDT 24 Apr 28 12:25:05 PM PDT 24 20276125794 ps
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T748 /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1738541100 Apr 28 12:23:45 PM PDT 24 Apr 28 12:24:29 PM PDT 24 57983197783 ps
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T758 /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2786785608 Apr 28 12:23:52 PM PDT 24 Apr 28 12:24:05 PM PDT 24 3795977290 ps
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T761 /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2783021007 Apr 28 12:23:45 PM PDT 24 Apr 28 12:23:54 PM PDT 24 2509557840 ps
T762 /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.531350386 Apr 28 12:20:33 PM PDT 24 Apr 28 12:20:37 PM PDT 24 3621835020 ps
T763 /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2209217330 Apr 28 12:24:26 PM PDT 24 Apr 28 12:24:30 PM PDT 24 2750728152 ps
T764 /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.636671084 Apr 28 12:22:44 PM PDT 24 Apr 28 12:22:54 PM PDT 24 2632828760 ps
T765 /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.2894978199 Apr 28 12:20:07 PM PDT 24 Apr 28 12:20:16 PM PDT 24 2610645815 ps
T766 /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.1303860198 Apr 28 12:22:34 PM PDT 24 Apr 28 12:22:39 PM PDT 24 2527165114 ps
T360 /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2940594990 Apr 28 12:23:50 PM PDT 24 Apr 28 12:24:12 PM PDT 24 70877631344 ps
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T768 /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.544057538 Apr 28 12:23:13 PM PDT 24 Apr 28 12:23:20 PM PDT 24 3246576897 ps
T123 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3183112266 Apr 28 12:23:36 PM PDT 24 Apr 28 12:25:34 PM PDT 24 42111960357 ps
T769 /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2126875776 Apr 28 12:22:01 PM PDT 24 Apr 28 12:22:06 PM PDT 24 10356884837 ps
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T771 /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3085205360 Apr 28 12:22:39 PM PDT 24 Apr 28 12:22:50 PM PDT 24 2469435555 ps
T772 /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3040105009 Apr 28 12:23:11 PM PDT 24 Apr 28 12:23:16 PM PDT 24 4842962574 ps
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T773 /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3392931921 Apr 28 12:22:44 PM PDT 24 Apr 28 12:23:06 PM PDT 24 5560077905 ps
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T776 /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.815520244 Apr 28 12:21:56 PM PDT 24 Apr 28 12:22:02 PM PDT 24 2257577914 ps
T777 /workspace/coverage/default/21.sysrst_ctrl_combo_detect.2279313225 Apr 28 12:23:05 PM PDT 24 Apr 28 12:25:00 PM PDT 24 43374131872 ps
T778 /workspace/coverage/default/28.sysrst_ctrl_smoke.2328762289 Apr 28 12:23:52 PM PDT 24 Apr 28 12:24:01 PM PDT 24 2110675996 ps
T779 /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3641499061 Apr 28 12:23:43 PM PDT 24 Apr 28 12:23:50 PM PDT 24 3215596908 ps
T780 /workspace/coverage/default/32.sysrst_ctrl_edge_detect.551725560 Apr 28 12:22:53 PM PDT 24 Apr 28 12:23:25 PM PDT 24 59615325085 ps
T781 /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2565117708 Apr 28 12:22:47 PM PDT 24 Apr 28 12:22:59 PM PDT 24 2530477597 ps
T782 /workspace/coverage/default/35.sysrst_ctrl_combo_detect.431251586 Apr 28 12:22:50 PM PDT 24 Apr 28 12:27:28 PM PDT 24 108193645907 ps
T783 /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.3507102599 Apr 28 12:20:18 PM PDT 24 Apr 28 12:20:26 PM PDT 24 2512388300 ps
T784 /workspace/coverage/default/49.sysrst_ctrl_smoke.4036432541 Apr 28 12:23:29 PM PDT 24 Apr 28 12:23:36 PM PDT 24 2108142294 ps
T785 /workspace/coverage/default/44.sysrst_ctrl_alert_test.394752285 Apr 28 12:23:21 PM PDT 24 Apr 28 12:23:23 PM PDT 24 2056891197 ps
T786 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3771184716 Apr 28 12:23:45 PM PDT 24 Apr 28 12:28:48 PM PDT 24 115079942057 ps
T787 /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.616876817 Apr 28 12:21:53 PM PDT 24 Apr 28 12:22:00 PM PDT 24 2445496147 ps
T788 /workspace/coverage/default/49.sysrst_ctrl_combo_detect.3815451814 Apr 28 12:23:38 PM PDT 24 Apr 28 12:24:21 PM PDT 24 51936237180 ps
T789 /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3847423584 Apr 28 12:23:02 PM PDT 24 Apr 28 12:24:06 PM PDT 24 89915195909 ps
T790 /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2865750058 Apr 28 12:23:58 PM PDT 24 Apr 28 12:24:09 PM PDT 24 2452668449 ps
T791 /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1415265819 Apr 28 12:21:51 PM PDT 24 Apr 28 12:21:59 PM PDT 24 2613752405 ps
T792 /workspace/coverage/default/0.sysrst_ctrl_smoke.4108189960 Apr 28 12:23:07 PM PDT 24 Apr 28 12:23:13 PM PDT 24 2137714007 ps
T202 /workspace/coverage/default/26.sysrst_ctrl_edge_detect.1444357451 Apr 28 12:22:37 PM PDT 24 Apr 28 12:22:55 PM PDT 24 5199358967 ps
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