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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.35 98.73 96.73 100.00 94.87 98.23 99.23 93.68


Total test records in report: 920
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T793 /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3040877480 Apr 28 12:25:12 PM PDT 24 Apr 28 12:26:58 PM PDT 24 68699787114 ps
T794 /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.1940498730 Apr 28 12:22:45 PM PDT 24 Apr 28 12:23:00 PM PDT 24 2217838021 ps
T795 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1896679747 Apr 28 12:19:40 PM PDT 24 Apr 28 12:19:43 PM PDT 24 2424240547 ps
T796 /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.1226892463 Apr 28 12:23:02 PM PDT 24 Apr 28 12:23:11 PM PDT 24 4883737031 ps
T797 /workspace/coverage/default/29.sysrst_ctrl_stress_all.4095205070 Apr 28 12:22:41 PM PDT 24 Apr 28 12:23:11 PM PDT 24 9662565403 ps
T25 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2806611706 Apr 28 12:16:59 PM PDT 24 Apr 28 12:17:02 PM PDT 24 2110397902 ps
T798 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.4027589915 Apr 28 12:22:58 PM PDT 24 Apr 28 12:23:14 PM PDT 24 2010584629 ps
T26 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3942918391 Apr 28 12:22:06 PM PDT 24 Apr 28 12:22:14 PM PDT 24 2075724907 ps
T27 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2103584748 Apr 28 12:20:17 PM PDT 24 Apr 28 12:20:21 PM PDT 24 2049625816 ps
T799 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2065766618 Apr 28 12:18:01 PM PDT 24 Apr 28 12:18:07 PM PDT 24 2008849348 ps
T298 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.744908517 Apr 28 12:21:09 PM PDT 24 Apr 28 12:21:12 PM PDT 24 2079974618 ps
T800 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3894466138 Apr 28 12:18:01 PM PDT 24 Apr 28 12:18:07 PM PDT 24 2014330071 ps
T19 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1646899675 Apr 28 12:21:52 PM PDT 24 Apr 28 12:22:01 PM PDT 24 7434703533 ps
T28 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3145251834 Apr 28 12:20:17 PM PDT 24 Apr 28 12:20:34 PM PDT 24 43382003687 ps
T311 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2144730345 Apr 28 12:21:54 PM PDT 24 Apr 28 12:22:01 PM PDT 24 2060175172 ps
T801 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.670792381 Apr 28 12:22:52 PM PDT 24 Apr 28 12:23:05 PM PDT 24 2059994951 ps
T802 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2182048072 Apr 28 12:18:52 PM PDT 24 Apr 28 12:18:54 PM PDT 24 2031961118 ps
T22 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1156471873 Apr 28 12:22:48 PM PDT 24 Apr 28 12:23:06 PM PDT 24 7165197765 ps
T243 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3695281288 Apr 28 12:19:12 PM PDT 24 Apr 28 12:19:44 PM PDT 24 42895032286 ps
T249 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1128778634 Apr 28 12:19:23 PM PDT 24 Apr 28 12:19:28 PM PDT 24 2167208464 ps
T314 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.3843276585 Apr 28 12:17:11 PM PDT 24 Apr 28 12:17:19 PM PDT 24 6017699410 ps
T803 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2547532346 Apr 28 12:22:15 PM PDT 24 Apr 28 12:22:21 PM PDT 24 2023571665 ps
T290 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3072133361 Apr 28 12:22:02 PM PDT 24 Apr 28 12:22:08 PM PDT 24 2086965744 ps
T20 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3525793230 Apr 28 12:22:13 PM PDT 24 Apr 28 12:22:19 PM PDT 24 4818024246 ps
T21 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.4160815371 Apr 28 12:21:53 PM PDT 24 Apr 28 12:22:04 PM PDT 24 5133787265 ps
T256 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2034334545 Apr 28 12:23:29 PM PDT 24 Apr 28 12:23:33 PM PDT 24 2240390739 ps
T804 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1976775379 Apr 28 12:22:13 PM PDT 24 Apr 28 12:22:22 PM PDT 24 2009995752 ps
T247 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.219650870 Apr 28 12:22:40 PM PDT 24 Apr 28 12:23:46 PM PDT 24 22246209730 ps
T312 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.889451675 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:28 PM PDT 24 4992903843 ps
T244 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3927775205 Apr 28 12:18:14 PM PDT 24 Apr 28 12:18:33 PM PDT 24 42654307458 ps
T805 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1203014587 Apr 28 12:23:07 PM PDT 24 Apr 28 12:23:14 PM PDT 24 2047951116 ps
T299 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3244244340 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:16 PM PDT 24 2672981856 ps
T313 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3777624354 Apr 28 12:18:41 PM PDT 24 Apr 28 12:19:03 PM PDT 24 5390241064 ps
T255 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2328503453 Apr 28 12:17:21 PM PDT 24 Apr 28 12:17:51 PM PDT 24 22219976351 ps
T250 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2438058188 Apr 28 12:17:00 PM PDT 24 Apr 28 12:17:07 PM PDT 24 2029581066 ps
T806 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.985740759 Apr 28 12:18:33 PM PDT 24 Apr 28 12:18:40 PM PDT 24 2012029109 ps
T807 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1168420759 Apr 28 12:22:09 PM PDT 24 Apr 28 12:23:12 PM PDT 24 22236890492 ps
T251 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2511737468 Apr 28 12:22:41 PM PDT 24 Apr 28 12:22:51 PM PDT 24 2492273450 ps
T808 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1209806719 Apr 28 12:22:07 PM PDT 24 Apr 28 12:22:27 PM PDT 24 22424394683 ps
T809 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1708570854 Apr 28 12:17:00 PM PDT 24 Apr 28 12:17:04 PM PDT 24 2018064742 ps
T300 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3998520455 Apr 28 12:19:24 PM PDT 24 Apr 28 12:19:49 PM PDT 24 38672722819 ps
T810 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2944802991 Apr 28 12:22:42 PM PDT 24 Apr 28 12:22:52 PM PDT 24 2074268657 ps
T811 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1107962267 Apr 28 12:17:49 PM PDT 24 Apr 28 12:17:56 PM PDT 24 4745528651 ps
T254 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1613576406 Apr 28 12:22:07 PM PDT 24 Apr 28 12:22:13 PM PDT 24 2072573339 ps
T812 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.191283489 Apr 28 12:22:09 PM PDT 24 Apr 28 12:22:13 PM PDT 24 2036427832 ps
T813 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2010082777 Apr 28 12:20:11 PM PDT 24 Apr 28 12:20:13 PM PDT 24 2027376999 ps
T814 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.651687791 Apr 28 12:20:34 PM PDT 24 Apr 28 12:20:37 PM PDT 24 2245852423 ps
T815 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.776757360 Apr 28 12:17:13 PM PDT 24 Apr 28 12:17:31 PM PDT 24 7803850970 ps
T816 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.65164469 Apr 28 12:21:59 PM PDT 24 Apr 28 12:22:07 PM PDT 24 2012784663 ps
T817 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2581024126 Apr 28 12:22:02 PM PDT 24 Apr 28 12:22:12 PM PDT 24 2075214544 ps
T818 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3263807292 Apr 28 12:18:01 PM PDT 24 Apr 28 12:18:04 PM PDT 24 2030409909 ps
T819 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1871656940 Apr 28 12:22:36 PM PDT 24 Apr 28 12:22:48 PM PDT 24 2012130891 ps
T820 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1256190797 Apr 28 12:22:10 PM PDT 24 Apr 28 12:22:15 PM PDT 24 2048152545 ps
T821 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.859790972 Apr 28 12:22:52 PM PDT 24 Apr 28 12:23:10 PM PDT 24 2013858764 ps
T258 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.4101294855 Apr 28 12:22:34 PM PDT 24 Apr 28 12:22:41 PM PDT 24 2508256377 ps
T822 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.896969786 Apr 28 12:23:30 PM PDT 24 Apr 28 12:25:20 PM PDT 24 42453167097 ps
T257 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1317700808 Apr 28 12:23:07 PM PDT 24 Apr 28 12:23:14 PM PDT 24 3577598619 ps
T301 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.489548936 Apr 28 12:19:35 PM PDT 24 Apr 28 12:19:42 PM PDT 24 2041105645 ps
T823 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2476136772 Apr 28 12:22:52 PM PDT 24 Apr 28 12:23:08 PM PDT 24 2017086221 ps
T824 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2225749294 Apr 28 12:22:53 PM PDT 24 Apr 28 12:23:06 PM PDT 24 2045876341 ps
T302 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.731873460 Apr 28 12:17:10 PM PDT 24 Apr 28 12:17:18 PM PDT 24 6088690007 ps
T825 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3008830524 Apr 28 12:17:11 PM PDT 24 Apr 28 12:17:15 PM PDT 24 2139326701 ps
T259 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1472636981 Apr 28 12:21:25 PM PDT 24 Apr 28 12:21:30 PM PDT 24 2623750894 ps
T826 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.861328522 Apr 28 12:22:04 PM PDT 24 Apr 28 12:22:15 PM PDT 24 2050116101 ps
T827 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3445306372 Apr 28 12:17:11 PM PDT 24 Apr 28 12:20:21 PM PDT 24 75632957818 ps
T828 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1508322737 Apr 28 12:18:09 PM PDT 24 Apr 28 12:18:11 PM PDT 24 2153137099 ps
T829 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.475310991 Apr 28 12:21:55 PM PDT 24 Apr 28 12:22:00 PM PDT 24 2488015279 ps
T303 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.802677385 Apr 28 12:22:19 PM PDT 24 Apr 28 12:22:23 PM PDT 24 2069255451 ps
T830 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.146813534 Apr 28 12:20:22 PM PDT 24 Apr 28 12:20:28 PM PDT 24 2029801977 ps
T304 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.676093091 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:16 PM PDT 24 2074193699 ps
T831 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.532309792 Apr 28 12:18:56 PM PDT 24 Apr 28 12:18:57 PM PDT 24 2080883680 ps
T832 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3004524500 Apr 28 12:21:54 PM PDT 24 Apr 28 12:22:05 PM PDT 24 2100254771 ps
T305 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3165453750 Apr 28 12:18:03 PM PDT 24 Apr 28 12:18:10 PM PDT 24 2056156334 ps
T833 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2573183800 Apr 28 12:19:32 PM PDT 24 Apr 28 12:20:32 PM PDT 24 22241358930 ps
T306 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.466805871 Apr 28 12:19:51 PM PDT 24 Apr 28 12:19:54 PM PDT 24 2078402442 ps
T834 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3901353418 Apr 28 12:22:14 PM PDT 24 Apr 28 12:22:24 PM PDT 24 2008013599 ps
T835 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3094118679 Apr 28 12:22:14 PM PDT 24 Apr 28 12:22:19 PM PDT 24 2031412662 ps
T836 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.590609723 Apr 28 12:22:47 PM PDT 24 Apr 28 12:23:26 PM PDT 24 22273704153 ps
T837 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.4259662435 Apr 28 12:17:10 PM PDT 24 Apr 28 12:17:17 PM PDT 24 2011979502 ps
T838 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.140476891 Apr 28 12:24:25 PM PDT 24 Apr 28 12:24:31 PM PDT 24 2122696256 ps
T839 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.4100107947 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:19 PM PDT 24 2192111093 ps
T840 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1470416129 Apr 28 12:22:04 PM PDT 24 Apr 28 12:22:12 PM PDT 24 8109231908 ps
T841 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.319238980 Apr 28 12:17:59 PM PDT 24 Apr 28 12:18:05 PM PDT 24 2017263671 ps
T842 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2359546824 Apr 28 12:21:54 PM PDT 24 Apr 28 12:22:01 PM PDT 24 2556583421 ps
T843 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3858455790 Apr 28 12:17:10 PM PDT 24 Apr 28 12:17:45 PM PDT 24 9384085234 ps
T844 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.711500475 Apr 28 12:18:57 PM PDT 24 Apr 28 12:19:01 PM PDT 24 2015776269 ps
T845 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.305715077 Apr 28 12:17:13 PM PDT 24 Apr 28 12:17:21 PM PDT 24 2113605503 ps
T846 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3505964533 Apr 28 12:18:51 PM PDT 24 Apr 28 12:18:58 PM PDT 24 2015151885 ps
T847 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2394262454 Apr 28 12:17:13 PM PDT 24 Apr 28 12:17:22 PM PDT 24 3258068693 ps
T848 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.558146681 Apr 28 12:22:47 PM PDT 24 Apr 28 12:23:00 PM PDT 24 2050505149 ps
T849 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3855805564 Apr 28 12:21:55 PM PDT 24 Apr 28 12:22:05 PM PDT 24 2012942995 ps
T307 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4213495898 Apr 28 12:17:13 PM PDT 24 Apr 28 12:18:07 PM PDT 24 75521402739 ps
T850 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.599264210 Apr 28 12:22:02 PM PDT 24 Apr 28 12:22:12 PM PDT 24 2102693967 ps
T851 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3062758505 Apr 28 12:21:54 PM PDT 24 Apr 28 12:22:05 PM PDT 24 2052826165 ps
T852 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1218667999 Apr 28 12:22:13 PM PDT 24 Apr 28 12:24:04 PM PDT 24 42459521672 ps
T853 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2079353737 Apr 28 12:18:12 PM PDT 24 Apr 28 12:18:18 PM PDT 24 2010599670 ps
T854 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1972512214 Apr 28 12:22:21 PM PDT 24 Apr 28 12:22:28 PM PDT 24 2128338836 ps
T855 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3755310820 Apr 28 12:22:12 PM PDT 24 Apr 28 12:22:29 PM PDT 24 9941838182 ps
T333 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2981548772 Apr 28 12:22:39 PM PDT 24 Apr 28 12:23:17 PM PDT 24 42799921753 ps
T856 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.868206958 Apr 28 12:22:15 PM PDT 24 Apr 28 12:22:20 PM PDT 24 2044413619 ps
T857 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3347082507 Apr 28 12:22:08 PM PDT 24 Apr 28 12:22:19 PM PDT 24 10474722487 ps
T858 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1313045897 Apr 28 12:22:20 PM PDT 24 Apr 28 12:22:45 PM PDT 24 22249692113 ps
T308 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1076120964 Apr 28 12:17:00 PM PDT 24 Apr 28 12:17:06 PM PDT 24 2051601046 ps
T859 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.643986153 Apr 28 12:20:53 PM PDT 24 Apr 28 12:20:59 PM PDT 24 2017847769 ps
T860 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.78547583 Apr 28 12:17:11 PM PDT 24 Apr 28 12:17:14 PM PDT 24 2402721321 ps
T861 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1346198568 Apr 28 12:22:20 PM PDT 24 Apr 28 12:22:27 PM PDT 24 2010818961 ps
T862 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.969683278 Apr 28 12:17:13 PM PDT 24 Apr 28 12:17:36 PM PDT 24 5553737215 ps
T863 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2470930699 Apr 28 12:22:42 PM PDT 24 Apr 28 12:22:54 PM PDT 24 5200725620 ps
T864 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2700436985 Apr 28 12:22:15 PM PDT 24 Apr 28 12:22:20 PM PDT 24 2048219732 ps
T865 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1401017140 Apr 28 12:22:13 PM PDT 24 Apr 28 12:22:21 PM PDT 24 2076994090 ps
T866 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.189881553 Apr 28 12:22:04 PM PDT 24 Apr 28 12:22:07 PM PDT 24 2215950185 ps
T867 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1011522910 Apr 28 12:22:20 PM PDT 24 Apr 28 12:22:23 PM PDT 24 2030206400 ps
T868 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.480937377 Apr 28 12:17:11 PM PDT 24 Apr 28 12:17:23 PM PDT 24 4027280170 ps
T869 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1935821453 Apr 28 12:22:52 PM PDT 24 Apr 28 12:23:04 PM PDT 24 2038595079 ps
T870 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3448751350 Apr 28 12:17:10 PM PDT 24 Apr 28 12:18:55 PM PDT 24 38146641140 ps
T871 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2532631179 Apr 28 12:22:04 PM PDT 24 Apr 28 12:22:14 PM PDT 24 2060645123 ps
T309 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2066067255 Apr 28 12:22:39 PM PDT 24 Apr 28 12:22:50 PM PDT 24 2021972501 ps
T872 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.4029236476 Apr 28 12:22:50 PM PDT 24 Apr 28 12:23:04 PM PDT 24 2309064859 ps
T873 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1843230971 Apr 28 12:17:23 PM PDT 24 Apr 28 12:17:29 PM PDT 24 2085768421 ps
T874 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.291092196 Apr 28 12:20:42 PM PDT 24 Apr 28 12:20:49 PM PDT 24 2020015188 ps
T875 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.692950829 Apr 28 12:17:59 PM PDT 24 Apr 28 12:18:02 PM PDT 24 2275473282 ps
T876 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.985032650 Apr 28 12:22:50 PM PDT 24 Apr 28 12:23:08 PM PDT 24 2678408523 ps
T877 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1836580667 Apr 28 12:22:38 PM PDT 24 Apr 28 12:22:45 PM PDT 24 2122882414 ps
T878 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3030795834 Apr 28 12:17:06 PM PDT 24 Apr 28 12:17:12 PM PDT 24 3368952972 ps
T335 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3459294690 Apr 28 12:22:51 PM PDT 24 Apr 28 12:23:31 PM PDT 24 42507182622 ps
T879 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1237927686 Apr 28 12:18:01 PM PDT 24 Apr 28 12:18:03 PM PDT 24 2043777385 ps
T880 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2482083287 Apr 28 12:18:50 PM PDT 24 Apr 28 12:18:53 PM PDT 24 2026897927 ps
T881 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2232810701 Apr 28 12:22:14 PM PDT 24 Apr 28 12:22:19 PM PDT 24 2022941296 ps
T882 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1855437151 Apr 28 12:21:59 PM PDT 24 Apr 28 12:22:07 PM PDT 24 2013243696 ps
T883 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2267204110 Apr 28 12:22:53 PM PDT 24 Apr 28 12:23:10 PM PDT 24 2016602780 ps
T310 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2038702431 Apr 28 12:19:14 PM PDT 24 Apr 28 12:19:23 PM PDT 24 2432277206 ps
T884 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2374317383 Apr 28 12:22:02 PM PDT 24 Apr 28 12:22:07 PM PDT 24 2120800766 ps
T885 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.996364591 Apr 28 12:22:02 PM PDT 24 Apr 28 12:22:19 PM PDT 24 4623079740 ps
T886 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1881509485 Apr 28 12:17:49 PM PDT 24 Apr 28 12:17:52 PM PDT 24 2034486991 ps
T887 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.4063582568 Apr 28 12:22:52 PM PDT 24 Apr 28 12:24:03 PM PDT 24 42381634855 ps
T888 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.4235033853 Apr 28 12:22:21 PM PDT 24 Apr 28 12:22:54 PM PDT 24 22203645292 ps
T889 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.4019293713 Apr 28 12:22:58 PM PDT 24 Apr 28 12:23:14 PM PDT 24 2008747902 ps
T890 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.645029318 Apr 28 12:17:10 PM PDT 24 Apr 28 12:17:14 PM PDT 24 2164552972 ps
T891 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3421691029 Apr 28 12:20:33 PM PDT 24 Apr 28 12:20:36 PM PDT 24 2025037948 ps
T892 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1878492940 Apr 28 12:18:14 PM PDT 24 Apr 28 12:18:31 PM PDT 24 6022915616 ps
T893 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.742182928 Apr 28 12:22:05 PM PDT 24 Apr 28 12:22:10 PM PDT 24 2040928399 ps
T894 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1637139749 Apr 28 12:22:38 PM PDT 24 Apr 28 12:22:49 PM PDT 24 2009491874 ps
T895 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3957807200 Apr 28 12:19:57 PM PDT 24 Apr 28 12:20:04 PM PDT 24 2074375968 ps
T896 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3953799702 Apr 28 12:22:38 PM PDT 24 Apr 28 12:22:47 PM PDT 24 2121689836 ps
T897 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.514994604 Apr 28 12:17:12 PM PDT 24 Apr 28 12:17:22 PM PDT 24 2949290683 ps
T334 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1926212290 Apr 28 12:18:21 PM PDT 24 Apr 28 12:18:32 PM PDT 24 45019227982 ps
T898 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.365045405 Apr 28 12:22:09 PM PDT 24 Apr 28 12:22:36 PM PDT 24 8715842283 ps
T899 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2187469769 Apr 28 12:20:25 PM PDT 24 Apr 28 12:20:30 PM PDT 24 2082559873 ps
T900 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.521979186 Apr 28 12:17:10 PM PDT 24 Apr 28 12:17:20 PM PDT 24 6036964412 ps
T901 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1455046531 Apr 28 12:22:16 PM PDT 24 Apr 28 12:22:22 PM PDT 24 2026029858 ps
T902 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1233442343 Apr 28 12:22:49 PM PDT 24 Apr 28 12:23:12 PM PDT 24 7733240643 ps
T903 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.971462592 Apr 28 12:19:33 PM PDT 24 Apr 28 12:19:50 PM PDT 24 22576347961 ps
T904 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3055448946 Apr 28 12:19:50 PM PDT 24 Apr 28 12:20:04 PM PDT 24 9475258921 ps
T905 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.275856089 Apr 28 12:18:00 PM PDT 24 Apr 28 12:18:04 PM PDT 24 2020683300 ps
T906 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3783077814 Apr 28 12:22:09 PM PDT 24 Apr 28 12:22:15 PM PDT 24 2160602178 ps
T907 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.20886304 Apr 28 12:22:12 PM PDT 24 Apr 28 12:22:22 PM PDT 24 2015271875 ps
T908 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3458568082 Apr 28 12:20:17 PM PDT 24 Apr 28 12:20:27 PM PDT 24 4411506005 ps
T336 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2667896101 Apr 28 12:16:59 PM PDT 24 Apr 28 12:18:47 PM PDT 24 42376512285 ps
T909 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.4272613612 Apr 28 12:22:53 PM PDT 24 Apr 28 12:23:10 PM PDT 24 2099672224 ps
T910 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1575891048 Apr 28 12:22:04 PM PDT 24 Apr 28 12:22:10 PM PDT 24 2021564666 ps
T911 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.957221114 Apr 28 12:19:24 PM PDT 24 Apr 28 12:19:30 PM PDT 24 2010828902 ps
T912 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.853851700 Apr 28 12:21:06 PM PDT 24 Apr 28 12:21:13 PM PDT 24 2046475501 ps
T913 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1565782960 Apr 28 12:20:42 PM PDT 24 Apr 28 12:20:45 PM PDT 24 2216145069 ps
T914 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3420537112 Apr 28 12:19:26 PM PDT 24 Apr 28 12:21:27 PM PDT 24 42451849185 ps
T915 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1379210673 Apr 28 12:22:10 PM PDT 24 Apr 28 12:22:19 PM PDT 24 2033588382 ps
T916 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3287797907 Apr 28 12:17:59 PM PDT 24 Apr 28 12:18:07 PM PDT 24 2110518721 ps
T917 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2658875044 Apr 28 12:23:00 PM PDT 24 Apr 28 12:23:13 PM PDT 24 2132733634 ps
T918 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.527640771 Apr 28 12:22:03 PM PDT 24 Apr 28 12:22:28 PM PDT 24 7802588831 ps
T919 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.954666080 Apr 28 12:22:03 PM PDT 24 Apr 28 12:22:12 PM PDT 24 2035631192 ps
T920 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.74288217 Apr 28 12:23:35 PM PDT 24 Apr 28 12:23:39 PM PDT 24 2357728587 ps

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3757843485
Short name T6
Test name
Test status
Simulation time 384874820074 ps
CPU time 38.02 seconds
Started Apr 28 12:23:05 PM PDT 24
Finished Apr 28 12:23:49 PM PDT 24
Peak memory 212288 kb
Host smart-e01f1051-34c1-4576-bec2-1a95f7f74b70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757843485 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.3757843485
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2294154252
Short name T7
Test name
Test status
Simulation time 117639947129 ps
CPU time 315.18 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:28:18 PM PDT 24
Peak memory 201820 kb
Host smart-759eac50-c467-4539-9fe4-324a2e493e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294154252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.2294154252
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.122961797
Short name T38
Test name
Test status
Simulation time 130812637640 ps
CPU time 59.82 seconds
Started Apr 28 12:20:37 PM PDT 24
Finished Apr 28 12:21:37 PM PDT 24
Peak memory 218520 kb
Host smart-d5d0eb8e-99e9-4852-b9fb-73237637938d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122961797 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.122961797
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3216418147
Short name T39
Test name
Test status
Simulation time 116906529717 ps
CPU time 43.55 seconds
Started Apr 28 12:22:39 PM PDT 24
Finished Apr 28 12:23:28 PM PDT 24
Peak memory 210496 kb
Host smart-e2a7797a-f3b5-42b3-8a4b-7906249855b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216418147 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.3216418147
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.4279922380
Short name T269
Test name
Test status
Simulation time 26438061945 ps
CPU time 35.42 seconds
Started Apr 28 12:19:14 PM PDT 24
Finished Apr 28 12:19:50 PM PDT 24
Peak memory 210380 kb
Host smart-f48197c2-d1b9-409c-ae51-68a26c511495
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279922380 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.4279922380
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.2745900952
Short name T33
Test name
Test status
Simulation time 3922854238 ps
CPU time 4.82 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:22:57 PM PDT 24
Peak memory 201772 kb
Host smart-d509234a-6522-4fb5-89e6-bc32889f8638
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745900952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.2745900952
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3145251834
Short name T28
Test name
Test status
Simulation time 43382003687 ps
CPU time 16.25 seconds
Started Apr 28 12:20:17 PM PDT 24
Finished Apr 28 12:20:34 PM PDT 24
Peak memory 201808 kb
Host smart-b30dd710-4ea8-492d-9a49-b9ffd2011d0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145251834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.3145251834
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.755311497
Short name T54
Test name
Test status
Simulation time 33589763052 ps
CPU time 85.85 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:23:43 PM PDT 24
Peak memory 201632 kb
Host smart-32168c9d-3fe3-42d0-8a63-df9d8c66cf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755311497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.755311497
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2603759617
Short name T220
Test name
Test status
Simulation time 122223609158 ps
CPU time 302.96 seconds
Started Apr 28 12:20:21 PM PDT 24
Finished Apr 28 12:25:24 PM PDT 24
Peak memory 202028 kb
Host smart-9d26bf55-db38-40c2-8c99-5784d28af29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603759617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.2603759617
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1998382907
Short name T121
Test name
Test status
Simulation time 273368755133 ps
CPU time 81.72 seconds
Started Apr 28 12:23:07 PM PDT 24
Finished Apr 28 12:24:33 PM PDT 24
Peak memory 218124 kb
Host smart-e83ac6c0-c0fe-4795-9a39-b6ef8dbf0ccf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998382907 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.1998382907
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.4126362414
Short name T78
Test name
Test status
Simulation time 192640708264 ps
CPU time 83.03 seconds
Started Apr 28 12:22:03 PM PDT 24
Finished Apr 28 12:23:29 PM PDT 24
Peak memory 216720 kb
Host smart-87e426b6-b988-4ae6-b9f4-7b1869d17d58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126362414 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.4126362414
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.648179087
Short name T83
Test name
Test status
Simulation time 96233423800 ps
CPU time 57.35 seconds
Started Apr 28 12:22:28 PM PDT 24
Finished Apr 28 12:23:26 PM PDT 24
Peak memory 218504 kb
Host smart-d180543c-0a50-401a-8278-efdd0e2ff07d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648179087 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.648179087
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3369335382
Short name T218
Test name
Test status
Simulation time 109431728084 ps
CPU time 150.27 seconds
Started Apr 28 12:23:44 PM PDT 24
Finished Apr 28 12:26:17 PM PDT 24
Peak memory 201852 kb
Host smart-28d31be5-84ea-4792-a82e-6e4d2317cde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369335382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.3369335382
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1303892192
Short name T175
Test name
Test status
Simulation time 115055186595 ps
CPU time 44.18 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:23:33 PM PDT 24
Peak memory 210520 kb
Host smart-5aaded77-42f6-4b7a-846a-0745184ddad2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303892192 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.1303892192
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.3229950087
Short name T160
Test name
Test status
Simulation time 42469262726 ps
CPU time 15.75 seconds
Started Apr 28 12:21:55 PM PDT 24
Finished Apr 28 12:22:15 PM PDT 24
Peak memory 221336 kb
Host smart-97bdddaf-29fd-475e-af10-50e86e344e75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229950087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.3229950087
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1679500940
Short name T2
Test name
Test status
Simulation time 959441847551 ps
CPU time 73.09 seconds
Started Apr 28 12:22:00 PM PDT 24
Finished Apr 28 12:23:16 PM PDT 24
Peak memory 217192 kb
Host smart-5a270597-53ab-4d2f-b84b-bc4ebe72c9b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679500940 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.1679500940
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.1399040132
Short name T174
Test name
Test status
Simulation time 423275117550 ps
CPU time 288.15 seconds
Started Apr 28 12:22:21 PM PDT 24
Finished Apr 28 12:27:10 PM PDT 24
Peak memory 201448 kb
Host smart-dbc0f9cf-598c-4f91-8ac3-dfc3a69f8737
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399040132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.1399040132
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.4261759473
Short name T144
Test name
Test status
Simulation time 5316947231 ps
CPU time 2.34 seconds
Started Apr 28 12:21:44 PM PDT 24
Finished Apr 28 12:21:47 PM PDT 24
Peak memory 201748 kb
Host smart-bdb41ac6-8034-4764-b943-b688ff6f06f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261759473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.4261759473
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.515756107
Short name T222
Test name
Test status
Simulation time 178634997738 ps
CPU time 438.45 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:30:19 PM PDT 24
Peak memory 201932 kb
Host smart-d6a53850-84dc-4fb0-ba5a-db252c581c51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515756107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_combo_detect.515756107
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.4070050255
Short name T73
Test name
Test status
Simulation time 8871042777 ps
CPU time 2.37 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 200980 kb
Host smart-fb363b2b-0256-4064-9eba-6328fc9bc037
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070050255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.4070050255
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2511737468
Short name T251
Test name
Test status
Simulation time 2492273450 ps
CPU time 4.1 seconds
Started Apr 28 12:22:41 PM PDT 24
Finished Apr 28 12:22:51 PM PDT 24
Peak memory 209092 kb
Host smart-999e7055-9e60-4448-8b17-da250067ca7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511737468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.2511737468
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3140409026
Short name T236
Test name
Test status
Simulation time 219287832758 ps
CPU time 146.47 seconds
Started Apr 28 12:24:01 PM PDT 24
Finished Apr 28 12:26:32 PM PDT 24
Peak memory 201992 kb
Host smart-53a51fc1-428b-4f5e-ab11-a945793371f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140409026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.3140409026
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.3910451154
Short name T85
Test name
Test status
Simulation time 3587098149 ps
CPU time 3.47 seconds
Started Apr 28 12:20:45 PM PDT 24
Finished Apr 28 12:20:49 PM PDT 24
Peak memory 201640 kb
Host smart-bf0f6ccd-3801-4dbe-913d-1b78461d71ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910451154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.3910451154
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.575292750
Short name T34
Test name
Test status
Simulation time 4480600019 ps
CPU time 3.12 seconds
Started Apr 28 12:17:34 PM PDT 24
Finished Apr 28 12:17:37 PM PDT 24
Peak memory 201724 kb
Host smart-994d766f-8568-4380-a0ea-c1a75bd79809
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575292750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_edge_detect.575292750
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.2307364691
Short name T84
Test name
Test status
Simulation time 3786532669 ps
CPU time 1.96 seconds
Started Apr 28 12:23:18 PM PDT 24
Finished Apr 28 12:23:21 PM PDT 24
Peak memory 201636 kb
Host smart-6edfe5c8-2093-4112-a528-a87a7545fae5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307364691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.2307364691
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1058013042
Short name T323
Test name
Test status
Simulation time 110409074872 ps
CPU time 69.6 seconds
Started Apr 28 12:23:19 PM PDT 24
Finished Apr 28 12:24:30 PM PDT 24
Peak memory 201884 kb
Host smart-ea036ef3-a7b6-4401-a19d-7eeea3fb6864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058013042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.1058013042
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.744908517
Short name T298
Test name
Test status
Simulation time 2079974618 ps
CPU time 2.27 seconds
Started Apr 28 12:21:09 PM PDT 24
Finished Apr 28 12:21:12 PM PDT 24
Peak memory 201584 kb
Host smart-6b579b67-f1f5-4d2d-a28c-90db3aa48b54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744908517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_r
w.744908517
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.883569571
Short name T1
Test name
Test status
Simulation time 38729261064 ps
CPU time 27.43 seconds
Started Apr 28 12:22:41 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 201952 kb
Host smart-49d66753-d849-4357-b5a8-23040abbb623
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883569571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_combo_detect.883569571
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.3078362741
Short name T321
Test name
Test status
Simulation time 154359696688 ps
CPU time 415.06 seconds
Started Apr 28 12:19:42 PM PDT 24
Finished Apr 28 12:26:37 PM PDT 24
Peak memory 201988 kb
Host smart-4919b750-653b-43c0-adda-8a3f12fbfdc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078362741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.3078362741
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1066051722
Short name T48
Test name
Test status
Simulation time 26588561683 ps
CPU time 30.69 seconds
Started Apr 28 12:24:44 PM PDT 24
Finished Apr 28 12:25:16 PM PDT 24
Peak memory 199808 kb
Host smart-e7b9bd0a-95ff-44c2-a775-2f82810fbc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066051722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.1066051722
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.1835353481
Short name T378
Test name
Test status
Simulation time 2009865802 ps
CPU time 5.83 seconds
Started Apr 28 12:20:25 PM PDT 24
Finished Apr 28 12:20:32 PM PDT 24
Peak memory 201792 kb
Host smart-4d8e9f1f-0d61-40c1-a215-5087484d5696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835353481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.1835353481
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2353801594
Short name T65
Test name
Test status
Simulation time 41368889683 ps
CPU time 25.16 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:26 PM PDT 24
Peak memory 210372 kb
Host smart-97b91466-8c99-41f1-8c7f-53a3c4ebd005
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353801594 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.2353801594
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1503760600
Short name T76
Test name
Test status
Simulation time 71591884908 ps
CPU time 196 seconds
Started Apr 28 12:23:46 PM PDT 24
Finished Apr 28 12:27:05 PM PDT 24
Peak memory 201868 kb
Host smart-9bc2dce4-487b-4ede-95e4-7f7833ba93af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503760600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.1503760600
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.446240914
Short name T339
Test name
Test status
Simulation time 48962492434 ps
CPU time 14.61 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 201528 kb
Host smart-4b4dfe60-a94d-40ac-8ad6-9f51a45efd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446240914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_wi
th_pre_cond.446240914
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.3918708915
Short name T280
Test name
Test status
Simulation time 115871488837 ps
CPU time 112.34 seconds
Started Apr 28 12:24:30 PM PDT 24
Finished Apr 28 12:26:26 PM PDT 24
Peak memory 201952 kb
Host smart-25bb5b51-5e77-4fb4-8103-9bbde753f371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918708915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.3918708915
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.776757360
Short name T815
Test name
Test status
Simulation time 7803850970 ps
CPU time 15.86 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:17:31 PM PDT 24
Peak memory 201596 kb
Host smart-c19a3d90-b4c0-4b23-82c6-ff48a78f29a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776757360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
sysrst_ctrl_same_csr_outstanding.776757360
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.3664062309
Short name T133
Test name
Test status
Simulation time 2140554041371 ps
CPU time 295.76 seconds
Started Apr 28 12:22:46 PM PDT 24
Finished Apr 28 12:27:52 PM PDT 24
Peak memory 212404 kb
Host smart-b3794951-cd8b-476e-8c6f-bfc9dfbcb851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664062309 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.3664062309
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3160897877
Short name T196
Test name
Test status
Simulation time 46574558524 ps
CPU time 102.89 seconds
Started Apr 28 12:21:13 PM PDT 24
Finished Apr 28 12:22:57 PM PDT 24
Peak memory 202004 kb
Host smart-03fa0b87-52d8-466e-86b0-844b37010ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160897877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.3160897877
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.757006016
Short name T330
Test name
Test status
Simulation time 111691641497 ps
CPU time 40.75 seconds
Started Apr 28 12:23:31 PM PDT 24
Finished Apr 28 12:24:12 PM PDT 24
Peak memory 201852 kb
Host smart-18f5690c-1484-445b-9bed-76787e953b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757006016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_wi
th_pre_cond.757006016
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1128778634
Short name T249
Test name
Test status
Simulation time 2167208464 ps
CPU time 3.74 seconds
Started Apr 28 12:19:23 PM PDT 24
Finished Apr 28 12:19:28 PM PDT 24
Peak memory 209940 kb
Host smart-4d36c2c5-d6e0-4799-ac24-083d7a481165
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128778634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.1128778634
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2472397730
Short name T77
Test name
Test status
Simulation time 3378621505 ps
CPU time 5.04 seconds
Started Apr 28 12:23:33 PM PDT 24
Finished Apr 28 12:23:38 PM PDT 24
Peak memory 201756 kb
Host smart-a745c927-b84e-4224-871b-e6da0695a703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472397730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2
472397730
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1550221789
Short name T343
Test name
Test status
Simulation time 70370927355 ps
CPU time 166.96 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:24:54 PM PDT 24
Peak memory 201964 kb
Host smart-3d8ce93c-9e80-4a27-bdaa-2fadbf8642a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550221789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.1550221789
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3339809727
Short name T328
Test name
Test status
Simulation time 86981879610 ps
CPU time 58.84 seconds
Started Apr 28 12:22:30 PM PDT 24
Finished Apr 28 12:23:30 PM PDT 24
Peak memory 201928 kb
Host smart-a3862f19-3562-4d5a-b7e9-b1a44588a015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339809727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.3339809727
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.15165415
Short name T226
Test name
Test status
Simulation time 66887979170 ps
CPU time 43.05 seconds
Started Apr 28 12:23:39 PM PDT 24
Finished Apr 28 12:24:23 PM PDT 24
Peak memory 202020 kb
Host smart-c9539043-ea0b-4338-ad8f-3f4f237c4dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15165415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_wit
h_pre_cond.15165415
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.4238388388
Short name T329
Test name
Test status
Simulation time 80540023633 ps
CPU time 218.44 seconds
Started Apr 28 12:23:43 PM PDT 24
Finished Apr 28 12:27:24 PM PDT 24
Peak memory 202012 kb
Host smart-4267f6ca-9f1e-4f68-a7f2-9371af58b06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238388388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.4238388388
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3244244340
Short name T299
Test name
Test status
Simulation time 2672981856 ps
CPU time 2.42 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:16 PM PDT 24
Peak memory 200504 kb
Host smart-dfaa010e-f95f-48cf-b5a9-1699d9adb7c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244244340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_aliasing.3244244340
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1926212290
Short name T334
Test name
Test status
Simulation time 45019227982 ps
CPU time 11.16 seconds
Started Apr 28 12:18:21 PM PDT 24
Finished Apr 28 12:18:32 PM PDT 24
Peak memory 201868 kb
Host smart-c830b198-abe0-4d70-8f7c-eacfd56d7fad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926212290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.1926212290
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.666900209
Short name T93
Test name
Test status
Simulation time 114892428229 ps
CPU time 175.91 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:24:50 PM PDT 24
Peak memory 200872 kb
Host smart-d0f7be9c-dfa5-4153-92e5-d0091df963fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666900209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_wi
th_pre_cond.666900209
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.4133158755
Short name T322
Test name
Test status
Simulation time 100644592562 ps
CPU time 134.32 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:25:17 PM PDT 24
Peak memory 201764 kb
Host smart-23dbf10c-5db4-41e0-adef-acd5d6a58b26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133158755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.4133158755
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2075864603
Short name T214
Test name
Test status
Simulation time 59720717168 ps
CPU time 172.67 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:25:52 PM PDT 24
Peak memory 202096 kb
Host smart-6cebac77-47ec-4e3b-a361-5693d99c0760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075864603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.2075864603
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2464907934
Short name T53
Test name
Test status
Simulation time 37473420011 ps
CPU time 47.89 seconds
Started Apr 28 12:20:29 PM PDT 24
Finished Apr 28 12:21:17 PM PDT 24
Peak memory 201756 kb
Host smart-ff857691-1f5b-4e7f-9d32-ed38296b976d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464907934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.2464907934
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.2058943
Short name T224
Test name
Test status
Simulation time 87612870350 ps
CPU time 59.58 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:24:01 PM PDT 24
Peak memory 201964 kb
Host smart-43940f91-5bde-4b15-9e40-93151caf614a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
combo_detect.2058943
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3353065165
Short name T80
Test name
Test status
Simulation time 61463814063 ps
CPU time 79.54 seconds
Started Apr 28 12:22:54 PM PDT 24
Finished Apr 28 12:24:24 PM PDT 24
Peak memory 201928 kb
Host smart-5ebc6707-3ba6-4145-9f63-148a31cd27c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353065165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.3353065165
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3327921363
Short name T82
Test name
Test status
Simulation time 3625385373264 ps
CPU time 190.68 seconds
Started Apr 28 12:22:21 PM PDT 24
Finished Apr 28 12:25:33 PM PDT 24
Peak memory 201452 kb
Host smart-3de3e7de-40e3-4ec7-b10a-d0a1640734eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327921363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.3327921363
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1077666531
Short name T105
Test name
Test status
Simulation time 3722571161 ps
CPU time 1.68 seconds
Started Apr 28 12:22:05 PM PDT 24
Finished Apr 28 12:22:09 PM PDT 24
Peak memory 200724 kb
Host smart-0752b8d7-6106-4341-94a5-5ce5ac56766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077666531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.1077666531
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2925104279
Short name T359
Test name
Test status
Simulation time 24339869259 ps
CPU time 35.59 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:39 PM PDT 24
Peak memory 201832 kb
Host smart-c61cbedc-db6c-464e-a130-d656a4a9306f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925104279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.2925104279
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1304114653
Short name T350
Test name
Test status
Simulation time 59765071208 ps
CPU time 57.46 seconds
Started Apr 28 12:22:57 PM PDT 24
Finished Apr 28 12:24:04 PM PDT 24
Peak memory 201964 kb
Host smart-cf85d99d-ce18-4301-97aa-cb285a5c2ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304114653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.1304114653
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.411327193
Short name T332
Test name
Test status
Simulation time 43846000371 ps
CPU time 105.4 seconds
Started Apr 28 12:23:33 PM PDT 24
Finished Apr 28 12:25:19 PM PDT 24
Peak memory 201880 kb
Host smart-e3931aec-2087-4948-89c7-d09c10d76f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411327193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_wi
th_pre_cond.411327193
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.26485417
Short name T347
Test name
Test status
Simulation time 85463528512 ps
CPU time 113.69 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:25:50 PM PDT 24
Peak memory 201900 kb
Host smart-3c551f7c-694b-4b2a-bd80-f72eda2860ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26485417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_wit
h_pre_cond.26485417
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1012349110
Short name T216
Test name
Test status
Simulation time 111282354990 ps
CPU time 156.43 seconds
Started Apr 28 12:24:45 PM PDT 24
Finished Apr 28 12:27:22 PM PDT 24
Peak memory 201464 kb
Host smart-7dc31fe5-1ef2-45f6-8276-8d4a69b0600d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012349110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.1012349110
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.788628284
Short name T331
Test name
Test status
Simulation time 59302253084 ps
CPU time 33.12 seconds
Started Apr 28 12:23:48 PM PDT 24
Finished Apr 28 12:24:23 PM PDT 24
Peak memory 201916 kb
Host smart-5604fbf3-87ea-4d1e-b458-4b6643e2730c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788628284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_wi
th_pre_cond.788628284
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.171480308
Short name T24
Test name
Test status
Simulation time 100380120392 ps
CPU time 270.86 seconds
Started Apr 28 12:23:39 PM PDT 24
Finished Apr 28 12:28:11 PM PDT 24
Peak memory 201984 kb
Host smart-660797b5-9e93-423f-82b0-30a1300813a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171480308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_wi
th_pre_cond.171480308
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3369027190
Short name T351
Test name
Test status
Simulation time 65732589834 ps
CPU time 172.62 seconds
Started Apr 28 12:24:12 PM PDT 24
Finished Apr 28 12:27:07 PM PDT 24
Peak memory 201892 kb
Host smart-6b09792a-9569-49c8-9c68-8d65fba41f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369027190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.3369027190
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1729299719
Short name T227
Test name
Test status
Simulation time 119629112091 ps
CPU time 311.41 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:27:06 PM PDT 24
Peak memory 200160 kb
Host smart-4c893863-837f-4ee2-a91d-4cef8bef509f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729299719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.1729299719
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1862923266
Short name T237
Test name
Test status
Simulation time 47303292216 ps
CPU time 30.69 seconds
Started Apr 28 12:23:39 PM PDT 24
Finished Apr 28 12:24:10 PM PDT 24
Peak memory 201852 kb
Host smart-b0e0b498-3013-4b88-a4ef-769b4f83b535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862923266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.1862923266
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2394262454
Short name T847
Test name
Test status
Simulation time 3258068693 ps
CPU time 7.79 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:17:22 PM PDT 24
Peak memory 201424 kb
Host smart-f4103597-7a2b-4eb1-ab85-1228a5ddb838
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394262454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.2394262454
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3445306372
Short name T827
Test name
Test status
Simulation time 75632957818 ps
CPU time 188.84 seconds
Started Apr 28 12:17:11 PM PDT 24
Finished Apr 28 12:20:21 PM PDT 24
Peak memory 201472 kb
Host smart-a84fda84-a3c1-438a-9303-d3533b4b5677
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445306372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.3445306372
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1878492940
Short name T892
Test name
Test status
Simulation time 6022915616 ps
CPU time 16.28 seconds
Started Apr 28 12:18:14 PM PDT 24
Finished Apr 28 12:18:31 PM PDT 24
Peak memory 201584 kb
Host smart-f9f7ab36-a97d-4edf-9730-a1551d6c104c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878492940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.1878492940
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.305715077
Short name T845
Test name
Test status
Simulation time 2113605503 ps
CPU time 6.39 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:17:21 PM PDT 24
Peak memory 201244 kb
Host smart-97a749c1-e04e-4d67-82ad-16f8e51bcc24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305715077 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.305715077
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1379210673
Short name T915
Test name
Test status
Simulation time 2033588382 ps
CPU time 5.62 seconds
Started Apr 28 12:22:10 PM PDT 24
Finished Apr 28 12:22:19 PM PDT 24
Peak memory 201240 kb
Host smart-7a00b6d8-3268-4f3f-8556-07139d2f7f1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379210673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.1379210673
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.558146681
Short name T848
Test name
Test status
Simulation time 2050505149 ps
CPU time 1.9 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 200896 kb
Host smart-4574fa26-c724-4728-84e1-731eded4d60a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558146681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test
.558146681
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2438058188
Short name T250
Test name
Test status
Simulation time 2029581066 ps
CPU time 7.09 seconds
Started Apr 28 12:17:00 PM PDT 24
Finished Apr 28 12:17:07 PM PDT 24
Peak memory 201500 kb
Host smart-58fb0da0-b37e-4f83-ba5c-b9cc54343861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438058188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.2438058188
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.896969786
Short name T822
Test name
Test status
Simulation time 42453167097 ps
CPU time 108.88 seconds
Started Apr 28 12:23:30 PM PDT 24
Finished Apr 28 12:25:20 PM PDT 24
Peak memory 201816 kb
Host smart-bfaf039d-1f78-4188-8c8a-525b6979ca52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896969786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_tl_intg_err.896969786
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2038702431
Short name T310
Test name
Test status
Simulation time 2432277206 ps
CPU time 8.07 seconds
Started Apr 28 12:19:14 PM PDT 24
Finished Apr 28 12:19:23 PM PDT 24
Peak memory 201812 kb
Host smart-50239b82-82ed-4200-b427-2432edbd2a3d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038702431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.2038702431
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4213495898
Short name T307
Test name
Test status
Simulation time 75521402739 ps
CPU time 52.56 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:18:07 PM PDT 24
Peak memory 201476 kb
Host smart-b1517215-4b70-4205-88e5-b7ebe0bf99d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213495898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.4213495898
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.521979186
Short name T900
Test name
Test status
Simulation time 6036964412 ps
CPU time 9.1 seconds
Started Apr 28 12:17:10 PM PDT 24
Finished Apr 28 12:17:20 PM PDT 24
Peak memory 199792 kb
Host smart-6d95df79-ffb8-428d-9186-663ab98a70d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521979186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_hw_reset.521979186
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.645029318
Short name T890
Test name
Test status
Simulation time 2164552972 ps
CPU time 3.36 seconds
Started Apr 28 12:17:10 PM PDT 24
Finished Apr 28 12:17:14 PM PDT 24
Peak memory 201304 kb
Host smart-297866d4-b906-4505-b0e9-1350927da664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645029318 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.645029318
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.742182928
Short name T893
Test name
Test status
Simulation time 2040928399 ps
CPU time 2.6 seconds
Started Apr 28 12:22:05 PM PDT 24
Finished Apr 28 12:22:10 PM PDT 24
Peak memory 201460 kb
Host smart-ae411412-54b9-4943-839e-addffd2ea2be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742182928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw
.742182928
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.191283489
Short name T812
Test name
Test status
Simulation time 2036427832 ps
CPU time 1.8 seconds
Started Apr 28 12:22:09 PM PDT 24
Finished Apr 28 12:22:13 PM PDT 24
Peak memory 200800 kb
Host smart-18d0e550-227a-4beb-a7eb-b7a1a8fd51f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191283489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test
.191283489
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3347082507
Short name T857
Test name
Test status
Simulation time 10474722487 ps
CPU time 7.89 seconds
Started Apr 28 12:22:08 PM PDT 24
Finished Apr 28 12:22:19 PM PDT 24
Peak memory 200980 kb
Host smart-91492daf-38d2-4123-b6f3-681c55c6987f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347082507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.3347082507
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.74288217
Short name T920
Test name
Test status
Simulation time 2357728587 ps
CPU time 3.16 seconds
Started Apr 28 12:23:35 PM PDT 24
Finished Apr 28 12:23:39 PM PDT 24
Peak memory 201688 kb
Host smart-39ca984a-c6bc-4279-a0e1-3e2a0cd31b00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74288217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.74288217
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1168420759
Short name T807
Test name
Test status
Simulation time 22236890492 ps
CPU time 60.41 seconds
Started Apr 28 12:22:09 PM PDT 24
Finished Apr 28 12:23:12 PM PDT 24
Peak memory 201552 kb
Host smart-5227e613-ff41-43de-ac84-90b4a17583c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168420759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.1168420759
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2581024126
Short name T817
Test name
Test status
Simulation time 2075214544 ps
CPU time 6.65 seconds
Started Apr 28 12:22:02 PM PDT 24
Finished Apr 28 12:22:12 PM PDT 24
Peak memory 199620 kb
Host smart-e77c0065-652b-4673-8350-9a89baf772cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581024126 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2581024126
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.146813534
Short name T830
Test name
Test status
Simulation time 2029801977 ps
CPU time 5.67 seconds
Started Apr 28 12:20:22 PM PDT 24
Finished Apr 28 12:20:28 PM PDT 24
Peak memory 201456 kb
Host smart-92b849e3-169f-41d7-8e28-ef3f4fb66569
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146813534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_r
w.146813534
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3505964533
Short name T846
Test name
Test status
Simulation time 2015151885 ps
CPU time 5.89 seconds
Started Apr 28 12:18:51 PM PDT 24
Finished Apr 28 12:18:58 PM PDT 24
Peak memory 201172 kb
Host smart-259936db-4c53-440a-9a1a-a130e3f87154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505964533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.3505964533
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.996364591
Short name T885
Test name
Test status
Simulation time 4623079740 ps
CPU time 14.29 seconds
Started Apr 28 12:22:02 PM PDT 24
Finished Apr 28 12:22:19 PM PDT 24
Peak memory 199420 kb
Host smart-3ae6c1b3-6375-4c9d-8621-6af559b0b54a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996364591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.sysrst_ctrl_same_csr_outstanding.996364591
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.291092196
Short name T874
Test name
Test status
Simulation time 2020015188 ps
CPU time 6.66 seconds
Started Apr 28 12:20:42 PM PDT 24
Finished Apr 28 12:20:49 PM PDT 24
Peak memory 201476 kb
Host smart-20af6598-a0bc-43d1-95b5-cf43c2377c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291092196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_error
s.291092196
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1218667999
Short name T852
Test name
Test status
Simulation time 42459521672 ps
CPU time 107.04 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:24:04 PM PDT 24
Peak memory 201764 kb
Host smart-8acb29c5-6f69-4e32-84cc-457c7121e85f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218667999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.1218667999
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3008830524
Short name T825
Test name
Test status
Simulation time 2139326701 ps
CPU time 3.86 seconds
Started Apr 28 12:17:11 PM PDT 24
Finished Apr 28 12:17:15 PM PDT 24
Peak memory 201784 kb
Host smart-0f4edb06-7cf0-4349-b204-80209a7fdde1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008830524 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3008830524
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.489548936
Short name T301
Test name
Test status
Simulation time 2041105645 ps
CPU time 6.11 seconds
Started Apr 28 12:19:35 PM PDT 24
Finished Apr 28 12:19:42 PM PDT 24
Peak memory 201484 kb
Host smart-652c99e0-830e-4f89-8bd7-7f213cbf09bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489548936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_r
w.489548936
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.189881553
Short name T866
Test name
Test status
Simulation time 2215950185 ps
CPU time 0.93 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:22:07 PM PDT 24
Peak memory 200932 kb
Host smart-72631305-2e79-4f9e-b384-3d76bd6ff139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189881553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_tes
t.189881553
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3458568082
Short name T908
Test name
Test status
Simulation time 4411506005 ps
CPU time 8.66 seconds
Started Apr 28 12:20:17 PM PDT 24
Finished Apr 28 12:20:27 PM PDT 24
Peak memory 201556 kb
Host smart-b9f4125d-d3e8-41bb-aec6-081e10c1b8f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458568082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.3458568082
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.4101294855
Short name T258
Test name
Test status
Simulation time 2508256377 ps
CPU time 2.79 seconds
Started Apr 28 12:22:34 PM PDT 24
Finished Apr 28 12:22:41 PM PDT 24
Peak memory 201800 kb
Host smart-7ad25263-2ffd-4e84-b79b-20e062dbbb4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101294855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.4101294855
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.971462592
Short name T903
Test name
Test status
Simulation time 22576347961 ps
CPU time 15.43 seconds
Started Apr 28 12:19:33 PM PDT 24
Finished Apr 28 12:19:50 PM PDT 24
Peak memory 201840 kb
Host smart-40d811a2-8879-450c-afbe-01dd1db12c5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971462592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_tl_intg_err.971462592
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3287797907
Short name T916
Test name
Test status
Simulation time 2110518721 ps
CPU time 6.89 seconds
Started Apr 28 12:17:59 PM PDT 24
Finished Apr 28 12:18:07 PM PDT 24
Peak memory 201652 kb
Host smart-e246a18f-e580-4b2f-82d0-60f43ed38760
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287797907 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3287797907
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.853851700
Short name T912
Test name
Test status
Simulation time 2046475501 ps
CPU time 5.84 seconds
Started Apr 28 12:21:06 PM PDT 24
Finished Apr 28 12:21:13 PM PDT 24
Peak memory 201476 kb
Host smart-6a7521fe-5f83-4673-af3e-1834edfdc8c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853851700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_r
w.853851700
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2010082777
Short name T813
Test name
Test status
Simulation time 2027376999 ps
CPU time 1.87 seconds
Started Apr 28 12:20:11 PM PDT 24
Finished Apr 28 12:20:13 PM PDT 24
Peak memory 201168 kb
Host smart-c1560a23-a0ef-4571-8c29-f3dd5a297034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010082777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.2010082777
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1233442343
Short name T902
Test name
Test status
Simulation time 7733240643 ps
CPU time 11.44 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:12 PM PDT 24
Peak memory 201616 kb
Host smart-abea906c-1774-48ec-96da-fdc07a146b3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233442343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.1233442343
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2532631179
Short name T871
Test name
Test status
Simulation time 2060645123 ps
CPU time 6.83 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:22:14 PM PDT 24
Peak memory 201464 kb
Host smart-1fcd6bc5-24d9-4f56-bf0b-560034057201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532631179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.2532631179
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2328503453
Short name T255
Test name
Test status
Simulation time 22219976351 ps
CPU time 28.75 seconds
Started Apr 28 12:17:21 PM PDT 24
Finished Apr 28 12:17:51 PM PDT 24
Peak memory 201796 kb
Host smart-c6af4ec2-e32d-4edf-8e87-efa4a8c04419
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328503453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.2328503453
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.4272613612
Short name T909
Test name
Test status
Simulation time 2099672224 ps
CPU time 6.18 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:23:10 PM PDT 24
Peak memory 201432 kb
Host smart-2d2da09f-6da0-44e2-9498-f87d46c5c6e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272613612 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.4272613612
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.859790972
Short name T821
Test name
Test status
Simulation time 2013858764 ps
CPU time 6.01 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:10 PM PDT 24
Peak memory 201084 kb
Host smart-5c55daf2-b3cd-4db0-821a-c93cafd2531d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859790972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_tes
t.859790972
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1156471873
Short name T22
Test name
Test status
Simulation time 7165197765 ps
CPU time 6.57 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 201580 kb
Host smart-196ff00a-5e28-4c48-a4b4-b0735f157711
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156471873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.1156471873
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1472636981
Short name T259
Test name
Test status
Simulation time 2623750894 ps
CPU time 4.45 seconds
Started Apr 28 12:21:25 PM PDT 24
Finished Apr 28 12:21:30 PM PDT 24
Peak memory 201800 kb
Host smart-2cf05055-3b51-4b16-a56b-347641433b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472636981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_erro
rs.1472636981
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3459294690
Short name T335
Test name
Test status
Simulation time 42507182622 ps
CPU time 28.95 seconds
Started Apr 28 12:22:51 PM PDT 24
Finished Apr 28 12:23:31 PM PDT 24
Peak memory 201800 kb
Host smart-cabe346e-253f-41b0-ae7d-72a3a1646ca5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459294690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.3459294690
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.475310991
Short name T829
Test name
Test status
Simulation time 2488015279 ps
CPU time 1.52 seconds
Started Apr 28 12:21:55 PM PDT 24
Finished Apr 28 12:22:00 PM PDT 24
Peak memory 201372 kb
Host smart-e56df1aa-3764-4f8a-9192-6e5a3dde92cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475310991 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.475310991
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.802677385
Short name T303
Test name
Test status
Simulation time 2069255451 ps
CPU time 2.05 seconds
Started Apr 28 12:22:19 PM PDT 24
Finished Apr 28 12:22:23 PM PDT 24
Peak memory 201216 kb
Host smart-27513dee-6e38-48a5-9d21-31605cc89247
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802677385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_r
w.802677385
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1346198568
Short name T861
Test name
Test status
Simulation time 2010818961 ps
CPU time 5.88 seconds
Started Apr 28 12:22:20 PM PDT 24
Finished Apr 28 12:22:27 PM PDT 24
Peak memory 201080 kb
Host smart-eb9c1d34-52dc-425a-bc10-e1050e8ca263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346198568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.1346198568
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.4160815371
Short name T21
Test name
Test status
Simulation time 5133787265 ps
CPU time 6.94 seconds
Started Apr 28 12:21:53 PM PDT 24
Finished Apr 28 12:22:04 PM PDT 24
Peak memory 200408 kb
Host smart-a8475bd2-a2ed-4f3b-860a-f6a41b67d2d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160815371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.4160815371
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2359546824
Short name T842
Test name
Test status
Simulation time 2556583421 ps
CPU time 3.93 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:01 PM PDT 24
Peak memory 201428 kb
Host smart-99826009-c832-4ac6-bbcb-683406507b50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359546824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.2359546824
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.4235033853
Short name T888
Test name
Test status
Simulation time 22203645292 ps
CPU time 32.09 seconds
Started Apr 28 12:22:21 PM PDT 24
Finished Apr 28 12:22:54 PM PDT 24
Peak memory 201524 kb
Host smart-7300a419-0e36-4ffc-a3fa-3e9a2925e747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235033853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.4235033853
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3953799702
Short name T896
Test name
Test status
Simulation time 2121689836 ps
CPU time 3.85 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:47 PM PDT 24
Peak memory 200732 kb
Host smart-c9607eef-c284-44fa-b984-02ac56c9936d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953799702 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3953799702
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3062758505
Short name T851
Test name
Test status
Simulation time 2052826165 ps
CPU time 6.19 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:05 PM PDT 24
Peak memory 201240 kb
Host smart-78a2eeb7-ac70-42fa-b6de-65de30203993
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062758505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.3062758505
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.957221114
Short name T911
Test name
Test status
Simulation time 2010828902 ps
CPU time 5.87 seconds
Started Apr 28 12:19:24 PM PDT 24
Finished Apr 28 12:19:30 PM PDT 24
Peak memory 200916 kb
Host smart-fb91c4a7-c0d0-4c0f-8153-13faad2494f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957221114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_tes
t.957221114
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1646899675
Short name T19
Test name
Test status
Simulation time 7434703533 ps
CPU time 6.28 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:22:01 PM PDT 24
Peak memory 201084 kb
Host smart-544783b9-a9b9-40f5-af03-b03c0c32463a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646899675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.1646899675
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3004524500
Short name T832
Test name
Test status
Simulation time 2100254771 ps
CPU time 7.56 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:05 PM PDT 24
Peak memory 201340 kb
Host smart-217085fb-6892-4311-8d31-18d14e5fb3fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004524500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.3004524500
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.4029236476
Short name T872
Test name
Test status
Simulation time 2309064859 ps
CPU time 1.93 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:04 PM PDT 24
Peak memory 201576 kb
Host smart-c23d6d6d-7698-4b13-afc2-c01969b5fcf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029236476 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.4029236476
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1836580667
Short name T877
Test name
Test status
Simulation time 2122882414 ps
CPU time 1.17 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:45 PM PDT 24
Peak memory 200356 kb
Host smart-9ff686a8-bfbb-4659-889f-41135e9a58a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836580667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.1836580667
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1637139749
Short name T894
Test name
Test status
Simulation time 2009491874 ps
CPU time 5.95 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:49 PM PDT 24
Peak memory 200184 kb
Host smart-184eb577-3255-409a-a377-f25a7ebb4fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637139749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.1637139749
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3777624354
Short name T313
Test name
Test status
Simulation time 5390241064 ps
CPU time 22.51 seconds
Started Apr 28 12:18:41 PM PDT 24
Finished Apr 28 12:19:03 PM PDT 24
Peak memory 201684 kb
Host smart-369f81ab-c70b-4da3-a48c-e4722eae2bee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777624354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.3777624354
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.861328522
Short name T826
Test name
Test status
Simulation time 2050116101 ps
CPU time 8.18 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:22:15 PM PDT 24
Peak memory 201400 kb
Host smart-ceb8d4a9-d23a-4f7c-af5e-0e706bc01dc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861328522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_error
s.861328522
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2981548772
Short name T333
Test name
Test status
Simulation time 42799921753 ps
CPU time 32.74 seconds
Started Apr 28 12:22:39 PM PDT 24
Finished Apr 28 12:23:17 PM PDT 24
Peak memory 201576 kb
Host smart-ef44b073-b629-48ef-bca4-c4ad8790b7a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981548772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.2981548772
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1843230971
Short name T873
Test name
Test status
Simulation time 2085768421 ps
CPU time 5.89 seconds
Started Apr 28 12:17:23 PM PDT 24
Finished Apr 28 12:17:29 PM PDT 24
Peak memory 201496 kb
Host smart-31d69fad-219b-476c-a428-007ad3ea5666
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843230971 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1843230971
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2066067255
Short name T309
Test name
Test status
Simulation time 2021972501 ps
CPU time 5.63 seconds
Started Apr 28 12:22:39 PM PDT 24
Finished Apr 28 12:22:50 PM PDT 24
Peak memory 201152 kb
Host smart-577741b3-a6b1-46c8-b588-3f758e047412
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066067255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.2066067255
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.711500475
Short name T844
Test name
Test status
Simulation time 2015776269 ps
CPU time 2.73 seconds
Started Apr 28 12:18:57 PM PDT 24
Finished Apr 28 12:19:01 PM PDT 24
Peak memory 201124 kb
Host smart-35d3e168-ea3e-48bf-b4eb-0481e1dfe9a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711500475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_tes
t.711500475
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.527640771
Short name T918
Test name
Test status
Simulation time 7802588831 ps
CPU time 22.63 seconds
Started Apr 28 12:22:03 PM PDT 24
Finished Apr 28 12:22:28 PM PDT 24
Peak memory 200472 kb
Host smart-02508686-ebf6-4da3-a2f0-ce3c6dd93253
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527640771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.sysrst_ctrl_same_csr_outstanding.527640771
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3783077814
Short name T906
Test name
Test status
Simulation time 2160602178 ps
CPU time 2.96 seconds
Started Apr 28 12:22:09 PM PDT 24
Finished Apr 28 12:22:15 PM PDT 24
Peak memory 201560 kb
Host smart-84ac0900-64a7-4c37-b6cd-7724c8a72c8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783077814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.3783077814
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.219650870
Short name T247
Test name
Test status
Simulation time 22246209730 ps
CPU time 61.17 seconds
Started Apr 28 12:22:40 PM PDT 24
Finished Apr 28 12:23:46 PM PDT 24
Peak memory 201012 kb
Host smart-e66cee71-8632-40a0-af2e-45349cea0acc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219650870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_tl_intg_err.219650870
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2187469769
Short name T899
Test name
Test status
Simulation time 2082559873 ps
CPU time 3.68 seconds
Started Apr 28 12:20:25 PM PDT 24
Finished Apr 28 12:20:30 PM PDT 24
Peak memory 201492 kb
Host smart-0b04d694-5156-4961-97bb-fabee6592297
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187469769 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2187469769
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.466805871
Short name T306
Test name
Test status
Simulation time 2078402442 ps
CPU time 2.06 seconds
Started Apr 28 12:19:51 PM PDT 24
Finished Apr 28 12:19:54 PM PDT 24
Peak memory 201288 kb
Host smart-bc61b5e2-1712-4ddc-9785-4f5b4d00e65f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466805871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_r
w.466805871
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.275856089
Short name T905
Test name
Test status
Simulation time 2020683300 ps
CPU time 3.43 seconds
Started Apr 28 12:18:00 PM PDT 24
Finished Apr 28 12:18:04 PM PDT 24
Peak memory 201396 kb
Host smart-d91d340a-f53d-4ddf-abb0-8f7d2b9654d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275856089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_tes
t.275856089
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3055448946
Short name T904
Test name
Test status
Simulation time 9475258921 ps
CPU time 12.77 seconds
Started Apr 28 12:19:50 PM PDT 24
Finished Apr 28 12:20:04 PM PDT 24
Peak memory 200452 kb
Host smart-1e894f70-b1df-4f18-acf7-900c952ea5ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055448946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.3055448946
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3957807200
Short name T895
Test name
Test status
Simulation time 2074375968 ps
CPU time 6.81 seconds
Started Apr 28 12:19:57 PM PDT 24
Finished Apr 28 12:20:04 PM PDT 24
Peak memory 201780 kb
Host smart-6c6ae52f-88d5-4802-837d-790c8ba3861d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957807200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.3957807200
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.590609723
Short name T836
Test name
Test status
Simulation time 22273704153 ps
CPU time 28.88 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:23:26 PM PDT 24
Peak memory 201536 kb
Host smart-7dc9dc3a-cd04-43b2-b64a-28535a8edba3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590609723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_tl_intg_err.590609723
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.651687791
Short name T814
Test name
Test status
Simulation time 2245852423 ps
CPU time 2.25 seconds
Started Apr 28 12:20:34 PM PDT 24
Finished Apr 28 12:20:37 PM PDT 24
Peak memory 209916 kb
Host smart-36f56c62-038d-4342-8fe6-8f3186fc28b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651687791 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.651687791
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2944802991
Short name T810
Test name
Test status
Simulation time 2074268657 ps
CPU time 3.15 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:52 PM PDT 24
Peak memory 201140 kb
Host smart-7edccec1-ef2d-4016-b731-45e35a36eb90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944802991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.2944802991
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2225749294
Short name T824
Test name
Test status
Simulation time 2045876341 ps
CPU time 1.92 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 200836 kb
Host smart-18e8592a-334c-4f2f-8067-245436378d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225749294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.2225749294
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1107962267
Short name T811
Test name
Test status
Simulation time 4745528651 ps
CPU time 7.06 seconds
Started Apr 28 12:17:49 PM PDT 24
Finished Apr 28 12:17:56 PM PDT 24
Peak memory 201780 kb
Host smart-bf1e23b5-bf50-4b70-a2af-815f2b097608
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107962267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.1107962267
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.140476891
Short name T838
Test name
Test status
Simulation time 2122696256 ps
CPU time 3.95 seconds
Started Apr 28 12:24:25 PM PDT 24
Finished Apr 28 12:24:31 PM PDT 24
Peak memory 201712 kb
Host smart-d5c84b1a-c104-4165-9e57-0d1e9ff1aafd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140476891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_error
s.140476891
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.4063582568
Short name T887
Test name
Test status
Simulation time 42381634855 ps
CPU time 59.98 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:24:03 PM PDT 24
Peak memory 201452 kb
Host smart-94d08ac4-2b84-4b0a-9327-1ccfd8de3ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063582568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.4063582568
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.985032650
Short name T876
Test name
Test status
Simulation time 2678408523 ps
CPU time 6.28 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:08 PM PDT 24
Peak memory 201660 kb
Host smart-92aea316-9ba6-42d8-85bd-75a0988c18b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985032650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_aliasing.985032650
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3448751350
Short name T870
Test name
Test status
Simulation time 38146641140 ps
CPU time 104.7 seconds
Started Apr 28 12:17:10 PM PDT 24
Finished Apr 28 12:18:55 PM PDT 24
Peak memory 200560 kb
Host smart-e58d41ae-174b-44e5-aa42-d8c418cf4138
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448751350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.3448751350
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.731873460
Short name T302
Test name
Test status
Simulation time 6088690007 ps
CPU time 7.03 seconds
Started Apr 28 12:17:10 PM PDT 24
Finished Apr 28 12:17:18 PM PDT 24
Peak memory 199756 kb
Host smart-d34a844d-d400-4d8b-a614-554d2fe316df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731873460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_hw_reset.731873460
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3942918391
Short name T26
Test name
Test status
Simulation time 2075724907 ps
CPU time 6.37 seconds
Started Apr 28 12:22:06 PM PDT 24
Finished Apr 28 12:22:14 PM PDT 24
Peak memory 201520 kb
Host smart-423172ea-9235-417c-921f-9ae5b8558ff5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942918391 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3942918391
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1076120964
Short name T308
Test name
Test status
Simulation time 2051601046 ps
CPU time 6.01 seconds
Started Apr 28 12:17:00 PM PDT 24
Finished Apr 28 12:17:06 PM PDT 24
Peak memory 201344 kb
Host smart-16929ef1-46b4-4d33-a666-3908d4c9dc84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076120964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.1076120964
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1708570854
Short name T809
Test name
Test status
Simulation time 2018064742 ps
CPU time 3.24 seconds
Started Apr 28 12:17:00 PM PDT 24
Finished Apr 28 12:17:04 PM PDT 24
Peak memory 200636 kb
Host smart-025d54e6-b7da-4802-8f64-4f0b57d5801f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708570854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.1708570854
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3858455790
Short name T843
Test name
Test status
Simulation time 9384085234 ps
CPU time 33.97 seconds
Started Apr 28 12:17:10 PM PDT 24
Finished Apr 28 12:17:45 PM PDT 24
Peak memory 200108 kb
Host smart-60f66387-8a0c-42a8-9351-1709d0c12337
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858455790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.3858455790
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3927775205
Short name T244
Test name
Test status
Simulation time 42654307458 ps
CPU time 19.12 seconds
Started Apr 28 12:18:14 PM PDT 24
Finished Apr 28 12:18:33 PM PDT 24
Peak memory 201768 kb
Host smart-12889d53-7655-4429-beb1-ca66811b24d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927775205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.3927775205
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3855805564
Short name T849
Test name
Test status
Simulation time 2012942995 ps
CPU time 6.09 seconds
Started Apr 28 12:21:55 PM PDT 24
Finished Apr 28 12:22:05 PM PDT 24
Peak memory 200880 kb
Host smart-e3dbdba5-4d21-45bd-87f7-688ac1ad743a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855805564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.3855805564
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3421691029
Short name T891
Test name
Test status
Simulation time 2025037948 ps
CPU time 2.32 seconds
Started Apr 28 12:20:33 PM PDT 24
Finished Apr 28 12:20:36 PM PDT 24
Peak memory 200940 kb
Host smart-2111f11c-b5c3-496a-bf64-e74cea642195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421691029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.3421691029
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3263807292
Short name T818
Test name
Test status
Simulation time 2030409909 ps
CPU time 1.82 seconds
Started Apr 28 12:18:01 PM PDT 24
Finished Apr 28 12:18:04 PM PDT 24
Peak memory 201140 kb
Host smart-edef94a4-17f1-415e-b3e5-3a0d35b3a46e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263807292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.3263807292
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2065766618
Short name T799
Test name
Test status
Simulation time 2008849348 ps
CPU time 5.67 seconds
Started Apr 28 12:18:01 PM PDT 24
Finished Apr 28 12:18:07 PM PDT 24
Peak memory 201088 kb
Host smart-0fa2e600-cb8c-4bc1-920f-cabce56d284d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065766618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.2065766618
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1881509485
Short name T886
Test name
Test status
Simulation time 2034486991 ps
CPU time 1.99 seconds
Started Apr 28 12:17:49 PM PDT 24
Finished Apr 28 12:17:52 PM PDT 24
Peak memory 201192 kb
Host smart-ddf49120-ddbb-4b22-a42a-be01aac3283b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881509485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.1881509485
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3894466138
Short name T800
Test name
Test status
Simulation time 2014330071 ps
CPU time 6.06 seconds
Started Apr 28 12:18:01 PM PDT 24
Finished Apr 28 12:18:07 PM PDT 24
Peak memory 201084 kb
Host smart-2c233c08-0af2-4b68-ae69-00c92d535ffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894466138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.3894466138
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.319238980
Short name T841
Test name
Test status
Simulation time 2017263671 ps
CPU time 6.12 seconds
Started Apr 28 12:17:59 PM PDT 24
Finished Apr 28 12:18:05 PM PDT 24
Peak memory 201184 kb
Host smart-acff0140-c929-4953-8571-284d65521301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319238980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_tes
t.319238980
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.65164469
Short name T816
Test name
Test status
Simulation time 2012784663 ps
CPU time 5.77 seconds
Started Apr 28 12:21:59 PM PDT 24
Finished Apr 28 12:22:07 PM PDT 24
Peak memory 199544 kb
Host smart-a440a106-1fd2-4b5c-9483-9996df192bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65164469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test
.65164469
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2079353737
Short name T853
Test name
Test status
Simulation time 2010599670 ps
CPU time 5.85 seconds
Started Apr 28 12:18:12 PM PDT 24
Finished Apr 28 12:18:18 PM PDT 24
Peak memory 201416 kb
Host smart-3fb7d429-f54f-4896-95d4-f29c831a44be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079353737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.2079353737
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1455046531
Short name T901
Test name
Test status
Simulation time 2026029858 ps
CPU time 3.14 seconds
Started Apr 28 12:22:16 PM PDT 24
Finished Apr 28 12:22:22 PM PDT 24
Peak memory 201072 kb
Host smart-3a35a4de-719c-414b-8a9a-085992e55cc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455046531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.1455046531
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3998520455
Short name T300
Test name
Test status
Simulation time 38672722819 ps
CPU time 24.13 seconds
Started Apr 28 12:19:24 PM PDT 24
Finished Apr 28 12:19:49 PM PDT 24
Peak memory 201792 kb
Host smart-9db65780-47c5-4159-9380-779bdf42fce2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998520455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.3998520455
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.480937377
Short name T868
Test name
Test status
Simulation time 4027280170 ps
CPU time 11.15 seconds
Started Apr 28 12:17:11 PM PDT 24
Finished Apr 28 12:17:23 PM PDT 24
Peak memory 201292 kb
Host smart-41485991-7ae8-4dee-ac86-1fef83b5a269
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480937377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_hw_reset.480937377
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2034334545
Short name T256
Test name
Test status
Simulation time 2240390739 ps
CPU time 2.59 seconds
Started Apr 28 12:23:29 PM PDT 24
Finished Apr 28 12:23:33 PM PDT 24
Peak memory 201676 kb
Host smart-b1718b1b-89b4-4b60-906c-cf2854d25e58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034334545 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2034334545
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2806611706
Short name T25
Test name
Test status
Simulation time 2110397902 ps
CPU time 2.16 seconds
Started Apr 28 12:16:59 PM PDT 24
Finished Apr 28 12:17:02 PM PDT 24
Peak memory 201348 kb
Host smart-0e4c7777-3cda-4cfa-bb87-28131fe0c879
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806611706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.2806611706
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.4259662435
Short name T837
Test name
Test status
Simulation time 2011979502 ps
CPU time 6.21 seconds
Started Apr 28 12:17:10 PM PDT 24
Finished Apr 28 12:17:17 PM PDT 24
Peak memory 199396 kb
Host smart-7cecc734-5498-4273-81f7-06a79a36ee5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259662435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.4259662435
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.969683278
Short name T862
Test name
Test status
Simulation time 5553737215 ps
CPU time 21.06 seconds
Started Apr 28 12:17:13 PM PDT 24
Finished Apr 28 12:17:36 PM PDT 24
Peak memory 201560 kb
Host smart-98ce8f9e-839f-48f3-beff-e084bada8037
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969683278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
sysrst_ctrl_same_csr_outstanding.969683278
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.78547583
Short name T860
Test name
Test status
Simulation time 2402721321 ps
CPU time 2.54 seconds
Started Apr 28 12:17:11 PM PDT 24
Finished Apr 28 12:17:14 PM PDT 24
Peak memory 201456 kb
Host smart-40da09f5-f78b-4332-ba81-8e6e1be6e990
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78547583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.78547583
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3695281288
Short name T243
Test name
Test status
Simulation time 42895032286 ps
CPU time 31.74 seconds
Started Apr 28 12:19:12 PM PDT 24
Finished Apr 28 12:19:44 PM PDT 24
Peak memory 201776 kb
Host smart-5f7092ff-11f9-463a-95c0-c61e8cff6dfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695281288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.3695281288
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.643986153
Short name T859
Test name
Test status
Simulation time 2017847769 ps
CPU time 5.86 seconds
Started Apr 28 12:20:53 PM PDT 24
Finished Apr 28 12:20:59 PM PDT 24
Peak memory 201400 kb
Host smart-440522c7-2f88-4636-bb99-f5719a1d6326
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643986153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_tes
t.643986153
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.532309792
Short name T831
Test name
Test status
Simulation time 2080883680 ps
CPU time 1.07 seconds
Started Apr 28 12:18:56 PM PDT 24
Finished Apr 28 12:18:57 PM PDT 24
Peak memory 201116 kb
Host smart-347376e2-6fbc-4f72-8215-e0b02f0f2105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532309792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_tes
t.532309792
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.20886304
Short name T907
Test name
Test status
Simulation time 2015271875 ps
CPU time 6.06 seconds
Started Apr 28 12:22:12 PM PDT 24
Finished Apr 28 12:22:22 PM PDT 24
Peak memory 201320 kb
Host smart-b2268d0b-9e41-43d4-8d16-6c66558dd11f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20886304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test
.20886304
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2547532346
Short name T803
Test name
Test status
Simulation time 2023571665 ps
CPU time 3.3 seconds
Started Apr 28 12:22:15 PM PDT 24
Finished Apr 28 12:22:21 PM PDT 24
Peak memory 200760 kb
Host smart-f5798fca-bfb1-4af7-8367-5f8979d1c82d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547532346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.2547532346
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1203014587
Short name T805
Test name
Test status
Simulation time 2047951116 ps
CPU time 1.94 seconds
Started Apr 28 12:23:07 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 200736 kb
Host smart-cf2848ce-3d75-461f-9e91-e047d3d249c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203014587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.1203014587
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2267204110
Short name T883
Test name
Test status
Simulation time 2016602780 ps
CPU time 5.78 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:23:10 PM PDT 24
Peak memory 200816 kb
Host smart-dbd97645-0d22-42c6-b5ad-a4037fa41ebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267204110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.2267204110
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.670792381
Short name T801
Test name
Test status
Simulation time 2059994951 ps
CPU time 1.33 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 200788 kb
Host smart-5d561bb2-f856-4cb6-9c75-43c1bc795959
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670792381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_tes
t.670792381
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.985740759
Short name T806
Test name
Test status
Simulation time 2012029109 ps
CPU time 5.65 seconds
Started Apr 28 12:18:33 PM PDT 24
Finished Apr 28 12:18:40 PM PDT 24
Peak memory 201436 kb
Host smart-da102fc0-e25b-45a2-808a-24d73f30939c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985740759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_tes
t.985740759
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1237927686
Short name T879
Test name
Test status
Simulation time 2043777385 ps
CPU time 1.99 seconds
Started Apr 28 12:18:01 PM PDT 24
Finished Apr 28 12:18:03 PM PDT 24
Peak memory 201096 kb
Host smart-1574657f-fbbf-41e3-935f-4f171a19a80d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237927686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.1237927686
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.4027589915
Short name T798
Test name
Test status
Simulation time 2010584629 ps
CPU time 5.77 seconds
Started Apr 28 12:22:58 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 200304 kb
Host smart-7158e26b-7d7a-4af1-af40-35370e906762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027589915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.4027589915
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3030795834
Short name T878
Test name
Test status
Simulation time 3368952972 ps
CPU time 5.45 seconds
Started Apr 28 12:17:06 PM PDT 24
Finished Apr 28 12:17:12 PM PDT 24
Peak memory 200948 kb
Host smart-cdff0e39-46fe-4d13-9b55-160ae1639984
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030795834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.3030795834
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.514994604
Short name T897
Test name
Test status
Simulation time 2949290683 ps
CPU time 7.85 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:22 PM PDT 24
Peak memory 201468 kb
Host smart-b9e3855a-02c1-4fd0-8a16-8637baaae791
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514994604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_bit_bash.514994604
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.3843276585
Short name T314
Test name
Test status
Simulation time 6017699410 ps
CPU time 8.17 seconds
Started Apr 28 12:17:11 PM PDT 24
Finished Apr 28 12:17:19 PM PDT 24
Peak memory 201328 kb
Host smart-27b9bec9-99e0-46f1-8995-25092f906b99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843276585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.3843276585
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2658875044
Short name T917
Test name
Test status
Simulation time 2132733634 ps
CPU time 4.72 seconds
Started Apr 28 12:23:00 PM PDT 24
Finished Apr 28 12:23:13 PM PDT 24
Peak memory 201584 kb
Host smart-b15d4d82-6f6d-44ea-b589-d8907f5bbeec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658875044 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2658875044
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.676093091
Short name T304
Test name
Test status
Simulation time 2074193699 ps
CPU time 1.58 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:16 PM PDT 24
Peak memory 201120 kb
Host smart-fb603c0a-c7e3-49d8-b33e-76940226bdd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676093091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw
.676093091
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1256190797
Short name T820
Test name
Test status
Simulation time 2048152545 ps
CPU time 1.58 seconds
Started Apr 28 12:22:10 PM PDT 24
Finished Apr 28 12:22:15 PM PDT 24
Peak memory 200920 kb
Host smart-de012ccb-9268-4a6a-896d-5ba5b60aa641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256190797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.1256190797
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.365045405
Short name T898
Test name
Test status
Simulation time 8715842283 ps
CPU time 24.51 seconds
Started Apr 28 12:22:09 PM PDT 24
Finished Apr 28 12:22:36 PM PDT 24
Peak memory 201780 kb
Host smart-7d51dbb9-e371-452b-8b65-7b5b88cd0112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365045405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
sysrst_ctrl_same_csr_outstanding.365045405
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1613576406
Short name T254
Test name
Test status
Simulation time 2072573339 ps
CPU time 3.7 seconds
Started Apr 28 12:22:07 PM PDT 24
Finished Apr 28 12:22:13 PM PDT 24
Peak memory 201668 kb
Host smart-bd8d4f5d-dfdd-4d0f-b53f-3ec2f3d1d6ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613576406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.1613576406
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2667896101
Short name T336
Test name
Test status
Simulation time 42376512285 ps
CPU time 107.77 seconds
Started Apr 28 12:16:59 PM PDT 24
Finished Apr 28 12:18:47 PM PDT 24
Peak memory 201624 kb
Host smart-a8fc90f4-08f4-4814-8d47-268756ac1e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667896101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.2667896101
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.868206958
Short name T856
Test name
Test status
Simulation time 2044413619 ps
CPU time 1.99 seconds
Started Apr 28 12:22:15 PM PDT 24
Finished Apr 28 12:22:20 PM PDT 24
Peak memory 201040 kb
Host smart-fd7734ed-3e98-4705-9547-109a02ec836b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868206958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_tes
t.868206958
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2700436985
Short name T864
Test name
Test status
Simulation time 2048219732 ps
CPU time 1.94 seconds
Started Apr 28 12:22:15 PM PDT 24
Finished Apr 28 12:22:20 PM PDT 24
Peak memory 201296 kb
Host smart-38a8c368-5608-42d4-9697-81a7a477dd58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700436985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.2700436985
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1976775379
Short name T804
Test name
Test status
Simulation time 2009995752 ps
CPU time 5.07 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:22 PM PDT 24
Peak memory 201072 kb
Host smart-a5aa192c-3776-4db7-bee8-4c14a031d317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976775379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.1976775379
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3901353418
Short name T834
Test name
Test status
Simulation time 2008013599 ps
CPU time 6.04 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:22:24 PM PDT 24
Peak memory 199644 kb
Host smart-c6c5d1d8-a55a-48cf-8136-bf842bc1dcf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901353418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te
st.3901353418
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2182048072
Short name T802
Test name
Test status
Simulation time 2031961118 ps
CPU time 1.98 seconds
Started Apr 28 12:18:52 PM PDT 24
Finished Apr 28 12:18:54 PM PDT 24
Peak memory 201168 kb
Host smart-d8e39247-9b2a-4c1b-9501-93a3644222ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182048072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.2182048072
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1935821453
Short name T869
Test name
Test status
Simulation time 2038595079 ps
CPU time 1.94 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:04 PM PDT 24
Peak memory 200940 kb
Host smart-23763705-06bd-48b5-936f-9f3056207a6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935821453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.1935821453
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2476136772
Short name T823
Test name
Test status
Simulation time 2017086221 ps
CPU time 5.95 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:08 PM PDT 24
Peak memory 200724 kb
Host smart-c661b90e-3541-4f83-8c17-0b996ebb6112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476136772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.2476136772
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3094118679
Short name T835
Test name
Test status
Simulation time 2031412662 ps
CPU time 1.93 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:22:19 PM PDT 24
Peak memory 199760 kb
Host smart-dfa5a989-d9cb-4310-b191-1b05c091a78e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094118679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.3094118679
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2232810701
Short name T881
Test name
Test status
Simulation time 2022941296 ps
CPU time 1.97 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:22:19 PM PDT 24
Peak memory 201036 kb
Host smart-8b60491d-7972-4b7c-87fb-2c61f6cce7dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232810701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.2232810701
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1855437151
Short name T882
Test name
Test status
Simulation time 2013243696 ps
CPU time 5.39 seconds
Started Apr 28 12:21:59 PM PDT 24
Finished Apr 28 12:22:07 PM PDT 24
Peak memory 199492 kb
Host smart-b885c659-39aa-4b52-8e4d-d9f4dcb6354a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855437151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.1855437151
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.692950829
Short name T875
Test name
Test status
Simulation time 2275473282 ps
CPU time 2.1 seconds
Started Apr 28 12:17:59 PM PDT 24
Finished Apr 28 12:18:02 PM PDT 24
Peak memory 201856 kb
Host smart-a68933ba-e3d7-4502-b115-0b2a8c0642f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692950829 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.692950829
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2144730345
Short name T311
Test name
Test status
Simulation time 2060175172 ps
CPU time 2.31 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:01 PM PDT 24
Peak memory 200696 kb
Host smart-45552015-1e85-459f-8ee5-bda6a9547f0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144730345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.2144730345
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1871656940
Short name T819
Test name
Test status
Simulation time 2012130891 ps
CPU time 6.01 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:48 PM PDT 24
Peak memory 201348 kb
Host smart-37dec700-8d70-4727-aef4-8d277d9e3976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871656940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.1871656940
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.889451675
Short name T312
Test name
Test status
Simulation time 4992903843 ps
CPU time 14.33 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:28 PM PDT 24
Peak memory 201660 kb
Host smart-263be63c-0e3f-4814-a7c8-f7d24110f224
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889451675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
sysrst_ctrl_same_csr_outstanding.889451675
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.4100107947
Short name T839
Test name
Test status
Simulation time 2192111093 ps
CPU time 5.13 seconds
Started Apr 28 12:17:12 PM PDT 24
Finished Apr 28 12:17:19 PM PDT 24
Peak memory 200632 kb
Host smart-67055e07-d20f-442d-8433-4da0ee010169
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100107947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.4100107947
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1209806719
Short name T808
Test name
Test status
Simulation time 22424394683 ps
CPU time 17.46 seconds
Started Apr 28 12:22:07 PM PDT 24
Finished Apr 28 12:22:27 PM PDT 24
Peak memory 201824 kb
Host smart-692d31ef-ec98-4b6e-ad6b-c068cdfa6711
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209806719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.1209806719
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3072133361
Short name T290
Test name
Test status
Simulation time 2086965744 ps
CPU time 3.46 seconds
Started Apr 28 12:22:02 PM PDT 24
Finished Apr 28 12:22:08 PM PDT 24
Peak memory 199248 kb
Host smart-2b4d50d4-8f0a-479c-9da6-b3b360f46ca0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072133361 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3072133361
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.954666080
Short name T919
Test name
Test status
Simulation time 2035631192 ps
CPU time 6.01 seconds
Started Apr 28 12:22:03 PM PDT 24
Finished Apr 28 12:22:12 PM PDT 24
Peak memory 201084 kb
Host smart-0289f73a-6fdb-48c9-bffa-1013c0a08e9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954666080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw
.954666080
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2482083287
Short name T880
Test name
Test status
Simulation time 2026897927 ps
CPU time 2.08 seconds
Started Apr 28 12:18:50 PM PDT 24
Finished Apr 28 12:18:53 PM PDT 24
Peak memory 201120 kb
Host smart-14c8eb28-8ed8-4219-8402-f13a99dd03f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482083287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.2482083287
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1470416129
Short name T840
Test name
Test status
Simulation time 8109231908 ps
CPU time 5.59 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:22:12 PM PDT 24
Peak memory 201572 kb
Host smart-824cd481-72cc-420a-b3d9-224b886641a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470416129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.1470416129
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1313045897
Short name T858
Test name
Test status
Simulation time 22249692113 ps
CPU time 23.1 seconds
Started Apr 28 12:22:20 PM PDT 24
Finished Apr 28 12:22:45 PM PDT 24
Peak memory 201764 kb
Host smart-24614359-dc01-4959-94a7-ec6c73cd3d05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313045897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.1313045897
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1972512214
Short name T854
Test name
Test status
Simulation time 2128338836 ps
CPU time 5.62 seconds
Started Apr 28 12:22:21 PM PDT 24
Finished Apr 28 12:22:28 PM PDT 24
Peak memory 201584 kb
Host smart-4285bf6b-b9be-45f8-83c9-36d845053171
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972512214 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1972512214
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3165453750
Short name T305
Test name
Test status
Simulation time 2056156334 ps
CPU time 5.93 seconds
Started Apr 28 12:18:03 PM PDT 24
Finished Apr 28 12:18:10 PM PDT 24
Peak memory 201584 kb
Host smart-2a50129f-cec1-45e9-8bb3-776cb714aa3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165453750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.3165453750
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1011522910
Short name T867
Test name
Test status
Simulation time 2030206400 ps
CPU time 1.94 seconds
Started Apr 28 12:22:20 PM PDT 24
Finished Apr 28 12:22:23 PM PDT 24
Peak memory 201068 kb
Host smart-610abbb7-ca41-416f-98a0-45f32d890885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011522910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.1011522910
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2470930699
Short name T863
Test name
Test status
Simulation time 5200725620 ps
CPU time 6.46 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:54 PM PDT 24
Peak memory 201132 kb
Host smart-261dcd3d-8f86-49a4-b69d-6c76cdea8cd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470930699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.2470930699
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1565782960
Short name T913
Test name
Test status
Simulation time 2216145069 ps
CPU time 2.72 seconds
Started Apr 28 12:20:42 PM PDT 24
Finished Apr 28 12:20:45 PM PDT 24
Peak memory 201724 kb
Host smart-2fef918b-5825-49de-96b2-04b667aeda82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565782960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.1565782960
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3420537112
Short name T914
Test name
Test status
Simulation time 42451849185 ps
CPU time 119.24 seconds
Started Apr 28 12:19:26 PM PDT 24
Finished Apr 28 12:21:27 PM PDT 24
Peak memory 201812 kb
Host smart-31b4afe2-d55a-40c1-afe9-3d202bc76750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420537112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.3420537112
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.599264210
Short name T850
Test name
Test status
Simulation time 2102693967 ps
CPU time 6.5 seconds
Started Apr 28 12:22:02 PM PDT 24
Finished Apr 28 12:22:12 PM PDT 24
Peak memory 199096 kb
Host smart-c45883b2-7af4-409c-9bfc-4d80b3b65f6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599264210 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.599264210
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2374317383
Short name T884
Test name
Test status
Simulation time 2120800766 ps
CPU time 2.32 seconds
Started Apr 28 12:22:02 PM PDT 24
Finished Apr 28 12:22:07 PM PDT 24
Peak memory 199104 kb
Host smart-37d4406a-b66a-4916-8de2-453c5475457a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374317383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.2374317383
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1575891048
Short name T910
Test name
Test status
Simulation time 2021564666 ps
CPU time 3.29 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:22:10 PM PDT 24
Peak memory 200872 kb
Host smart-bed93849-d77c-4804-9318-d5750976cc8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575891048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.1575891048
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3525793230
Short name T20
Test name
Test status
Simulation time 4818024246 ps
CPU time 2.91 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:19 PM PDT 24
Peak memory 201836 kb
Host smart-bbe09ffb-7e40-4e8e-84d3-4cde296e7cc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525793230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.3525793230
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1401017140
Short name T865
Test name
Test status
Simulation time 2076994090 ps
CPU time 4.64 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:21 PM PDT 24
Peak memory 201716 kb
Host smart-ec1b88a3-a60a-47d3-98dd-148e8f83a652
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401017140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.1401017140
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1508322737
Short name T828
Test name
Test status
Simulation time 2153137099 ps
CPU time 2.23 seconds
Started Apr 28 12:18:09 PM PDT 24
Finished Apr 28 12:18:11 PM PDT 24
Peak memory 201676 kb
Host smart-0b02bbe3-bf28-469c-a8ed-5c6b834a6b7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508322737 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1508322737
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2103584748
Short name T27
Test name
Test status
Simulation time 2049625816 ps
CPU time 3.12 seconds
Started Apr 28 12:20:17 PM PDT 24
Finished Apr 28 12:20:21 PM PDT 24
Peak memory 201584 kb
Host smart-21456002-0383-4963-ac88-edb05c8bae2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103584748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.2103584748
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.4019293713
Short name T889
Test name
Test status
Simulation time 2008747902 ps
CPU time 6.03 seconds
Started Apr 28 12:22:58 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 199564 kb
Host smart-3e2aed96-b2b1-494c-8366-731d90469bd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019293713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.4019293713
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3755310820
Short name T855
Test name
Test status
Simulation time 9941838182 ps
CPU time 13.62 seconds
Started Apr 28 12:22:12 PM PDT 24
Finished Apr 28 12:22:29 PM PDT 24
Peak memory 201640 kb
Host smart-6cd8a6a3-cc94-4154-8d4a-a4d3c289153e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755310820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.3755310820
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1317700808
Short name T257
Test name
Test status
Simulation time 3577598619 ps
CPU time 2.83 seconds
Started Apr 28 12:23:07 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 209568 kb
Host smart-1605613a-b36f-4c0e-bb72-bccfa7d8b229
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317700808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.1317700808
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2573183800
Short name T833
Test name
Test status
Simulation time 22241358930 ps
CPU time 59.54 seconds
Started Apr 28 12:19:32 PM PDT 24
Finished Apr 28 12:20:32 PM PDT 24
Peak memory 201624 kb
Host smart-49e2a9fe-f2ad-4cc3-a8a4-67372e52c47d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573183800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.2573183800
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.1899258540
Short name T547
Test name
Test status
Simulation time 2009953548 ps
CPU time 6.2 seconds
Started Apr 28 12:21:55 PM PDT 24
Finished Apr 28 12:22:06 PM PDT 24
Peak memory 201500 kb
Host smart-dfb7d9e9-e287-4b43-9d66-2c631d3d0669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899258540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.1899258540
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1649188878
Short name T42
Test name
Test status
Simulation time 3615269083 ps
CPU time 9.75 seconds
Started Apr 28 12:21:08 PM PDT 24
Finished Apr 28 12:21:19 PM PDT 24
Peak memory 201864 kb
Host smart-a70017b4-5ef2-4641-9cff-d176456ef848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649188878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.1649188878
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.2736356587
Short name T318
Test name
Test status
Simulation time 225569995025 ps
CPU time 148.6 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:24:46 PM PDT 24
Peak memory 200332 kb
Host smart-1592f4ca-80ec-4304-b76d-4259fe4759a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736356587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.2736356587
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1896679747
Short name T795
Test name
Test status
Simulation time 2424240547 ps
CPU time 2.22 seconds
Started Apr 28 12:19:40 PM PDT 24
Finished Apr 28 12:19:43 PM PDT 24
Peak memory 201708 kb
Host smart-6c4b4961-0d70-42ba-8de4-bf36176b0af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896679747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.1896679747
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1287531104
Short name T550
Test name
Test status
Simulation time 2530258827 ps
CPU time 3.83 seconds
Started Apr 28 12:19:12 PM PDT 24
Finished Apr 28 12:19:16 PM PDT 24
Peak memory 201728 kb
Host smart-3f70498a-ff66-4672-b6e5-02463dc2aa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287531104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1287531104
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.4262614523
Short name T379
Test name
Test status
Simulation time 2566328287 ps
CPU time 2.25 seconds
Started Apr 28 12:22:20 PM PDT 24
Finished Apr 28 12:22:24 PM PDT 24
Peak memory 201688 kb
Host smart-7a4b56bd-8cad-4560-a523-1b1c57e651e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262614523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.4262614523
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.4137744089
Short name T147
Test name
Test status
Simulation time 4411783164 ps
CPU time 1.66 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:01 PM PDT 24
Peak memory 201604 kb
Host smart-9fb6a615-a8a1-41c0-bf1d-7e58fd43dcb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137744089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.4137744089
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.299436314
Short name T434
Test name
Test status
Simulation time 2610805388 ps
CPU time 8.15 seconds
Started Apr 28 12:20:10 PM PDT 24
Finished Apr 28 12:20:19 PM PDT 24
Peak memory 201752 kb
Host smart-15cbde49-516d-4d62-ac77-2880f493a3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299436314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.299436314
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.1971364477
Short name T61
Test name
Test status
Simulation time 2458068430 ps
CPU time 7.25 seconds
Started Apr 28 12:22:58 PM PDT 24
Finished Apr 28 12:23:15 PM PDT 24
Peak memory 200188 kb
Host smart-2571355f-e193-41e1-b0fa-3aeef91ace81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971364477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.1971364477
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1601553012
Short name T466
Test name
Test status
Simulation time 2235778718 ps
CPU time 6.96 seconds
Started Apr 28 12:17:58 PM PDT 24
Finished Apr 28 12:18:06 PM PDT 24
Peak memory 201716 kb
Host smart-94851c30-9d30-4ea0-b21f-cfb93b950d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601553012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.1601553012
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.3507102599
Short name T783
Test name
Test status
Simulation time 2512388300 ps
CPU time 7.26 seconds
Started Apr 28 12:20:18 PM PDT 24
Finished Apr 28 12:20:26 PM PDT 24
Peak memory 201848 kb
Host smart-584310e5-d2b4-4644-9518-f2479ae775dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507102599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.3507102599
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.4255227874
Short name T246
Test name
Test status
Simulation time 42312625285 ps
CPU time 11.95 seconds
Started Apr 28 12:21:55 PM PDT 24
Finished Apr 28 12:22:11 PM PDT 24
Peak memory 220952 kb
Host smart-27fe1526-7cee-4fd9-8db6-7d86c12f58fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255227874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.4255227874
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.4108189960
Short name T792
Test name
Test status
Simulation time 2137714007 ps
CPU time 1.93 seconds
Started Apr 28 12:23:07 PM PDT 24
Finished Apr 28 12:23:13 PM PDT 24
Peak memory 201260 kb
Host smart-612e7f51-52db-49b1-9209-e372a792a497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108189960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.4108189960
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.433403860
Short name T194
Test name
Test status
Simulation time 8396937331 ps
CPU time 23.5 seconds
Started Apr 28 12:18:09 PM PDT 24
Finished Apr 28 12:18:33 PM PDT 24
Peak memory 201436 kb
Host smart-1a430457-a4d3-448f-9519-9cc89d8c3c80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433403860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_str
ess_all.433403860
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2126806572
Short name T361
Test name
Test status
Simulation time 21291540880 ps
CPU time 29.13 seconds
Started Apr 28 12:22:34 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 210348 kb
Host smart-b6fcb2fa-0f48-433c-ad63-c2a97bb3cba5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126806572 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.2126806572
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.207697313
Short name T575
Test name
Test status
Simulation time 11509868538 ps
CPU time 6.86 seconds
Started Apr 28 12:22:21 PM PDT 24
Finished Apr 28 12:22:29 PM PDT 24
Peak memory 201712 kb
Host smart-21fbed22-1aae-4504-a489-7e7f19035ec6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207697313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_ultra_low_pwr.207697313
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.1858670427
Short name T598
Test name
Test status
Simulation time 2016929013 ps
CPU time 3.3 seconds
Started Apr 28 12:20:21 PM PDT 24
Finished Apr 28 12:20:25 PM PDT 24
Peak memory 201792 kb
Host smart-ad568caf-346e-42f9-83eb-6bf3de59cadc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858670427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.1858670427
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.270252063
Short name T106
Test name
Test status
Simulation time 3847654259 ps
CPU time 3.16 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:22:10 PM PDT 24
Peak memory 201752 kb
Host smart-e403209e-0a7b-4747-8709-a44201178fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270252063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.270252063
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2510474188
Short name T477
Test name
Test status
Simulation time 2262083382 ps
CPU time 1.41 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 201640 kb
Host smart-fbd26c1d-c5a1-47af-be1d-4162b88395f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510474188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.2510474188
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1609993662
Short name T611
Test name
Test status
Simulation time 2341376441 ps
CPU time 3.7 seconds
Started Apr 28 12:21:55 PM PDT 24
Finished Apr 28 12:22:03 PM PDT 24
Peak memory 201420 kb
Host smart-82a02e82-54ee-4453-8ea5-e903e37fd53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609993662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1609993662
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.2097677811
Short name T595
Test name
Test status
Simulation time 2816962637 ps
CPU time 2.49 seconds
Started Apr 28 12:18:08 PM PDT 24
Finished Apr 28 12:18:11 PM PDT 24
Peak memory 201700 kb
Host smart-c6dbb1e2-a740-4631-bfcf-5825cabc622f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097677811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.2097677811
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.2894978199
Short name T765
Test name
Test status
Simulation time 2610645815 ps
CPU time 8.31 seconds
Started Apr 28 12:20:07 PM PDT 24
Finished Apr 28 12:20:16 PM PDT 24
Peak memory 201756 kb
Host smart-22e067db-5a47-44a5-b04f-9c7d3491ea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894978199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.2894978199
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.3754071277
Short name T407
Test name
Test status
Simulation time 2462826123 ps
CPU time 7.92 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:24 PM PDT 24
Peak memory 201664 kb
Host smart-5d38d3c0-8bc7-469b-aabb-9a42b779cb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754071277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.3754071277
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.542662413
Short name T646
Test name
Test status
Simulation time 2112539787 ps
CPU time 1.93 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:03 PM PDT 24
Peak memory 201628 kb
Host smart-ec9d08da-da16-4dc9-a155-47febad726e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542662413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.542662413
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.4266520933
Short name T680
Test name
Test status
Simulation time 2507025731 ps
CPU time 7.13 seconds
Started Apr 28 12:20:43 PM PDT 24
Finished Apr 28 12:20:51 PM PDT 24
Peak memory 201504 kb
Host smart-085cc3ff-24c5-49b3-9b66-e21ab76ff5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266520933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.4266520933
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2166685417
Short name T245
Test name
Test status
Simulation time 42610435012 ps
CPU time 6.72 seconds
Started Apr 28 12:22:57 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 221236 kb
Host smart-f0d34e0a-85b2-46bb-8db6-0272e6299cf9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166685417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.2166685417
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.665325159
Short name T467
Test name
Test status
Simulation time 2110796044 ps
CPU time 5.58 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 201528 kb
Host smart-30e7bb8d-ab70-4574-8f75-f8b40dc68d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665325159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.665325159
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.1707047617
Short name T17
Test name
Test status
Simulation time 7055696693 ps
CPU time 19.15 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:22:15 PM PDT 24
Peak memory 201424 kb
Host smart-d8bf3804-d840-4f57-bc0f-d04ac15fbea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707047617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.1707047617
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.3953129577
Short name T203
Test name
Test status
Simulation time 2027473422 ps
CPU time 1.57 seconds
Started Apr 28 12:22:18 PM PDT 24
Finished Apr 28 12:22:21 PM PDT 24
Peak memory 201340 kb
Host smart-bb39fae2-dd78-4da5-be5e-b84fc63b556e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953129577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.3953129577
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.4244644614
Short name T518
Test name
Test status
Simulation time 3664878918 ps
CPU time 10.16 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 201184 kb
Host smart-b320f3f8-3dfd-4e4d-b111-d25faed69488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244644614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.4
244644614
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.2073569518
Short name T583
Test name
Test status
Simulation time 127563635564 ps
CPU time 329.67 seconds
Started Apr 28 12:22:12 PM PDT 24
Finished Apr 28 12:27:45 PM PDT 24
Peak memory 201832 kb
Host smart-f2136f41-39d7-4b25-a56b-273d43d3a11a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073569518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.2073569518
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.1350654539
Short name T522
Test name
Test status
Simulation time 3610511662 ps
CPU time 2.88 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:51 PM PDT 24
Peak memory 201088 kb
Host smart-0c25cc88-96f7-4325-b1b6-a534202d3f3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350654539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.1350654539
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.1758023610
Short name T707
Test name
Test status
Simulation time 2560603995 ps
CPU time 0.98 seconds
Started Apr 28 12:20:17 PM PDT 24
Finished Apr 28 12:20:19 PM PDT 24
Peak memory 201676 kb
Host smart-be11f376-0154-4fe7-8fde-3c8464935f60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758023610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.1758023610
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3183853088
Short name T365
Test name
Test status
Simulation time 2621329897 ps
CPU time 3.78 seconds
Started Apr 28 12:22:43 PM PDT 24
Finished Apr 28 12:22:53 PM PDT 24
Peak memory 201344 kb
Host smart-9c6b45a4-7206-4deb-afd3-9c54e2405a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183853088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.3183853088
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.981745520
Short name T468
Test name
Test status
Simulation time 2568084770 ps
CPU time 1.25 seconds
Started Apr 28 12:23:02 PM PDT 24
Finished Apr 28 12:23:11 PM PDT 24
Peak memory 199972 kb
Host smart-59278b68-7e7d-4660-b3cc-8c15669194e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981745520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.981745520
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.1746722234
Short name T441
Test name
Test status
Simulation time 2211298704 ps
CPU time 2.24 seconds
Started Apr 28 12:20:37 PM PDT 24
Finished Apr 28 12:20:40 PM PDT 24
Peak memory 201716 kb
Host smart-a835c564-06e9-456f-bf5e-cab9b014180c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746722234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.1746722234
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.3414820231
Short name T621
Test name
Test status
Simulation time 2517935617 ps
CPU time 3.97 seconds
Started Apr 28 12:19:57 PM PDT 24
Finished Apr 28 12:20:01 PM PDT 24
Peak memory 201836 kb
Host smart-0ade78a7-176b-46c2-a3cb-66182428ac70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414820231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.3414820231
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.2219359134
Short name T634
Test name
Test status
Simulation time 2114218566 ps
CPU time 3.27 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 201288 kb
Host smart-979f8de3-3ec1-46c8-8daf-1b9e329bce48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219359134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.2219359134
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.2908490828
Short name T495
Test name
Test status
Simulation time 7855768800 ps
CPU time 5.94 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:23:04 PM PDT 24
Peak memory 201164 kb
Host smart-2f23d60f-e5da-4574-9fb9-edff266fa7b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908490828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.2908490828
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.309001705
Short name T200
Test name
Test status
Simulation time 47319924898 ps
CPU time 116.19 seconds
Started Apr 28 12:22:11 PM PDT 24
Finished Apr 28 12:24:10 PM PDT 24
Peak memory 210324 kb
Host smart-dfc16455-1558-463b-b032-b797811d7ab1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309001705 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.309001705
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.503349507
Short name T279
Test name
Test status
Simulation time 4757292111 ps
CPU time 6.83 seconds
Started Apr 28 12:20:01 PM PDT 24
Finished Apr 28 12:20:08 PM PDT 24
Peak memory 201424 kb
Host smart-eeef1253-b18e-4f91-a23d-29c9085f832e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503349507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_ultra_low_pwr.503349507
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.2094646888
Short name T443
Test name
Test status
Simulation time 2030653268 ps
CPU time 1.9 seconds
Started Apr 28 12:20:22 PM PDT 24
Finished Apr 28 12:20:24 PM PDT 24
Peak memory 201784 kb
Host smart-e3a615b1-803d-464d-bdbd-da3c9bc66831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094646888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.2094646888
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.499585541
Short name T530
Test name
Test status
Simulation time 3454328431 ps
CPU time 9.09 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:08 PM PDT 24
Peak memory 201536 kb
Host smart-9b746f8a-774b-4032-b93a-8552b1ceb3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499585541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.499585541
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.1634137282
Short name T316
Test name
Test status
Simulation time 57545720080 ps
CPU time 144.37 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:25:28 PM PDT 24
Peak memory 201800 kb
Host smart-dd175045-d35a-44d2-9916-827d3bf68bdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634137282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.1634137282
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2875947235
Short name T516
Test name
Test status
Simulation time 3390708250 ps
CPU time 2.28 seconds
Started Apr 28 12:22:17 PM PDT 24
Finished Apr 28 12:22:22 PM PDT 24
Peak memory 199964 kb
Host smart-52626f8e-446d-4707-a0c0-51cc57bf916a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875947235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.2875947235
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.1851550746
Short name T752
Test name
Test status
Simulation time 2686949110 ps
CPU time 2.22 seconds
Started Apr 28 12:22:45 PM PDT 24
Finished Apr 28 12:22:55 PM PDT 24
Peak memory 201408 kb
Host smart-bb337332-24eb-4694-8cd1-fb134f9de1a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851550746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.1851550746
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.4182308832
Short name T377
Test name
Test status
Simulation time 2616701632 ps
CPU time 3.88 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:21:58 PM PDT 24
Peak memory 200968 kb
Host smart-061302d2-d0a1-4414-ab08-6871cc058be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182308832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.4182308832
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.897260086
Short name T560
Test name
Test status
Simulation time 2503446928 ps
CPU time 2.25 seconds
Started Apr 28 12:22:17 PM PDT 24
Finished Apr 28 12:22:22 PM PDT 24
Peak memory 200592 kb
Host smart-86001a20-fb44-4433-838c-068d571d85a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897260086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.897260086
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.2641490488
Short name T661
Test name
Test status
Simulation time 2076637928 ps
CPU time 2.03 seconds
Started Apr 28 12:22:17 PM PDT 24
Finished Apr 28 12:22:21 PM PDT 24
Peak memory 200220 kb
Host smart-1f34060e-affd-45e9-881d-9f9b2ef3c235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641490488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.2641490488
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.1303860198
Short name T766
Test name
Test status
Simulation time 2527165114 ps
CPU time 2.27 seconds
Started Apr 28 12:22:34 PM PDT 24
Finished Apr 28 12:22:39 PM PDT 24
Peak memory 200284 kb
Host smart-2c517289-e8a5-41d9-b590-cb45b5581d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303860198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.1303860198
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.4017207432
Short name T775
Test name
Test status
Simulation time 2125299775 ps
CPU time 2.22 seconds
Started Apr 28 12:22:18 PM PDT 24
Finished Apr 28 12:22:22 PM PDT 24
Peak memory 201208 kb
Host smart-9bcf3ef3-260f-4a11-b48d-32c8933a0178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017207432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.4017207432
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.1946911866
Short name T87
Test name
Test status
Simulation time 324191271733 ps
CPU time 779.99 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:36:04 PM PDT 24
Peak memory 201812 kb
Host smart-7940352b-ca87-4293-abe2-541de7859f48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946911866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.1946911866
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3561426997
Short name T248
Test name
Test status
Simulation time 1138916912083 ps
CPU time 391.26 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:29:14 PM PDT 24
Peak memory 208812 kb
Host smart-28a6aea8-b4e2-4a67-a9e2-4b5ed5ca42db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561426997 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.3561426997
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1877344080
Short name T455
Test name
Test status
Simulation time 5013054783 ps
CPU time 2.3 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:21:57 PM PDT 24
Peak memory 200568 kb
Host smart-54b73006-b507-42a5-8f58-a3a27fcc9c2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877344080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.1877344080
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.2265043481
Short name T754
Test name
Test status
Simulation time 3743300479 ps
CPU time 8.9 seconds
Started Apr 28 12:22:10 PM PDT 24
Finished Apr 28 12:22:21 PM PDT 24
Peak memory 198908 kb
Host smart-4de7b9bb-5d30-4582-a2b9-1ae538c45140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265043481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.2
265043481
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.3670991848
Short name T704
Test name
Test status
Simulation time 162862239044 ps
CPU time 108.7 seconds
Started Apr 28 12:21:51 PM PDT 24
Finished Apr 28 12:23:42 PM PDT 24
Peak memory 201588 kb
Host smart-8ae60856-b952-45e9-b469-1126bf7e823d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670991848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.3670991848
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2847896080
Short name T66
Test name
Test status
Simulation time 86256524145 ps
CPU time 219.29 seconds
Started Apr 28 12:22:10 PM PDT 24
Finished Apr 28 12:25:52 PM PDT 24
Peak memory 199840 kb
Host smart-6d41ca87-edda-48f7-9d92-6eca39802e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847896080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.2847896080
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2426963363
Short name T189
Test name
Test status
Simulation time 1613312164359 ps
CPU time 207.35 seconds
Started Apr 28 12:22:11 PM PDT 24
Finished Apr 28 12:25:41 PM PDT 24
Peak memory 201324 kb
Host smart-92e00a67-fd9f-44fb-af2b-0cd7fd2ffcf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426963363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.2426963363
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.1770562779
Short name T36
Test name
Test status
Simulation time 3723984505 ps
CPU time 3.74 seconds
Started Apr 28 12:22:03 PM PDT 24
Finished Apr 28 12:22:09 PM PDT 24
Peak memory 199796 kb
Host smart-0d894ca0-f849-4e15-9d2f-ed96d058ff52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770562779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.1770562779
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.420690419
Short name T623
Test name
Test status
Simulation time 2616454841 ps
CPU time 3.29 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:01 PM PDT 24
Peak memory 199800 kb
Host smart-043b5a46-252e-4a08-bb60-c159cc767834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420690419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.420690419
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.3960808258
Short name T571
Test name
Test status
Simulation time 2507129622 ps
CPU time 1.77 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 201596 kb
Host smart-56a2f719-778a-4fd7-9ce3-2a9d8f2b8d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960808258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.3960808258
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.204133697
Short name T366
Test name
Test status
Simulation time 2198770504 ps
CPU time 1.93 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 201596 kb
Host smart-7479b839-70fe-4613-8a28-e52df8a885f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204133697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.204133697
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.3585210717
Short name T605
Test name
Test status
Simulation time 2507885289 ps
CPU time 7.24 seconds
Started Apr 28 12:21:55 PM PDT 24
Finished Apr 28 12:22:06 PM PDT 24
Peak memory 201480 kb
Host smart-b4aa6b15-cd55-4021-97ef-6fe44c9637ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585210717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.3585210717
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.3661527683
Short name T699
Test name
Test status
Simulation time 2114129828 ps
CPU time 5.72 seconds
Started Apr 28 12:20:21 PM PDT 24
Finished Apr 28 12:20:28 PM PDT 24
Peak memory 201644 kb
Host smart-8579ed1e-f702-41a4-b815-9e503ef34142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661527683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.3661527683
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.2507819989
Short name T264
Test name
Test status
Simulation time 10162017536 ps
CPU time 28.47 seconds
Started Apr 28 12:22:10 PM PDT 24
Finished Apr 28 12:22:41 PM PDT 24
Peak memory 201324 kb
Host smart-7f69b585-d31e-4791-beb8-c834db41346d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507819989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.2507819989
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.587762102
Short name T270
Test name
Test status
Simulation time 24239421163 ps
CPU time 60.59 seconds
Started Apr 28 12:22:10 PM PDT 24
Finished Apr 28 12:23:13 PM PDT 24
Peak memory 201772 kb
Host smart-82ccc0f4-ec25-44af-a6d3-e97d81021abf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587762102 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.587762102
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2739662958
Short name T736
Test name
Test status
Simulation time 6972768323 ps
CPU time 2.13 seconds
Started Apr 28 12:22:10 PM PDT 24
Finished Apr 28 12:22:14 PM PDT 24
Peak memory 199084 kb
Host smart-bf20c166-db39-4cf3-87fc-a5ad96c97486
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739662958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.2739662958
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.2005960554
Short name T494
Test name
Test status
Simulation time 2054317709 ps
CPU time 1.23 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:21:56 PM PDT 24
Peak memory 201396 kb
Host smart-8357d1fd-eaf3-4b0a-80c1-6d5c34591915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005960554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.2005960554
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.370085449
Short name T456
Test name
Test status
Simulation time 3737886776 ps
CPU time 1.62 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:42 PM PDT 24
Peak memory 200464 kb
Host smart-466a18c0-2c23-4d5b-95d5-3fd865557a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370085449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.370085449
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.1962519945
Short name T233
Test name
Test status
Simulation time 124154094889 ps
CPU time 334.66 seconds
Started Apr 28 12:20:28 PM PDT 24
Finished Apr 28 12:26:04 PM PDT 24
Peak memory 201968 kb
Host smart-1662169d-20c5-43f0-8079-639e2aa22d09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962519945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.1962519945
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.531350386
Short name T762
Test name
Test status
Simulation time 3621835020 ps
CPU time 3.33 seconds
Started Apr 28 12:20:33 PM PDT 24
Finished Apr 28 12:20:37 PM PDT 24
Peak memory 201632 kb
Host smart-3b3b6382-c87c-4c33-91ec-a272b886f6d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531350386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_ec_pwr_on_rst.531350386
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.2361702128
Short name T213
Test name
Test status
Simulation time 3022205028 ps
CPU time 7.18 seconds
Started Apr 28 12:21:53 PM PDT 24
Finished Apr 28 12:22:03 PM PDT 24
Peak memory 201424 kb
Host smart-88da74a3-564e-465d-b30b-97f7c62067cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361702128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.2361702128
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2820158172
Short name T197
Test name
Test status
Simulation time 2623291481 ps
CPU time 2.58 seconds
Started Apr 28 12:22:10 PM PDT 24
Finished Apr 28 12:22:15 PM PDT 24
Peak memory 199004 kb
Host smart-e692a028-f6f3-442c-bd5a-3c0572080b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820158172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.2820158172
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.3359447491
Short name T293
Test name
Test status
Simulation time 2459675476 ps
CPU time 7.08 seconds
Started Apr 28 12:21:50 PM PDT 24
Finished Apr 28 12:21:59 PM PDT 24
Peak memory 199940 kb
Host smart-0dbe72cc-4159-4885-af62-1649a061030d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359447491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.3359447491
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.2800867308
Short name T684
Test name
Test status
Simulation time 2133340802 ps
CPU time 2.04 seconds
Started Apr 28 12:22:10 PM PDT 24
Finished Apr 28 12:22:14 PM PDT 24
Peak memory 199100 kb
Host smart-62e2db78-aab4-44f7-bc7f-02cfe9cc4dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800867308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.2800867308
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.1838132355
Short name T639
Test name
Test status
Simulation time 2515154763 ps
CPU time 3.85 seconds
Started Apr 28 12:22:03 PM PDT 24
Finished Apr 28 12:22:10 PM PDT 24
Peak memory 201428 kb
Host smart-18bcfc15-df5b-43e5-b9dc-6771f96408d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838132355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.1838132355
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.1469597550
Short name T206
Test name
Test status
Simulation time 2194823086 ps
CPU time 0.88 seconds
Started Apr 28 12:21:51 PM PDT 24
Finished Apr 28 12:21:53 PM PDT 24
Peak memory 201380 kb
Host smart-d790745f-c192-4c48-9d98-f39fc4c4f7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469597550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.1469597550
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.2902121572
Short name T319
Test name
Test status
Simulation time 139709791221 ps
CPU time 366.1 seconds
Started Apr 28 12:20:28 PM PDT 24
Finished Apr 28 12:26:35 PM PDT 24
Peak memory 202000 kb
Host smart-a16aa11f-d84f-4310-9354-7627c07b6587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902121572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_s
tress_all.2902121572
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3878322335
Short name T558
Test name
Test status
Simulation time 3797734575 ps
CPU time 3.52 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:02 PM PDT 24
Peak memory 201376 kb
Host smart-24f1d241-501a-423a-82cc-4001f413f2d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878322335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.3878322335
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.2198457625
Short name T712
Test name
Test status
Simulation time 2023902520 ps
CPU time 3.21 seconds
Started Apr 28 12:22:10 PM PDT 24
Finished Apr 28 12:22:16 PM PDT 24
Peak memory 199000 kb
Host smart-0b3360cd-f286-4e9f-a71f-1e8a9a276992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198457625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.2198457625
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.4057037986
Short name T47
Test name
Test status
Simulation time 251093412886 ps
CPU time 149.08 seconds
Started Apr 28 12:21:53 PM PDT 24
Finished Apr 28 12:24:25 PM PDT 24
Peak memory 201472 kb
Host smart-3e561bed-81d5-4d2f-ba88-7e670f8b593b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057037986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.4
057037986
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.1525627424
Short name T587
Test name
Test status
Simulation time 106229632602 ps
CPU time 75.37 seconds
Started Apr 28 12:22:04 PM PDT 24
Finished Apr 28 12:23:22 PM PDT 24
Peak memory 201856 kb
Host smart-2d46c1ba-8ee0-4fc4-9856-f00fd308c269
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525627424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.1525627424
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2747592373
Short name T501
Test name
Test status
Simulation time 57181540960 ps
CPU time 38.96 seconds
Started Apr 28 12:23:07 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 201536 kb
Host smart-c1a46e48-9ecc-4857-8b5c-33025c2198d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747592373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.2747592373
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1909333903
Short name T383
Test name
Test status
Simulation time 3349169647 ps
CPU time 9.48 seconds
Started Apr 28 12:20:40 PM PDT 24
Finished Apr 28 12:20:50 PM PDT 24
Peak memory 201776 kb
Host smart-c28054d1-a456-447d-b31d-224396ae06b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909333903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.1909333903
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1415265819
Short name T791
Test name
Test status
Simulation time 2613752405 ps
CPU time 7.73 seconds
Started Apr 28 12:21:51 PM PDT 24
Finished Apr 28 12:21:59 PM PDT 24
Peak memory 200716 kb
Host smart-8f114aae-d11a-442d-8ed1-309d324264ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415265819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.1415265819
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.616876817
Short name T787
Test name
Test status
Simulation time 2445496147 ps
CPU time 3.78 seconds
Started Apr 28 12:21:53 PM PDT 24
Finished Apr 28 12:22:00 PM PDT 24
Peak memory 201416 kb
Host smart-de920acf-28bd-4251-898d-245c7aa147d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616876817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.616876817
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.3278115919
Short name T420
Test name
Test status
Simulation time 2280477589 ps
CPU time 2.21 seconds
Started Apr 28 12:20:30 PM PDT 24
Finished Apr 28 12:20:32 PM PDT 24
Peak memory 201768 kb
Host smart-e4625169-773f-49de-801c-d58c413feff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278115919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.3278115919
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.3744110953
Short name T658
Test name
Test status
Simulation time 2529399930 ps
CPU time 2.3 seconds
Started Apr 28 12:21:53 PM PDT 24
Finished Apr 28 12:21:59 PM PDT 24
Peak memory 200472 kb
Host smart-bb710cfc-6a40-49a3-bcc6-4108dc3a42f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744110953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.3744110953
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.2216435206
Short name T559
Test name
Test status
Simulation time 2115750554 ps
CPU time 3.61 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:21:58 PM PDT 24
Peak memory 199676 kb
Host smart-40b55595-312b-4b52-a816-0a28ef86e4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216435206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.2216435206
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.2976707149
Short name T586
Test name
Test status
Simulation time 109045352603 ps
CPU time 78.02 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:24:18 PM PDT 24
Peak memory 201664 kb
Host smart-e55d84d7-6d15-49bf-b522-0d92c9074dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976707149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.2976707149
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3001276098
Short name T119
Test name
Test status
Simulation time 9069173624 ps
CPU time 2.48 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:01 PM PDT 24
Peak memory 201348 kb
Host smart-74fa3e74-f599-4f2d-bbfc-1fb289a666e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001276098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.3001276098
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.1341120326
Short name T630
Test name
Test status
Simulation time 2026570433 ps
CPU time 2.82 seconds
Started Apr 28 12:21:05 PM PDT 24
Finished Apr 28 12:21:08 PM PDT 24
Peak memory 201820 kb
Host smart-975a59d9-e159-4065-9bbe-58b2d97767e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341120326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_te
st.1341120326
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.2656563856
Short name T100
Test name
Test status
Simulation time 122760101850 ps
CPU time 165.71 seconds
Started Apr 28 12:20:56 PM PDT 24
Finished Apr 28 12:23:42 PM PDT 24
Peak memory 201920 kb
Host smart-10087cea-5a36-4c41-9ea7-da378f411e0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656563856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.2656563856
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.414276778
Short name T677
Test name
Test status
Simulation time 40310928487 ps
CPU time 58.75 seconds
Started Apr 28 12:20:54 PM PDT 24
Finished Apr 28 12:21:54 PM PDT 24
Peak memory 201928 kb
Host smart-55c77879-c044-4fdf-903e-1b268c6d3d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414276778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_wi
th_pre_cond.414276778
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2049927505
Short name T592
Test name
Test status
Simulation time 2969626368 ps
CPU time 2.6 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:22:20 PM PDT 24
Peak memory 200112 kb
Host smart-bad33548-3d18-42bb-813d-8ea3b635e1e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049927505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.2049927505
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.151786029
Short name T481
Test name
Test status
Simulation time 2400681416 ps
CPU time 1.16 seconds
Started Apr 28 12:20:55 PM PDT 24
Finished Apr 28 12:20:57 PM PDT 24
Peak memory 201764 kb
Host smart-cf50ca12-47a3-40f0-aea9-517aca36fe3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151786029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctr
l_edge_detect.151786029
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.4269698436
Short name T139
Test name
Test status
Simulation time 2647099295 ps
CPU time 1.89 seconds
Started Apr 28 12:20:49 PM PDT 24
Finished Apr 28 12:20:52 PM PDT 24
Peak memory 201428 kb
Host smart-ea4f04c5-beba-41fd-84fb-91c2ca12adc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269698436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.4269698436
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.2736058763
Short name T600
Test name
Test status
Simulation time 2491912822 ps
CPU time 2.62 seconds
Started Apr 28 12:20:45 PM PDT 24
Finished Apr 28 12:20:48 PM PDT 24
Peak memory 201464 kb
Host smart-a7405979-c9a4-46dd-9a77-c70fa564165e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736058763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.2736058763
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.3516145583
Short name T107
Test name
Test status
Simulation time 2206586061 ps
CPU time 3.81 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:22:21 PM PDT 24
Peak memory 199752 kb
Host smart-4c33c3d9-55d7-4bf0-a1c0-fa71a20cecf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516145583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.3516145583
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.3993340697
Short name T276
Test name
Test status
Simulation time 2536821616 ps
CPU time 2.41 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:22:20 PM PDT 24
Peak memory 199876 kb
Host smart-2301a2d4-5c8c-453f-a752-91e4e42c3628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993340697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.3993340697
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.3862956304
Short name T389
Test name
Test status
Simulation time 2115479030 ps
CPU time 6.06 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:04 PM PDT 24
Peak memory 201220 kb
Host smart-138184d7-20a0-4037-9d90-7312f534d5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862956304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.3862956304
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.3502473554
Short name T8
Test name
Test status
Simulation time 9623240068 ps
CPU time 6.5 seconds
Started Apr 28 12:21:02 PM PDT 24
Finished Apr 28 12:21:09 PM PDT 24
Peak memory 201720 kb
Host smart-2043f01b-e206-4d30-85b7-285116b5f188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502473554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.3502473554
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.767405393
Short name T113
Test name
Test status
Simulation time 23991929473 ps
CPU time 67.55 seconds
Started Apr 28 12:21:04 PM PDT 24
Finished Apr 28 12:22:12 PM PDT 24
Peak memory 210296 kb
Host smart-4e6d4503-6e70-4b3a-ae14-06e097f5ce7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767405393 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.767405393
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3979664302
Short name T519
Test name
Test status
Simulation time 9267948443 ps
CPU time 7.08 seconds
Started Apr 28 12:23:46 PM PDT 24
Finished Apr 28 12:23:55 PM PDT 24
Peak memory 201720 kb
Host smart-953a012f-f268-446f-8c39-dbfb645ea1e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979664302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.3979664302
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.2620228447
Short name T297
Test name
Test status
Simulation time 2010269535 ps
CPU time 5.8 seconds
Started Apr 28 12:22:46 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 200380 kb
Host smart-f157c0f6-0052-443f-9aab-6d75f1ff4824
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620228447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te
st.2620228447
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.408332306
Short name T568
Test name
Test status
Simulation time 2999722556 ps
CPU time 8.03 seconds
Started Apr 28 12:21:07 PM PDT 24
Finished Apr 28 12:21:15 PM PDT 24
Peak memory 201784 kb
Host smart-c05eb486-fa71-44e6-b9c5-365002dc78ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408332306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.408332306
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.3274674142
Short name T745
Test name
Test status
Simulation time 101392015789 ps
CPU time 246.23 seconds
Started Apr 28 12:21:16 PM PDT 24
Finished Apr 28 12:25:23 PM PDT 24
Peak memory 201908 kb
Host smart-15f3e7cd-10a0-4d9a-8428-f26bbe4f1b8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274674142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.3274674142
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1168447625
Short name T542
Test name
Test status
Simulation time 4023414808 ps
CPU time 3.1 seconds
Started Apr 28 12:21:05 PM PDT 24
Finished Apr 28 12:21:09 PM PDT 24
Peak memory 201736 kb
Host smart-b7f6a7aa-b68f-49ec-8fb7-ade81db0ee6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168447625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.1168447625
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.2945286562
Short name T171
Test name
Test status
Simulation time 3190361198 ps
CPU time 2.89 seconds
Started Apr 28 12:21:07 PM PDT 24
Finished Apr 28 12:21:11 PM PDT 24
Peak memory 201812 kb
Host smart-0fc04260-887d-40a9-abe0-c096494394e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945286562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.2945286562
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3686641059
Short name T140
Test name
Test status
Simulation time 2610098331 ps
CPU time 7.22 seconds
Started Apr 28 12:23:32 PM PDT 24
Finished Apr 28 12:23:39 PM PDT 24
Peak memory 201756 kb
Host smart-3d1a50cf-9648-4fd5-af5a-c42472aa7eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686641059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.3686641059
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.2918707356
Short name T647
Test name
Test status
Simulation time 2462677846 ps
CPU time 6.63 seconds
Started Apr 28 12:21:06 PM PDT 24
Finished Apr 28 12:21:13 PM PDT 24
Peak memory 201752 kb
Host smart-3bbc5789-60a6-4702-a02a-fb2035d050f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918707356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.2918707356
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.3734602858
Short name T491
Test name
Test status
Simulation time 2216260153 ps
CPU time 4.69 seconds
Started Apr 28 12:23:35 PM PDT 24
Finished Apr 28 12:23:40 PM PDT 24
Peak memory 201692 kb
Host smart-9a3057ec-237d-4f94-8f04-4478e696ee8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734602858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.3734602858
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2783021007
Short name T761
Test name
Test status
Simulation time 2509557840 ps
CPU time 6.97 seconds
Started Apr 28 12:23:45 PM PDT 24
Finished Apr 28 12:23:54 PM PDT 24
Peak memory 201784 kb
Host smart-f08e6d6f-733b-4248-bf9b-fea3da398b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783021007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.2783021007
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.661562463
Short name T690
Test name
Test status
Simulation time 2150292702 ps
CPU time 1.25 seconds
Started Apr 28 12:21:02 PM PDT 24
Finished Apr 28 12:21:04 PM PDT 24
Peak memory 201692 kb
Host smart-575b9bef-a034-4eb9-ac51-dfa6d8fce615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661562463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.661562463
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.226340880
Short name T192
Test name
Test status
Simulation time 175679227439 ps
CPU time 121.03 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:24:57 PM PDT 24
Peak memory 201540 kb
Host smart-1298bbb1-062f-4edc-be45-eb258c17c9d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226340880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_st
ress_all.226340880
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.996141278
Short name T507
Test name
Test status
Simulation time 5411595290 ps
CPU time 7.83 seconds
Started Apr 28 12:21:07 PM PDT 24
Finished Apr 28 12:21:15 PM PDT 24
Peak memory 201748 kb
Host smart-c1cfdba9-1bf0-49b0-9260-72597fa5c514
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996141278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_ultra_low_pwr.996141278
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.174429476
Short name T569
Test name
Test status
Simulation time 2088103971 ps
CPU time 1.27 seconds
Started Apr 28 12:22:46 PM PDT 24
Finished Apr 28 12:22:57 PM PDT 24
Peak memory 200308 kb
Host smart-c664ab0a-7e3e-4d8a-a180-b69288eb4612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174429476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_tes
t.174429476
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.4001239145
Short name T267
Test name
Test status
Simulation time 3355127290 ps
CPU time 8.95 seconds
Started Apr 28 12:21:12 PM PDT 24
Finished Apr 28 12:21:21 PM PDT 24
Peak memory 201812 kb
Host smart-d851f514-1fdc-4b0e-a092-22bc848fc9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001239145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.4
001239145
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.4157083600
Short name T325
Test name
Test status
Simulation time 80120468859 ps
CPU time 48.39 seconds
Started Apr 28 12:21:16 PM PDT 24
Finished Apr 28 12:22:04 PM PDT 24
Peak memory 201936 kb
Host smart-12ecc514-e625-4f99-955a-806ca4c75bca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157083600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.4157083600
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1872506089
Short name T612
Test name
Test status
Simulation time 297114061243 ps
CPU time 836.57 seconds
Started Apr 28 12:21:08 PM PDT 24
Finished Apr 28 12:35:06 PM PDT 24
Peak memory 201748 kb
Host smart-ee78cd27-0101-4fa1-bf8b-a46717968418
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872506089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.1872506089
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.797357745
Short name T198
Test name
Test status
Simulation time 3924696960 ps
CPU time 11.07 seconds
Started Apr 28 12:21:22 PM PDT 24
Finished Apr 28 12:21:34 PM PDT 24
Peak memory 201716 kb
Host smart-5b6394d7-e517-447b-a719-14450c6a111a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797357745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctr
l_edge_detect.797357745
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.367684592
Short name T524
Test name
Test status
Simulation time 2607988577 ps
CPU time 7.77 seconds
Started Apr 28 12:21:16 PM PDT 24
Finished Apr 28 12:21:24 PM PDT 24
Peak memory 201676 kb
Host smart-6bc891fd-6a13-47ce-a29e-d557c4c12dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367684592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.367684592
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.1468290780
Short name T655
Test name
Test status
Simulation time 2467009298 ps
CPU time 6.52 seconds
Started Apr 28 12:21:11 PM PDT 24
Finished Apr 28 12:21:18 PM PDT 24
Peak memory 201752 kb
Host smart-13448443-7e89-416e-8fc4-9c02229b164b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468290780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.1468290780
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.3479659182
Short name T368
Test name
Test status
Simulation time 2269566197 ps
CPU time 2.06 seconds
Started Apr 28 12:21:07 PM PDT 24
Finished Apr 28 12:21:10 PM PDT 24
Peak memory 201708 kb
Host smart-a90e9982-ccbb-40ca-b3c3-67e78e7ba183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479659182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.3479659182
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.823133993
Short name T685
Test name
Test status
Simulation time 2526761576 ps
CPU time 2.4 seconds
Started Apr 28 12:21:16 PM PDT 24
Finished Apr 28 12:21:19 PM PDT 24
Peak memory 201760 kb
Host smart-c3f25b81-96c6-4a26-8a49-fc6c7840cb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823133993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.823133993
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.765425362
Short name T454
Test name
Test status
Simulation time 2112202708 ps
CPU time 6.04 seconds
Started Apr 28 12:22:46 PM PDT 24
Finished Apr 28 12:23:01 PM PDT 24
Peak memory 201568 kb
Host smart-9710c98f-461b-4a30-8dfe-834467e6e900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765425362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.765425362
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.93460768
Short name T535
Test name
Test status
Simulation time 9486726977 ps
CPU time 12.26 seconds
Started Apr 28 12:21:08 PM PDT 24
Finished Apr 28 12:21:21 PM PDT 24
Peak memory 201432 kb
Host smart-ff38eedd-2888-4476-8756-b11a734706ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93460768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_str
ess_all.93460768
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3533435874
Short name T602
Test name
Test status
Simulation time 55753001083 ps
CPU time 137.08 seconds
Started Apr 28 12:23:25 PM PDT 24
Finished Apr 28 12:25:43 PM PDT 24
Peak memory 218512 kb
Host smart-30d2833d-b71e-4ec6-af02-d9d88db8587d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533435874 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.3533435874
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3232513318
Short name T645
Test name
Test status
Simulation time 7056140572 ps
CPU time 2.28 seconds
Started Apr 28 12:21:21 PM PDT 24
Finished Apr 28 12:21:24 PM PDT 24
Peak memory 201808 kb
Host smart-e3df917e-7dd1-4c40-9ab8-164093b4d8ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232513318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.3232513318
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.925319785
Short name T449
Test name
Test status
Simulation time 2013645297 ps
CPU time 5.88 seconds
Started Apr 28 12:22:55 PM PDT 24
Finished Apr 28 12:23:12 PM PDT 24
Peak memory 201716 kb
Host smart-d46400ab-1bf7-47fb-ae02-7cc28d531eff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925319785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_tes
t.925319785
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.727878687
Short name T671
Test name
Test status
Simulation time 3198953810 ps
CPU time 2.83 seconds
Started Apr 28 12:23:02 PM PDT 24
Finished Apr 28 12:23:12 PM PDT 24
Peak memory 200240 kb
Host smart-2c347627-04d4-4ba2-b237-d7b0626af01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727878687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.727878687
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3847423584
Short name T789
Test name
Test status
Simulation time 89915195909 ps
CPU time 56.28 seconds
Started Apr 28 12:23:02 PM PDT 24
Finished Apr 28 12:24:06 PM PDT 24
Peak memory 200872 kb
Host smart-96000953-9b88-4c2e-a8be-f49173d6e636
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847423584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.3847423584
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1817839153
Short name T588
Test name
Test status
Simulation time 71966775195 ps
CPU time 100.99 seconds
Started Apr 28 12:21:23 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 202008 kb
Host smart-bd4a4f33-d76f-4373-9941-1c1a1c120374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817839153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_w
ith_pre_cond.1817839153
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1783651738
Short name T460
Test name
Test status
Simulation time 3263464981 ps
CPU time 9.83 seconds
Started Apr 28 12:23:02 PM PDT 24
Finished Apr 28 12:23:19 PM PDT 24
Peak memory 199944 kb
Host smart-04f4f412-d540-4932-a4eb-9a2d0012fcf7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783651738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.1783651738
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.545512121
Short name T500
Test name
Test status
Simulation time 3000325479 ps
CPU time 6.89 seconds
Started Apr 28 12:21:24 PM PDT 24
Finished Apr 28 12:21:31 PM PDT 24
Peak memory 201680 kb
Host smart-25fc44e9-8992-4ae4-968d-8b8b1d92b0ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545512121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctr
l_edge_detect.545512121
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3808156571
Short name T691
Test name
Test status
Simulation time 2608187893 ps
CPU time 8.06 seconds
Started Apr 28 12:21:24 PM PDT 24
Finished Apr 28 12:21:33 PM PDT 24
Peak memory 201728 kb
Host smart-f436380e-ce08-40c0-ace8-7d6dcf3b6954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808156571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.3808156571
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.472451148
Short name T689
Test name
Test status
Simulation time 2466231742 ps
CPU time 5.07 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:23:03 PM PDT 24
Peak memory 201312 kb
Host smart-ed9b4a79-7cab-48a4-accf-3771d0bca8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472451148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.472451148
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.742166168
Short name T215
Test name
Test status
Simulation time 2120937192 ps
CPU time 6.03 seconds
Started Apr 28 12:21:22 PM PDT 24
Finished Apr 28 12:21:28 PM PDT 24
Peak memory 201692 kb
Host smart-9db27755-00d8-4332-b9db-58c1cdcc1727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742166168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.742166168
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.1466084299
Short name T410
Test name
Test status
Simulation time 2531623674 ps
CPU time 3.2 seconds
Started Apr 28 12:22:46 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 200448 kb
Host smart-b17d5eed-cdd8-431c-a899-8b96aa2424f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466084299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.1466084299
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.3218943490
Short name T14
Test name
Test status
Simulation time 2109421170 ps
CPU time 6.55 seconds
Started Apr 28 12:21:25 PM PDT 24
Finished Apr 28 12:21:32 PM PDT 24
Peak memory 201652 kb
Host smart-1ae65016-2eeb-44e3-9d07-e5341c0823a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218943490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.3218943490
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.730028673
Short name T429
Test name
Test status
Simulation time 9089194637 ps
CPU time 24.06 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:23:28 PM PDT 24
Peak memory 201644 kb
Host smart-cedff254-672c-4db5-a5cc-99bf380087da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730028673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_st
ress_all.730028673
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3222078473
Short name T282
Test name
Test status
Simulation time 1098562650041 ps
CPU time 294.05 seconds
Started Apr 28 12:21:33 PM PDT 24
Finished Apr 28 12:26:28 PM PDT 24
Peak memory 218496 kb
Host smart-c395febd-eaac-4148-934e-b2f08b8ff033
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222078473 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.3222078473
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1628539104
Short name T116
Test name
Test status
Simulation time 5934071214 ps
CPU time 7.23 seconds
Started Apr 28 12:23:03 PM PDT 24
Finished Apr 28 12:23:17 PM PDT 24
Peak memory 201296 kb
Host smart-fed067d8-9f8e-4c03-9b9a-cf1275967750
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628539104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.1628539104
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.1199618839
Short name T729
Test name
Test status
Simulation time 2031710315 ps
CPU time 2.18 seconds
Started Apr 28 12:21:41 PM PDT 24
Finished Apr 28 12:21:44 PM PDT 24
Peak memory 201880 kb
Host smart-4caf4641-f78c-4b6b-a4d0-67f58992bf3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199618839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.1199618839
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1566368679
Short name T593
Test name
Test status
Simulation time 3793543254 ps
CPU time 2.64 seconds
Started Apr 28 12:22:54 PM PDT 24
Finished Apr 28 12:23:07 PM PDT 24
Peak memory 201708 kb
Host smart-9b2cc7b4-5536-4d86-b014-cb2487756d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566368679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.1
566368679
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.1734479139
Short name T317
Test name
Test status
Simulation time 137657475796 ps
CPU time 353.12 seconds
Started Apr 28 12:21:31 PM PDT 24
Finished Apr 28 12:27:25 PM PDT 24
Peak memory 201976 kb
Host smart-fdcd5858-2f2a-48e6-991d-7100bcd90643
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734479139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.1734479139
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3800864120
Short name T96
Test name
Test status
Simulation time 45533803479 ps
CPU time 70.28 seconds
Started Apr 28 12:21:37 PM PDT 24
Finished Apr 28 12:22:47 PM PDT 24
Peak memory 201956 kb
Host smart-123dba0c-fbc5-4a5f-b6cd-daa97929dd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800864120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.3800864120
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.927410652
Short name T473
Test name
Test status
Simulation time 3759105624 ps
CPU time 2.69 seconds
Started Apr 28 12:21:33 PM PDT 24
Finished Apr 28 12:21:36 PM PDT 24
Peak memory 201660 kb
Host smart-99dd3d26-f8f1-48f2-8cc7-a6e186512252
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927410652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ec_pwr_on_rst.927410652
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.2982946055
Short name T744
Test name
Test status
Simulation time 4064950811 ps
CPU time 1.17 seconds
Started Apr 28 12:21:33 PM PDT 24
Finished Apr 28 12:21:35 PM PDT 24
Peak memory 201756 kb
Host smart-c3517d50-32e0-4b1c-b7eb-b8395aab956a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982946055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.2982946055
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2880306
Short name T187
Test name
Test status
Simulation time 2611640619 ps
CPU time 7.48 seconds
Started Apr 28 12:22:39 PM PDT 24
Finished Apr 28 12:22:52 PM PDT 24
Peak memory 200060 kb
Host smart-6d85e6aa-037e-4cc6-83ab-c504dcb0d2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.2880306
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.1981755282
Short name T597
Test name
Test status
Simulation time 2464805069 ps
CPU time 6.93 seconds
Started Apr 28 12:22:54 PM PDT 24
Finished Apr 28 12:23:11 PM PDT 24
Peak memory 201652 kb
Host smart-38a07eae-329f-45b2-8385-8acbf4950b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981755282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.1981755282
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.2333606256
Short name T666
Test name
Test status
Simulation time 2255363688 ps
CPU time 6.85 seconds
Started Apr 28 12:21:26 PM PDT 24
Finished Apr 28 12:21:34 PM PDT 24
Peak memory 201780 kb
Host smart-002d376e-5f0d-4d97-814c-07dcadaf2fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333606256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.2333606256
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.46934941
Short name T479
Test name
Test status
Simulation time 2542734920 ps
CPU time 1.74 seconds
Started Apr 28 12:21:23 PM PDT 24
Finished Apr 28 12:21:26 PM PDT 24
Peak memory 201832 kb
Host smart-f2722fa9-3b03-4182-b4e7-f33268793534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46934941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.46934941
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.906905632
Short name T604
Test name
Test status
Simulation time 2117660162 ps
CPU time 3.36 seconds
Started Apr 28 12:21:22 PM PDT 24
Finished Apr 28 12:21:26 PM PDT 24
Peak memory 201352 kb
Host smart-04f60e25-0517-4289-9cff-4bcf34c55b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906905632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.906905632
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.409158565
Short name T134
Test name
Test status
Simulation time 93004863359 ps
CPU time 228.6 seconds
Started Apr 28 12:21:39 PM PDT 24
Finished Apr 28 12:25:28 PM PDT 24
Peak memory 201908 kb
Host smart-26d46644-a0d5-4813-8082-70baf0c86600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409158565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_st
ress_all.409158565
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2971766856
Short name T44
Test name
Test status
Simulation time 29073584748 ps
CPU time 18.07 seconds
Started Apr 28 12:21:34 PM PDT 24
Finished Apr 28 12:21:53 PM PDT 24
Peak memory 210412 kb
Host smart-e7845225-06ec-4672-a8d1-e86a61ac21ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971766856 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.2971766856
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.204029068
Short name T50
Test name
Test status
Simulation time 3365922521 ps
CPU time 5.76 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:49 PM PDT 24
Peak memory 200108 kb
Host smart-99fa4b2c-8883-41b3-8daa-354ef8561f62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204029068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ultra_low_pwr.204029068
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.2733565063
Short name T430
Test name
Test status
Simulation time 2025896963 ps
CPU time 1.82 seconds
Started Apr 28 12:22:59 PM PDT 24
Finished Apr 28 12:23:10 PM PDT 24
Peak memory 201796 kb
Host smart-1fb86671-c09e-4bb7-891c-f260f2b4e934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733565063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.2733565063
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.3645338233
Short name T184
Test name
Test status
Simulation time 85137301822 ps
CPU time 164.12 seconds
Started Apr 28 12:22:03 PM PDT 24
Finished Apr 28 12:24:50 PM PDT 24
Peak memory 200036 kb
Host smart-f194b03a-6078-4641-ab54-3f830a0ff35b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645338233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.3645338233
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3198955232
Short name T475
Test name
Test status
Simulation time 2221217589 ps
CPU time 3.24 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:51 PM PDT 24
Peak memory 201416 kb
Host smart-c136e9d9-02ec-4d98-b576-56a90474be91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198955232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.3198955232
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2634894737
Short name T570
Test name
Test status
Simulation time 2359049551 ps
CPU time 6.82 seconds
Started Apr 28 12:17:10 PM PDT 24
Finished Apr 28 12:17:18 PM PDT 24
Peak memory 201708 kb
Host smart-4d84ca58-1cdf-4b03-9da2-635e358fe130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634894737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2634894737
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1792635744
Short name T345
Test name
Test status
Simulation time 51775425393 ps
CPU time 35.32 seconds
Started Apr 28 12:22:35 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 201660 kb
Host smart-22cd6c83-4a63-4ba3-91f7-fc84e4c359ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792635744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.1792635744
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.2556554822
Short name T582
Test name
Test status
Simulation time 3895264924 ps
CPU time 5.44 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 201508 kb
Host smart-ff1bf133-f378-4ef8-9d6a-d587f573fe0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556554822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.2556554822
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3805576480
Short name T577
Test name
Test status
Simulation time 2627009496 ps
CPU time 2.36 seconds
Started Apr 28 12:21:10 PM PDT 24
Finished Apr 28 12:21:13 PM PDT 24
Peak memory 201776 kb
Host smart-1e6e45d4-a73d-410e-9d21-748b16b3367b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805576480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.3805576480
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.3743898086
Short name T296
Test name
Test status
Simulation time 2448496576 ps
CPU time 8.13 seconds
Started Apr 28 12:21:57 PM PDT 24
Finished Apr 28 12:22:09 PM PDT 24
Peak memory 200636 kb
Host smart-05f9b0c5-1a80-43e7-b76c-5be87cc777ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743898086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.3743898086
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.1477582647
Short name T285
Test name
Test status
Simulation time 2179684932 ps
CPU time 2.36 seconds
Started Apr 28 12:22:37 PM PDT 24
Finished Apr 28 12:22:45 PM PDT 24
Peak memory 200372 kb
Host smart-ec96d993-589f-4614-b170-1eb9c996b468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477582647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.1477582647
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.3387906465
Short name T735
Test name
Test status
Simulation time 2522380551 ps
CPU time 4.26 seconds
Started Apr 28 12:21:58 PM PDT 24
Finished Apr 28 12:22:05 PM PDT 24
Peak memory 201096 kb
Host smart-8c2bdfa1-3865-427f-b5b6-ca7e9ad021db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387906465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.3387906465
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.1766653090
Short name T260
Test name
Test status
Simulation time 42152576772 ps
CPU time 22.75 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:24 PM PDT 24
Peak memory 221496 kb
Host smart-a5f4777d-aba1-4fc2-9bb0-c2dec0d1e5b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766653090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.1766653090
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.1212316179
Short name T459
Test name
Test status
Simulation time 2134316177 ps
CPU time 2.06 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:00 PM PDT 24
Peak memory 199652 kb
Host smart-5276fa73-7082-4cbd-b71f-7fff2dfb08c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212316179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.1212316179
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.3142848116
Short name T241
Test name
Test status
Simulation time 39386328515 ps
CPU time 97.42 seconds
Started Apr 28 12:20:11 PM PDT 24
Finished Apr 28 12:21:49 PM PDT 24
Peak memory 201916 kb
Host smart-26d20324-2fe9-4752-af22-e7192fdc0dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142848116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.3142848116
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1244078105
Short name T289
Test name
Test status
Simulation time 80629398071 ps
CPU time 99.23 seconds
Started Apr 28 12:18:09 PM PDT 24
Finished Apr 28 12:19:49 PM PDT 24
Peak memory 210364 kb
Host smart-084f12d5-756d-4207-bd60-d2c5d0e985c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244078105 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.1244078105
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.913723253
Short name T362
Test name
Test status
Simulation time 1113473836804 ps
CPU time 89.89 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:23:47 PM PDT 24
Peak memory 201772 kb
Host smart-20829af2-0265-48b9-b247-c9f69ec0cf4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913723253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_ultra_low_pwr.913723253
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.3374578296
Short name T544
Test name
Test status
Simulation time 2082720453 ps
CPU time 1.1 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:21:58 PM PDT 24
Peak memory 201804 kb
Host smart-2716b3aa-3503-4907-96fa-b12d9d7f3184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374578296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.3374578296
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.4201613273
Short name T405
Test name
Test status
Simulation time 3271053489 ps
CPU time 8.91 seconds
Started Apr 28 12:21:45 PM PDT 24
Finished Apr 28 12:21:55 PM PDT 24
Peak memory 201808 kb
Host smart-1ac0ca0a-f505-49ae-89b5-d34d5078de58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201613273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.4
201613273
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.828126766
Short name T232
Test name
Test status
Simulation time 35422836818 ps
CPU time 96.05 seconds
Started Apr 28 12:21:51 PM PDT 24
Finished Apr 28 12:23:29 PM PDT 24
Peak memory 201984 kb
Host smart-6d44fd2d-f7b3-4ca4-b39d-869a27d0d4da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828126766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_combo_detect.828126766
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1884208801
Short name T324
Test name
Test status
Simulation time 99137372917 ps
CPU time 67.77 seconds
Started Apr 28 12:21:51 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 201992 kb
Host smart-5237e835-e301-4e99-b186-0085ca03a6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884208801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.1884208801
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.739662960
Short name T513
Test name
Test status
Simulation time 2899063608 ps
CPU time 8.52 seconds
Started Apr 28 12:21:51 PM PDT 24
Finished Apr 28 12:22:02 PM PDT 24
Peak memory 201728 kb
Host smart-4b458049-4a66-46c8-b961-f870592d3890
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739662960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_ec_pwr_on_rst.739662960
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.868433827
Short name T733
Test name
Test status
Simulation time 2634165819 ps
CPU time 2.43 seconds
Started Apr 28 12:21:44 PM PDT 24
Finished Apr 28 12:21:47 PM PDT 24
Peak memory 201744 kb
Host smart-53e8b6e4-804c-4ab3-a31f-f5d13a982fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868433827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.868433827
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.1755702023
Short name T486
Test name
Test status
Simulation time 2474405580 ps
CPU time 4.39 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 201608 kb
Host smart-ce17fd60-b150-4ea4-a575-0599435c07bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755702023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.1755702023
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.2649436107
Short name T531
Test name
Test status
Simulation time 2210578025 ps
CPU time 1.14 seconds
Started Apr 28 12:21:39 PM PDT 24
Finished Apr 28 12:21:41 PM PDT 24
Peak memory 201440 kb
Host smart-4fbba4de-454a-41ed-97a7-c429e9f60e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649436107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.2649436107
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.1417297243
Short name T515
Test name
Test status
Simulation time 2578677609 ps
CPU time 1.23 seconds
Started Apr 28 12:21:42 PM PDT 24
Finished Apr 28 12:21:44 PM PDT 24
Peak memory 201508 kb
Host smart-d7607cfe-eb1c-4b9b-ba27-d0f922e9bcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417297243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.1417297243
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.1766996482
Short name T432
Test name
Test status
Simulation time 2134362055 ps
CPU time 1.99 seconds
Started Apr 28 12:21:41 PM PDT 24
Finished Apr 28 12:21:44 PM PDT 24
Peak memory 201652 kb
Host smart-efbc58a7-ce7d-4cc8-85d2-1f8c6eea88e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766996482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1766996482
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.1339052471
Short name T464
Test name
Test status
Simulation time 130566927301 ps
CPU time 331.56 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:27:28 PM PDT 24
Peak memory 202036 kb
Host smart-591fc918-66d5-491d-8f9b-2552656bb63c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339052471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.1339052471
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.467388461
Short name T135
Test name
Test status
Simulation time 923220889251 ps
CPU time 110.87 seconds
Started Apr 28 12:21:45 PM PDT 24
Finished Apr 28 12:23:37 PM PDT 24
Peak memory 215036 kb
Host smart-d931bcbf-6c05-41ac-bf0b-f5c08c347f2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467388461 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.467388461
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2456323926
Short name T136
Test name
Test status
Simulation time 761021577118 ps
CPU time 45.97 seconds
Started Apr 28 12:21:51 PM PDT 24
Finished Apr 28 12:22:39 PM PDT 24
Peak memory 201752 kb
Host smart-d93456dc-784d-45cf-b6df-5c065334d5d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456323926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.2456323926
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.532717635
Short name T159
Test name
Test status
Simulation time 2037542651 ps
CPU time 2.13 seconds
Started Apr 28 12:21:59 PM PDT 24
Finished Apr 28 12:22:03 PM PDT 24
Peak memory 201812 kb
Host smart-e080bed8-e6b9-4041-b2bb-a6230c7aa1ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532717635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_tes
t.532717635
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.595408648
Short name T208
Test name
Test status
Simulation time 2845337255 ps
CPU time 5.47 seconds
Started Apr 28 12:21:48 PM PDT 24
Finished Apr 28 12:21:54 PM PDT 24
Peak memory 201808 kb
Host smart-bd40b274-326c-4af4-9d4f-4984efd761cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595408648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.595408648
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.2279313225
Short name T777
Test name
Test status
Simulation time 43374131872 ps
CPU time 108.58 seconds
Started Apr 28 12:23:05 PM PDT 24
Finished Apr 28 12:25:00 PM PDT 24
Peak memory 200960 kb
Host smart-a5aea185-b080-498a-bed8-1f316793778e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279313225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.2279313225
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.400275580
Short name T228
Test name
Test status
Simulation time 54142018406 ps
CPU time 38.11 seconds
Started Apr 28 12:21:53 PM PDT 24
Finished Apr 28 12:22:34 PM PDT 24
Peak memory 202032 kb
Host smart-fb741084-eeb3-4501-b498-ddda6f9d07e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400275580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_wi
th_pre_cond.400275580
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.384730022
Short name T169
Test name
Test status
Simulation time 4285408083 ps
CPU time 11.48 seconds
Started Apr 28 12:21:51 PM PDT 24
Finished Apr 28 12:22:04 PM PDT 24
Peak memory 201664 kb
Host smart-df8c920e-3edb-4a0a-ab84-4d54c9a9b7f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384730022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_ec_pwr_on_rst.384730022
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.3641835762
Short name T37
Test name
Test status
Simulation time 442327959150 ps
CPU time 1044.3 seconds
Started Apr 28 12:24:28 PM PDT 24
Finished Apr 28 12:41:54 PM PDT 24
Peak memory 201680 kb
Host smart-bc4bc418-113d-4f79-966f-da2b4398df25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641835762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.3641835762
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3943041080
Short name T628
Test name
Test status
Simulation time 2621441926 ps
CPU time 2.36 seconds
Started Apr 28 12:21:49 PM PDT 24
Finished Apr 28 12:21:52 PM PDT 24
Peak memory 201776 kb
Host smart-81224e0b-072f-45d3-82e2-1e96146e94fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943041080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.3943041080
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.516405979
Short name T385
Test name
Test status
Simulation time 2467151052 ps
CPU time 7.79 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:22:02 PM PDT 24
Peak memory 201744 kb
Host smart-dbc52fd2-db38-47d6-9baa-897a657d6a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516405979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.516405979
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.362681639
Short name T525
Test name
Test status
Simulation time 2265605337 ps
CPU time 0.93 seconds
Started Apr 28 12:21:51 PM PDT 24
Finished Apr 28 12:21:53 PM PDT 24
Peak memory 201784 kb
Host smart-fc104643-3e68-4753-8ba7-af733385efa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362681639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.362681639
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.1500998673
Short name T629
Test name
Test status
Simulation time 2533585389 ps
CPU time 2.27 seconds
Started Apr 28 12:21:47 PM PDT 24
Finished Apr 28 12:21:50 PM PDT 24
Peak memory 201836 kb
Host smart-58bbcb2c-7dc7-40b6-a68f-fc1bb74c7237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500998673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.1500998673
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.2224176074
Short name T442
Test name
Test status
Simulation time 2136738062 ps
CPU time 1.89 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:21:56 PM PDT 24
Peak memory 201652 kb
Host smart-37cbf907-5461-48b4-a156-64e7ecdef994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224176074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.2224176074
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.3155720300
Short name T749
Test name
Test status
Simulation time 9588116429 ps
CPU time 5.14 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:48 PM PDT 24
Peak memory 201692 kb
Host smart-efb5c6a7-7446-4545-9731-cda8f898c54d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155720300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.3155720300
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.3030195998
Short name T445
Test name
Test status
Simulation time 2011901660 ps
CPU time 5.76 seconds
Started Apr 28 12:22:40 PM PDT 24
Finished Apr 28 12:22:51 PM PDT 24
Peak memory 201748 kb
Host smart-179a26ec-8049-4f69-82e7-d80ebc3baf4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030195998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.3030195998
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.4009877081
Short name T574
Test name
Test status
Simulation time 3625869873 ps
CPU time 2.06 seconds
Started Apr 28 12:22:05 PM PDT 24
Finished Apr 28 12:22:09 PM PDT 24
Peak memory 201808 kb
Host smart-47ea16cd-c81d-4710-bbeb-0eb266787529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009877081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.4
009877081
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.1150513675
Short name T352
Test name
Test status
Simulation time 105043360835 ps
CPU time 294.98 seconds
Started Apr 28 12:22:03 PM PDT 24
Finished Apr 28 12:27:01 PM PDT 24
Peak memory 202016 kb
Host smart-6c788f2c-5387-45ca-9d2c-bf9c9b4d88fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150513675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.1150513675
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.2805940602
Short name T669
Test name
Test status
Simulation time 4362999651 ps
CPU time 1.47 seconds
Started Apr 28 12:22:01 PM PDT 24
Finished Apr 28 12:22:04 PM PDT 24
Peak memory 201732 kb
Host smart-0475c0e8-b308-48d0-9ae9-71e8489cb8cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805940602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.2805940602
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.1318715504
Short name T151
Test name
Test status
Simulation time 3208413491 ps
CPU time 1.96 seconds
Started Apr 28 12:22:03 PM PDT 24
Finished Apr 28 12:22:08 PM PDT 24
Peak memory 201756 kb
Host smart-952ecf6b-cbfb-434c-8ebf-ee20f2136a67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318715504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.1318715504
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.517210577
Short name T374
Test name
Test status
Simulation time 2629625301 ps
CPU time 2.68 seconds
Started Apr 28 12:21:59 PM PDT 24
Finished Apr 28 12:22:03 PM PDT 24
Peak memory 201776 kb
Host smart-2e3301aa-c995-4283-b551-1719d4232147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517210577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.517210577
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.3067137610
Short name T549
Test name
Test status
Simulation time 2467711581 ps
CPU time 4.04 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:47 PM PDT 24
Peak memory 201692 kb
Host smart-b745cb82-8be8-46de-987c-8ceeb1ac5abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067137610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.3067137610
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.815520244
Short name T776
Test name
Test status
Simulation time 2257577914 ps
CPU time 2.15 seconds
Started Apr 28 12:21:56 PM PDT 24
Finished Apr 28 12:22:02 PM PDT 24
Peak memory 201732 kb
Host smart-7792f32c-ecda-4ee0-8c59-5b50e1fbfa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815520244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.815520244
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.149816370
Short name T277
Test name
Test status
Simulation time 2659354669 ps
CPU time 1.25 seconds
Started Apr 28 12:22:26 PM PDT 24
Finished Apr 28 12:22:28 PM PDT 24
Peak memory 201824 kb
Host smart-141621e4-df07-4cfa-9147-6d16191e23c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149816370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.149816370
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.1333168496
Short name T555
Test name
Test status
Simulation time 2112161073 ps
CPU time 5.7 seconds
Started Apr 28 12:21:53 PM PDT 24
Finished Apr 28 12:22:01 PM PDT 24
Peak memory 201688 kb
Host smart-a769c5ec-fad1-4d49-bfaa-83c6028899fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333168496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.1333168496
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.400238538
Short name T562
Test name
Test status
Simulation time 295894495621 ps
CPU time 11.2 seconds
Started Apr 28 12:22:07 PM PDT 24
Finished Apr 28 12:22:20 PM PDT 24
Peak memory 201792 kb
Host smart-793efaa9-d578-4d4a-8030-bde701653415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400238538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_st
ress_all.400238538
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2034735187
Short name T283
Test name
Test status
Simulation time 360121786487 ps
CPU time 94 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:24:14 PM PDT 24
Peak memory 210420 kb
Host smart-d80995a8-705c-4a60-bfca-27588e0069a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034735187 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.2034735187
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.1774763218
Short name T553
Test name
Test status
Simulation time 6771053644 ps
CPU time 2.49 seconds
Started Apr 28 12:22:03 PM PDT 24
Finished Apr 28 12:22:08 PM PDT 24
Peak memory 201804 kb
Host smart-3f66a433-34de-4036-b149-401983bfcf46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774763218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.1774763218
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.1055429797
Short name T253
Test name
Test status
Simulation time 2033314749 ps
CPU time 1.96 seconds
Started Apr 28 12:22:28 PM PDT 24
Finished Apr 28 12:22:31 PM PDT 24
Peak memory 201780 kb
Host smart-4a838a45-3197-4382-b042-a519e88deb31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055429797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.1055429797
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3252189136
Short name T13
Test name
Test status
Simulation time 3187732104 ps
CPU time 5.04 seconds
Started Apr 28 12:22:12 PM PDT 24
Finished Apr 28 12:22:20 PM PDT 24
Peak memory 201816 kb
Host smart-faeb412f-4418-4e75-a53b-4d05f0603a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252189136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.3
252189136
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.207724933
Short name T552
Test name
Test status
Simulation time 26099679873 ps
CPU time 18.73 seconds
Started Apr 28 12:22:23 PM PDT 24
Finished Apr 28 12:22:42 PM PDT 24
Peak memory 202008 kb
Host smart-e540f169-ac71-4daf-887f-11657429f73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207724933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_wi
th_pre_cond.207724933
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3392931921
Short name T773
Test name
Test status
Simulation time 5560077905 ps
CPU time 15.1 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 201688 kb
Host smart-8e5f2407-4d4c-4289-aa32-7a8c2627afc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392931921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.3392931921
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.2568952854
Short name T201
Test name
Test status
Simulation time 3322132084 ps
CPU time 2.14 seconds
Started Apr 28 12:22:28 PM PDT 24
Finished Apr 28 12:22:31 PM PDT 24
Peak memory 201740 kb
Host smart-ffd118c0-e740-403a-a395-b55471f1b209
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568952854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.2568952854
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.1603889846
Short name T681
Test name
Test status
Simulation time 2629651677 ps
CPU time 2.44 seconds
Started Apr 28 12:22:22 PM PDT 24
Finished Apr 28 12:22:25 PM PDT 24
Peak memory 201780 kb
Host smart-e1df03eb-9e48-41fc-9188-b0b0ff0b268a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603889846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.1603889846
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.3474895023
Short name T702
Test name
Test status
Simulation time 2468501908 ps
CPU time 2.14 seconds
Started Apr 28 12:22:07 PM PDT 24
Finished Apr 28 12:22:11 PM PDT 24
Peak memory 201756 kb
Host smart-dda52044-8d68-4c19-8f87-d25add9c0410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474895023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.3474895023
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.426319948
Short name T476
Test name
Test status
Simulation time 2255389845 ps
CPU time 3.78 seconds
Started Apr 28 12:22:10 PM PDT 24
Finished Apr 28 12:22:17 PM PDT 24
Peak memory 201720 kb
Host smart-ff116822-c478-494e-822b-fad6a1b43f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426319948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.426319948
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.1761461366
Short name T278
Test name
Test status
Simulation time 2525479573 ps
CPU time 2.27 seconds
Started Apr 28 12:22:12 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 201812 kb
Host smart-b450ba17-5f7f-47a6-aa69-19e619f08cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761461366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.1761461366
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.1816399339
Short name T650
Test name
Test status
Simulation time 2110760885 ps
CPU time 6.31 seconds
Started Apr 28 12:22:11 PM PDT 24
Finished Apr 28 12:22:20 PM PDT 24
Peak memory 201652 kb
Host smart-1b9c1429-e86c-4700-b44a-9b601bc7f9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816399339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.1816399339
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.2259342573
Short name T607
Test name
Test status
Simulation time 8334794789 ps
CPU time 6.21 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:53 PM PDT 24
Peak memory 201680 kb
Host smart-9f1ba78b-f1f6-43e0-88f3-8befad8818de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259342573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.2259342573
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.1584196768
Short name T118
Test name
Test status
Simulation time 8869135612 ps
CPU time 8.38 seconds
Started Apr 28 12:22:43 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 201716 kb
Host smart-1d7086f7-b936-454d-abb8-0817289ac5bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584196768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.1584196768
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.4054436680
Short name T424
Test name
Test status
Simulation time 2023617430 ps
CPU time 1.85 seconds
Started Apr 28 12:22:31 PM PDT 24
Finished Apr 28 12:22:33 PM PDT 24
Peak memory 201816 kb
Host smart-5ad9f555-a20e-42aa-ac5b-e7fc52da20fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054436680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.4054436680
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3906010077
Short name T418
Test name
Test status
Simulation time 3443555721 ps
CPU time 1.21 seconds
Started Apr 28 12:22:32 PM PDT 24
Finished Apr 28 12:22:35 PM PDT 24
Peak memory 201868 kb
Host smart-06699e68-f7c1-4257-8c62-463f16f7e73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906010077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.3
906010077
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.2968230635
Short name T320
Test name
Test status
Simulation time 129386166311 ps
CPU time 364.83 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:28:48 PM PDT 24
Peak memory 201860 kb
Host smart-cdbe09c6-eee1-413f-8c5a-d173ba681a1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968230635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.2968230635
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.2910375302
Short name T427
Test name
Test status
Simulation time 3055767095 ps
CPU time 4.57 seconds
Started Apr 28 12:22:28 PM PDT 24
Finished Apr 28 12:22:34 PM PDT 24
Peak memory 201640 kb
Host smart-c64f25d7-215e-470b-b0ba-c76f158526df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910375302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.2910375302
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.2693504772
Short name T770
Test name
Test status
Simulation time 3613917088 ps
CPU time 1.19 seconds
Started Apr 28 12:22:33 PM PDT 24
Finished Apr 28 12:22:35 PM PDT 24
Peak memory 201416 kb
Host smart-97e320c9-764b-4e50-a809-72290168b55c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693504772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.2693504772
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3929306584
Short name T631
Test name
Test status
Simulation time 2621548509 ps
CPU time 2.36 seconds
Started Apr 28 12:22:25 PM PDT 24
Finished Apr 28 12:22:28 PM PDT 24
Peak memory 201756 kb
Host smart-d6ec6381-5651-4bb4-9dce-130c6b7ad262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929306584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.3929306584
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3453231066
Short name T480
Test name
Test status
Simulation time 2458291616 ps
CPU time 4.41 seconds
Started Apr 28 12:22:28 PM PDT 24
Finished Apr 28 12:22:34 PM PDT 24
Peak memory 201652 kb
Host smart-55e78701-4967-4dea-aecf-dbf6a05e7eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453231066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.3453231066
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.1043529015
Short name T287
Test name
Test status
Simulation time 2080785614 ps
CPU time 2.07 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:45 PM PDT 24
Peak memory 201620 kb
Host smart-fd47745b-3836-4a40-ad03-fd3d72864be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043529015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.1043529015
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.3462101357
Short name T275
Test name
Test status
Simulation time 2514353787 ps
CPU time 7.2 seconds
Started Apr 28 12:22:37 PM PDT 24
Finished Apr 28 12:22:49 PM PDT 24
Peak memory 201780 kb
Host smart-36c7c2e5-40c6-46e8-9564-b3cfe23d020b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462101357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.3462101357
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.3619884730
Short name T406
Test name
Test status
Simulation time 2126723098 ps
CPU time 1.85 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:22:53 PM PDT 24
Peak memory 201616 kb
Host smart-1c7deff2-f0b1-4101-a5dd-8c1ff7dcb4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619884730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.3619884730
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.391435730
Short name T572
Test name
Test status
Simulation time 14816982941 ps
CPU time 20.27 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:23:12 PM PDT 24
Peak memory 201712 kb
Host smart-65783f80-aa56-4520-9e79-b4b6553c0766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391435730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_st
ress_all.391435730
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1393231579
Short name T127
Test name
Test status
Simulation time 94654805126 ps
CPU time 66.37 seconds
Started Apr 28 12:23:43 PM PDT 24
Finished Apr 28 12:24:51 PM PDT 24
Peak memory 210420 kb
Host smart-19d117b6-9315-43d9-ab5e-582d60db16d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393231579 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.1393231579
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1502457220
Short name T89
Test name
Test status
Simulation time 7594454160 ps
CPU time 4.44 seconds
Started Apr 28 12:22:39 PM PDT 24
Finished Apr 28 12:22:49 PM PDT 24
Peak memory 201752 kb
Host smart-5b705a45-f0d4-4391-983a-00e5b26f315b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502457220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.1502457220
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.4055768331
Short name T737
Test name
Test status
Simulation time 2015477701 ps
CPU time 5.51 seconds
Started Apr 28 12:22:35 PM PDT 24
Finished Apr 28 12:22:45 PM PDT 24
Peak memory 201496 kb
Host smart-e3cae228-6944-41c0-827a-45a325ea61dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055768331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.4055768331
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1394247009
Short name T674
Test name
Test status
Simulation time 3478094389 ps
CPU time 9.23 seconds
Started Apr 28 12:23:29 PM PDT 24
Finished Apr 28 12:23:39 PM PDT 24
Peak memory 201472 kb
Host smart-f903a02d-d5f3-4fa0-9100-5d50eb3c8465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394247009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.1
394247009
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.1354193674
Short name T357
Test name
Test status
Simulation time 189726251691 ps
CPU time 48.81 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:51 PM PDT 24
Peak memory 201848 kb
Host smart-68b006d6-ef08-43d5-a0a5-3852f270db35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354193674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.1354193674
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.203140222
Short name T23
Test name
Test status
Simulation time 61966334739 ps
CPU time 165.67 seconds
Started Apr 28 12:22:33 PM PDT 24
Finished Apr 28 12:25:20 PM PDT 24
Peak memory 201496 kb
Host smart-a4db8e91-fdb2-4cd3-8ae4-f41954e97bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203140222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_wi
th_pre_cond.203140222
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.4221380700
Short name T382
Test name
Test status
Simulation time 3247492289 ps
CPU time 9.28 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:23:01 PM PDT 24
Peak memory 201688 kb
Host smart-c61cd650-c818-4c0f-8a5b-b214addbbfa8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221380700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.4221380700
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.1069537626
Short name T696
Test name
Test status
Simulation time 2549304718 ps
CPU time 6.83 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:22:58 PM PDT 24
Peak memory 201712 kb
Host smart-aea42ece-fc8f-4cbf-bca8-764b67c37aed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069537626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.1069537626
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1545327990
Short name T537
Test name
Test status
Simulation time 2610800815 ps
CPU time 7.28 seconds
Started Apr 28 12:22:38 PM PDT 24
Finished Apr 28 12:22:50 PM PDT 24
Peak memory 201688 kb
Host smart-188565c4-26d3-49c3-84b4-98dbc84c2f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545327990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.1545327990
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.905494653
Short name T273
Test name
Test status
Simulation time 2467111403 ps
CPU time 2.75 seconds
Started Apr 28 12:23:44 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 201432 kb
Host smart-8714d682-c4de-4a3a-bb3b-6478262e1c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905494653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.905494653
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.990898187
Short name T413
Test name
Test status
Simulation time 2193202886 ps
CPU time 1.95 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:22:54 PM PDT 24
Peak memory 201684 kb
Host smart-62f17145-02af-42d5-851c-5e81288fb70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990898187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.990898187
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.3781544077
Short name T292
Test name
Test status
Simulation time 2511996679 ps
CPU time 7.35 seconds
Started Apr 28 12:22:34 PM PDT 24
Finished Apr 28 12:22:43 PM PDT 24
Peak memory 201856 kb
Host smart-dc47b833-1c2b-4898-88ec-f8d30e33a2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781544077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.3781544077
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.4042127040
Short name T487
Test name
Test status
Simulation time 2124268440 ps
CPU time 1.88 seconds
Started Apr 28 12:22:43 PM PDT 24
Finished Apr 28 12:22:53 PM PDT 24
Peak memory 201616 kb
Host smart-5806e750-52a5-4aaa-b5d5-bf804cd8b5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042127040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.4042127040
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.3617921348
Short name T115
Test name
Test status
Simulation time 7364673665 ps
CPU time 17.11 seconds
Started Apr 28 12:22:33 PM PDT 24
Finished Apr 28 12:22:51 PM PDT 24
Peak memory 201416 kb
Host smart-2eedf605-ac91-4952-b019-63aef541d95d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617921348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.3617921348
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.4136121748
Short name T57
Test name
Test status
Simulation time 36946750867 ps
CPU time 19.87 seconds
Started Apr 28 12:22:33 PM PDT 24
Finished Apr 28 12:22:54 PM PDT 24
Peak memory 201836 kb
Host smart-2d5accbe-c5de-430e-9b74-e8f88cd89960
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136121748 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.4136121748
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2071337253
Short name T195
Test name
Test status
Simulation time 2978690933 ps
CPU time 4.14 seconds
Started Apr 28 12:22:32 PM PDT 24
Finished Apr 28 12:22:38 PM PDT 24
Peak memory 201780 kb
Host smart-c00f255b-4550-4125-b783-d12a736ba770
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071337253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.2071337253
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.2120191762
Short name T433
Test name
Test status
Simulation time 2013257287 ps
CPU time 5.87 seconds
Started Apr 28 12:23:29 PM PDT 24
Finished Apr 28 12:23:36 PM PDT 24
Peak memory 201752 kb
Host smart-cdcc77a4-69b3-4458-8282-8d7baeca6fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120191762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.2120191762
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2786785608
Short name T758
Test name
Test status
Simulation time 3795977290 ps
CPU time 10.57 seconds
Started Apr 28 12:23:52 PM PDT 24
Finished Apr 28 12:24:05 PM PDT 24
Peak memory 198736 kb
Host smart-b8e10b6e-4b6c-4333-a43a-584c549c54ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786785608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.2
786785608
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.3903518782
Short name T753
Test name
Test status
Simulation time 91295307785 ps
CPU time 59.58 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 201604 kb
Host smart-24181d81-6701-4ecc-a20d-04e57d4184f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903518782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.3903518782
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2183578825
Short name T341
Test name
Test status
Simulation time 83821909119 ps
CPU time 61.84 seconds
Started Apr 28 12:22:58 PM PDT 24
Finished Apr 28 12:24:09 PM PDT 24
Peak memory 201872 kb
Host smart-918320e2-30e4-466d-956d-edff9ecaef55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183578825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.2183578825
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.1788423229
Short name T369
Test name
Test status
Simulation time 3596478997 ps
CPU time 1.22 seconds
Started Apr 28 12:23:52 PM PDT 24
Finished Apr 28 12:23:56 PM PDT 24
Peak memory 198788 kb
Host smart-768e879d-2969-407e-9662-bb5472151460
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788423229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.1788423229
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.1444357451
Short name T202
Test name
Test status
Simulation time 5199358967 ps
CPU time 12.84 seconds
Started Apr 28 12:22:37 PM PDT 24
Finished Apr 28 12:22:55 PM PDT 24
Peak memory 201800 kb
Host smart-784ae67d-ac67-4499-ac5e-514769083b6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444357451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.1444357451
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.2490625628
Short name T388
Test name
Test status
Simulation time 2618269469 ps
CPU time 4.03 seconds
Started Apr 28 12:23:18 PM PDT 24
Finished Apr 28 12:23:23 PM PDT 24
Peak memory 201692 kb
Host smart-432c01a3-e2a6-463e-b906-bd48b9ea8214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490625628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.2490625628
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.1583648735
Short name T409
Test name
Test status
Simulation time 2476782573 ps
CPU time 2.18 seconds
Started Apr 28 12:22:35 PM PDT 24
Finished Apr 28 12:22:41 PM PDT 24
Peak memory 201648 kb
Host smart-fe1540a0-d188-491e-bb02-b0521a79c2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583648735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.1583648735
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.1755700399
Short name T104
Test name
Test status
Simulation time 2255959687 ps
CPU time 6.61 seconds
Started Apr 28 12:23:47 PM PDT 24
Finished Apr 28 12:23:56 PM PDT 24
Peak memory 201688 kb
Host smart-28145d94-adef-4a62-ab7e-9bb0953fbcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755700399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.1755700399
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3509799628
Short name T274
Test name
Test status
Simulation time 2519241283 ps
CPU time 3.85 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:22:55 PM PDT 24
Peak memory 201780 kb
Host smart-97e950b3-210e-4378-bff3-195a2d595a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509799628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3509799628
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.4225432636
Short name T622
Test name
Test status
Simulation time 2111890447 ps
CPU time 6.21 seconds
Started Apr 28 12:22:39 PM PDT 24
Finished Apr 28 12:22:51 PM PDT 24
Peak memory 201656 kb
Host smart-f738737e-8f8b-49b9-923e-eca087a87539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225432636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.4225432636
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.1782016022
Short name T632
Test name
Test status
Simulation time 80542237861 ps
CPU time 27.76 seconds
Started Apr 28 12:23:44 PM PDT 24
Finished Apr 28 12:24:15 PM PDT 24
Peak memory 201760 kb
Host smart-480d305e-8ec3-42db-bdcf-179bd75f527b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782016022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.1782016022
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.617392855
Short name T638
Test name
Test status
Simulation time 3196034632 ps
CPU time 2.14 seconds
Started Apr 28 12:23:34 PM PDT 24
Finished Apr 28 12:23:36 PM PDT 24
Peak memory 201400 kb
Host smart-510fd232-e5a4-4935-8787-171e3c37b8d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617392855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ultra_low_pwr.617392855
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.146885738
Short name T521
Test name
Test status
Simulation time 2017804278 ps
CPU time 3.28 seconds
Started Apr 28 12:23:36 PM PDT 24
Finished Apr 28 12:23:40 PM PDT 24
Peak memory 201540 kb
Host smart-5b8b662d-7bea-40e5-b701-298c5cfd4ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146885738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_tes
t.146885738
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.544057538
Short name T768
Test name
Test status
Simulation time 3246576897 ps
CPU time 4.67 seconds
Started Apr 28 12:23:13 PM PDT 24
Finished Apr 28 12:23:20 PM PDT 24
Peak memory 201724 kb
Host smart-90e618ba-348e-4065-87d0-7bb14abfd081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544057538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.544057538
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.1273061734
Short name T327
Test name
Test status
Simulation time 193562508466 ps
CPU time 148.61 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:25:30 PM PDT 24
Peak memory 201884 kb
Host smart-cd9350d3-c097-409d-9efe-daf8a8399525
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273061734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.1273061734
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.447917567
Short name T161
Test name
Test status
Simulation time 3624299418 ps
CPU time 10.36 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 201744 kb
Host smart-d667e08a-fc27-435d-960a-ac0e4e98f08c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447917567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_ec_pwr_on_rst.447917567
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.1530810248
Short name T578
Test name
Test status
Simulation time 3420779214 ps
CPU time 3.7 seconds
Started Apr 28 12:23:13 PM PDT 24
Finished Apr 28 12:23:18 PM PDT 24
Peak memory 201764 kb
Host smart-ff364e85-739e-4eb7-bfe2-d95a94636944
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530810248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.1530810248
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.636671084
Short name T764
Test name
Test status
Simulation time 2632828760 ps
CPU time 2.12 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:22:54 PM PDT 24
Peak memory 201624 kb
Host smart-7c0ffa76-1fef-4d8b-8708-3a6d4912fc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636671084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.636671084
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.2681265169
Short name T757
Test name
Test status
Simulation time 2456668245 ps
CPU time 3.66 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 200896 kb
Host smart-29fc268d-bf74-4008-aafd-910584132c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681265169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.2681265169
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.4089673109
Short name T397
Test name
Test status
Simulation time 2049487613 ps
CPU time 5.95 seconds
Started Apr 28 12:23:42 PM PDT 24
Finished Apr 28 12:23:49 PM PDT 24
Peak memory 201620 kb
Host smart-b32f2a4d-dc66-4ade-a97c-428ccd9a0927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089673109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.4089673109
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.1925123604
Short name T618
Test name
Test status
Simulation time 2508240413 ps
CPU time 6.94 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:22:58 PM PDT 24
Peak memory 201788 kb
Host smart-afa5aa63-99d8-4522-8a80-6e97a2644b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925123604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.1925123604
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.557242168
Short name T373
Test name
Test status
Simulation time 2193642406 ps
CPU time 1.05 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:50 PM PDT 24
Peak memory 201696 kb
Host smart-9082b83f-f5c0-4a21-b735-9f6e23d5d18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557242168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.557242168
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.2213276167
Short name T393
Test name
Test status
Simulation time 6621344069 ps
CPU time 17.38 seconds
Started Apr 28 12:23:24 PM PDT 24
Finished Apr 28 12:23:43 PM PDT 24
Peak memory 201716 kb
Host smart-bd07906d-881d-407c-aa17-516420aeade0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213276167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.2213276167
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1145693666
Short name T178
Test name
Test status
Simulation time 127263227904 ps
CPU time 26.44 seconds
Started Apr 28 12:22:35 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 210408 kb
Host smart-4fd0ca5f-5dcb-431c-87e0-4cfe4914c916
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145693666 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.1145693666
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.844886730
Short name T122
Test name
Test status
Simulation time 4798930262 ps
CPU time 7.04 seconds
Started Apr 28 12:23:52 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 198620 kb
Host smart-1627a255-5ef7-4e09-aa60-33f03566170e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844886730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_ultra_low_pwr.844886730
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.1854270972
Short name T503
Test name
Test status
Simulation time 2026401220 ps
CPU time 3.2 seconds
Started Apr 28 12:23:52 PM PDT 24
Finished Apr 28 12:23:58 PM PDT 24
Peak memory 198928 kb
Host smart-ff8982e3-41b4-4bf4-b0e1-6da0178ba4f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854270972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.1854270972
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2773965424
Short name T463
Test name
Test status
Simulation time 3537354073 ps
CPU time 10.43 seconds
Started Apr 28 12:23:25 PM PDT 24
Finished Apr 28 12:23:37 PM PDT 24
Peak memory 201612 kb
Host smart-50384f46-5db6-4af2-b348-0b80258cda31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773965424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.2
773965424
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.2168538113
Short name T234
Test name
Test status
Simulation time 66774648797 ps
CPU time 170.98 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:25:43 PM PDT 24
Peak memory 201996 kb
Host smart-4d2643f9-c34b-4013-8b6b-12774bdcba66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168538113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.2168538113
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1114544113
Short name T728
Test name
Test status
Simulation time 52596584569 ps
CPU time 128.74 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:24:50 PM PDT 24
Peak memory 201980 kb
Host smart-76b858f8-eb50-49d2-9b1d-7d723cee4297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114544113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.1114544113
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2150057798
Short name T579
Test name
Test status
Simulation time 3188645710 ps
CPU time 1.55 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:23:57 PM PDT 24
Peak memory 201360 kb
Host smart-3d37c877-a4be-496f-86ed-8784c43d8379
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150057798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.2150057798
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.3199230915
Short name T509
Test name
Test status
Simulation time 2516368894 ps
CPU time 1.52 seconds
Started Apr 28 12:23:25 PM PDT 24
Finished Apr 28 12:23:28 PM PDT 24
Peak memory 201760 kb
Host smart-b8ce5a85-531f-4f30-a8a8-6f5c9047b1b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199230915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.3199230915
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1747903629
Short name T386
Test name
Test status
Simulation time 2611282818 ps
CPU time 7.49 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:24:05 PM PDT 24
Peak memory 200912 kb
Host smart-3d95d794-7ffa-4aef-bc04-1cdcba5e3392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747903629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.1747903629
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.401793095
Short name T4
Test name
Test status
Simulation time 2454710501 ps
CPU time 3.67 seconds
Started Apr 28 12:22:58 PM PDT 24
Finished Apr 28 12:23:11 PM PDT 24
Peak memory 201692 kb
Host smart-b22ecff5-5837-44da-82c2-e3e79663eb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401793095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.401793095
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.3704144173
Short name T469
Test name
Test status
Simulation time 2156940378 ps
CPU time 6.42 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:55 PM PDT 24
Peak memory 201716 kb
Host smart-97b126c4-314f-41f3-b839-38e88a4b622e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704144173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.3704144173
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.1468170682
Short name T286
Test name
Test status
Simulation time 2569261442 ps
CPU time 1.42 seconds
Started Apr 28 12:23:22 PM PDT 24
Finished Apr 28 12:23:25 PM PDT 24
Peak memory 201836 kb
Host smart-4a573f5f-f379-418b-88ad-3429d50ac9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468170682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.1468170682
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.2328762289
Short name T778
Test name
Test status
Simulation time 2110675996 ps
CPU time 6.5 seconds
Started Apr 28 12:23:52 PM PDT 24
Finished Apr 28 12:24:01 PM PDT 24
Peak memory 199608 kb
Host smart-61205324-1541-40a5-825b-a7e7e4a5a6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328762289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.2328762289
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.648845669
Short name T421
Test name
Test status
Simulation time 9768297048 ps
CPU time 25.73 seconds
Started Apr 28 12:23:24 PM PDT 24
Finished Apr 28 12:23:51 PM PDT 24
Peak memory 201796 kb
Host smart-60e4f4a5-9f32-4a48-abe1-6bcdafdc5f34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648845669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_st
ress_all.648845669
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2582818396
Short name T12
Test name
Test status
Simulation time 51793102146 ps
CPU time 136.67 seconds
Started Apr 28 12:23:12 PM PDT 24
Finished Apr 28 12:25:31 PM PDT 24
Peak memory 210312 kb
Host smart-fc27b096-f94c-4517-9d1d-b5f79f61ca33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582818396 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.2582818396
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.3974178118
Short name T262
Test name
Test status
Simulation time 2939544756 ps
CPU time 3.19 seconds
Started Apr 28 12:23:25 PM PDT 24
Finished Apr 28 12:23:30 PM PDT 24
Peak memory 201604 kb
Host smart-501ca363-5930-4146-9f7f-a3a8bf21f3e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974178118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.3974178118
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.4075924374
Short name T398
Test name
Test status
Simulation time 2047367757 ps
CPU time 1.53 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 201720 kb
Host smart-6ff1eef5-0710-4883-b03d-acbe258bbd44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075924374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.4075924374
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1056164874
Short name T603
Test name
Test status
Simulation time 3780325105 ps
CPU time 10.45 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:12 PM PDT 24
Peak memory 201788 kb
Host smart-310ab762-ebcf-4c24-8bb4-1cc379f469e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056164874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.1
056164874
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.1568852895
Short name T619
Test name
Test status
Simulation time 143906043111 ps
CPU time 194.74 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:26:18 PM PDT 24
Peak memory 201788 kb
Host smart-2eb8f105-2962-4057-8228-2cb788202640
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568852895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.1568852895
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.794340888
Short name T700
Test name
Test status
Simulation time 4651788671 ps
CPU time 3.74 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:22:56 PM PDT 24
Peak memory 201612 kb
Host smart-b8c38a33-e801-4262-a3c1-531173f1959c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794340888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_ec_pwr_on_rst.794340888
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3295009572
Short name T512
Test name
Test status
Simulation time 2609878812 ps
CPU time 7.78 seconds
Started Apr 28 12:23:52 PM PDT 24
Finished Apr 28 12:24:02 PM PDT 24
Peak memory 199672 kb
Host smart-e9ccecdd-8102-4f97-a1bc-10d8de0b35c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295009572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.3295009572
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.1843458493
Short name T660
Test name
Test status
Simulation time 2452096973 ps
CPU time 8.13 seconds
Started Apr 28 12:23:19 PM PDT 24
Finished Apr 28 12:23:29 PM PDT 24
Peak memory 201736 kb
Host smart-78caf496-e468-4ece-8042-3655b0faf5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843458493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.1843458493
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.4027271815
Short name T694
Test name
Test status
Simulation time 2085540949 ps
CPU time 1.56 seconds
Started Apr 28 12:23:19 PM PDT 24
Finished Apr 28 12:23:22 PM PDT 24
Peak memory 201664 kb
Host smart-91c897e9-f8ff-49e3-b620-eaa6d368fb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027271815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.4027271815
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3258796344
Short name T149
Test name
Test status
Simulation time 2523645827 ps
CPU time 2.52 seconds
Started Apr 28 12:23:15 PM PDT 24
Finished Apr 28 12:23:19 PM PDT 24
Peak memory 201836 kb
Host smart-bd5c1ec7-84a1-4eff-b921-6241141de0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258796344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3258796344
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.3752676701
Short name T746
Test name
Test status
Simulation time 2125783893 ps
CPU time 1.92 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:24:00 PM PDT 24
Peak memory 201292 kb
Host smart-58e4dca0-bd4a-4824-9196-ff17dff44efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752676701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.3752676701
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.4095205070
Short name T797
Test name
Test status
Simulation time 9662565403 ps
CPU time 24.57 seconds
Started Apr 28 12:22:41 PM PDT 24
Finished Apr 28 12:23:11 PM PDT 24
Peak memory 201740 kb
Host smart-9024fec7-fa21-4853-9b92-a208cf636cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095205070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.4095205070
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.596052861
Short name T165
Test name
Test status
Simulation time 215929834098 ps
CPU time 31.94 seconds
Started Apr 28 12:22:43 PM PDT 24
Finished Apr 28 12:23:23 PM PDT 24
Peak memory 211536 kb
Host smart-e2199072-9b5d-4fe0-9c61-eb0f20872b93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596052861 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.596052861
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2433308378
Short name T444
Test name
Test status
Simulation time 4159300967 ps
CPU time 2.16 seconds
Started Apr 28 12:22:42 PM PDT 24
Finished Apr 28 12:22:50 PM PDT 24
Peak memory 201752 kb
Host smart-b7289b01-b949-487d-9d59-15ae0ca560dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433308378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.2433308378
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.1082892289
Short name T573
Test name
Test status
Simulation time 2028558200 ps
CPU time 2.4 seconds
Started Apr 28 12:22:12 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 201724 kb
Host smart-80a89d1f-5d6a-4083-b770-c8017eb415a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082892289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.1082892289
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3740903207
Short name T263
Test name
Test status
Simulation time 303526105574 ps
CPU time 413.3 seconds
Started Apr 28 12:19:50 PM PDT 24
Finished Apr 28 12:26:45 PM PDT 24
Peak memory 200560 kb
Host smart-0af633a4-8e41-4b99-9559-72bbc732bd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740903207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.3740903207
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.2750433818
Short name T326
Test name
Test status
Simulation time 118257269700 ps
CPU time 148.49 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:25:29 PM PDT 24
Peak memory 201848 kb
Host smart-b3bffd35-462f-4dde-8a61-9ead1fcd84ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750433818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.2750433818
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3297761864
Short name T411
Test name
Test status
Simulation time 2458437949 ps
CPU time 2.05 seconds
Started Apr 28 12:18:51 PM PDT 24
Finished Apr 28 12:18:54 PM PDT 24
Peak memory 201752 kb
Host smart-0f0f71f9-49e0-4aa6-83a0-23ca507df806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297761864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.3297761864
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1806732254
Short name T637
Test name
Test status
Simulation time 2314615717 ps
CPU time 3.76 seconds
Started Apr 28 12:19:45 PM PDT 24
Finished Apr 28 12:19:50 PM PDT 24
Peak memory 201704 kb
Host smart-51ba1a29-9fc6-4448-a355-d6fb6ff9c10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806732254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1806732254
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1310411789
Short name T70
Test name
Test status
Simulation time 29423944783 ps
CPU time 10.65 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:23:15 PM PDT 24
Peak memory 201956 kb
Host smart-2398a017-75d5-41fc-9c67-748f6d914df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310411789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.1310411789
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.3405904785
Short name T372
Test name
Test status
Simulation time 3666142731 ps
CPU time 4.64 seconds
Started Apr 28 12:19:50 PM PDT 24
Finished Apr 28 12:19:56 PM PDT 24
Peak memory 200276 kb
Host smart-0f36de1c-c1b2-4acd-ac5f-b0b9bde0d56f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405904785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.3405904785
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.2151302792
Short name T653
Test name
Test status
Simulation time 2758412258 ps
CPU time 4.04 seconds
Started Apr 28 12:19:55 PM PDT 24
Finished Apr 28 12:19:59 PM PDT 24
Peak memory 201748 kb
Host smart-d1e29aa5-a580-4a00-94b8-52bc49d1485d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151302792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.2151302792
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2761388770
Short name T415
Test name
Test status
Simulation time 2626874862 ps
CPU time 2.48 seconds
Started Apr 28 12:22:20 PM PDT 24
Finished Apr 28 12:22:24 PM PDT 24
Peak memory 201692 kb
Host smart-3d672cff-a38f-4c1e-b86d-fd121ba40311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761388770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.2761388770
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.2978682984
Short name T601
Test name
Test status
Simulation time 2457322836 ps
CPU time 3.8 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 201440 kb
Host smart-3f75910d-9797-4b72-8044-d02d6d4ea060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978682984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.2978682984
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.3159214861
Short name T390
Test name
Test status
Simulation time 2156847866 ps
CPU time 1.92 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:44 PM PDT 24
Peak memory 201776 kb
Host smart-156b4acb-61bd-4f22-b2d8-742a32d80aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159214861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.3159214861
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.3994080921
Short name T363
Test name
Test status
Simulation time 2517746858 ps
CPU time 3.81 seconds
Started Apr 28 12:22:01 PM PDT 24
Finished Apr 28 12:22:07 PM PDT 24
Peak memory 201056 kb
Host smart-4b220195-fecf-4150-b96c-fb81782e905e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994080921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.3994080921
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.552878202
Short name T261
Test name
Test status
Simulation time 42011740502 ps
CPU time 101.3 seconds
Started Apr 28 12:21:53 PM PDT 24
Finished Apr 28 12:23:40 PM PDT 24
Peak memory 220112 kb
Host smart-abb8311d-e0c7-46c3-939e-71166e00670d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552878202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.552878202
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.2934625987
Short name T419
Test name
Test status
Simulation time 2117731816 ps
CPU time 3.4 seconds
Started Apr 28 12:22:39 PM PDT 24
Finished Apr 28 12:22:48 PM PDT 24
Peak memory 201320 kb
Host smart-e5157d08-248d-4a01-9c6b-0992aaa45595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934625987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.2934625987
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.2046534678
Short name T457
Test name
Test status
Simulation time 10046645503 ps
CPU time 10.27 seconds
Started Apr 28 12:21:55 PM PDT 24
Finished Apr 28 12:22:10 PM PDT 24
Peak memory 201516 kb
Host smart-675f3b67-3aa5-4cb0-a92b-e7f456000f0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046534678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.2046534678
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2126875776
Short name T769
Test name
Test status
Simulation time 10356884837 ps
CPU time 2.78 seconds
Started Apr 28 12:22:01 PM PDT 24
Finished Apr 28 12:22:06 PM PDT 24
Peak memory 201292 kb
Host smart-4bcec101-0628-4c26-adda-a736aa73ed9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126875776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.2126875776
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.1686851319
Short name T109
Test name
Test status
Simulation time 2039433766 ps
CPU time 1.84 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 201492 kb
Host smart-23322a73-ea84-4679-abb5-8f287874ed8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686851319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.1686851319
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.4056064525
Short name T742
Test name
Test status
Simulation time 287202327805 ps
CPU time 103.88 seconds
Started Apr 28 12:22:45 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 201824 kb
Host smart-94856c8d-9953-4a87-b191-5c325ffd558a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056064525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.4
056064525
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.3755906295
Short name T435
Test name
Test status
Simulation time 29136279233 ps
CPU time 36.25 seconds
Started Apr 28 12:23:00 PM PDT 24
Finished Apr 28 12:23:45 PM PDT 24
Peak memory 201876 kb
Host smart-b7b399d1-1c21-4bb8-9c31-b118f38df997
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755906295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.3755906295
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1157648982
Short name T235
Test name
Test status
Simulation time 75929006916 ps
CPU time 24.65 seconds
Started Apr 28 12:22:45 PM PDT 24
Finished Apr 28 12:23:17 PM PDT 24
Peak memory 202012 kb
Host smart-f5842384-f90a-4b96-a80b-4690a8eca5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157648982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.1157648982
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.492986588
Short name T526
Test name
Test status
Simulation time 3482363564 ps
CPU time 1.57 seconds
Started Apr 28 12:22:55 PM PDT 24
Finished Apr 28 12:23:07 PM PDT 24
Peak memory 200776 kb
Host smart-d840004c-6a87-44a6-a411-c2670c353cb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492986588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_ec_pwr_on_rst.492986588
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.2312000798
Short name T191
Test name
Test status
Simulation time 4703582236 ps
CPU time 9.81 seconds
Started Apr 28 12:22:45 PM PDT 24
Finished Apr 28 12:23:04 PM PDT 24
Peak memory 201772 kb
Host smart-a597bbfc-5fcd-46e9-a802-74b9cfca0151
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312000798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.2312000798
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.4064297557
Short name T609
Test name
Test status
Simulation time 2616572398 ps
CPU time 3.93 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 201724 kb
Host smart-3ccc029c-6752-4185-9686-05abc3925fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064297557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.4064297557
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.4220742961
Short name T527
Test name
Test status
Simulation time 2473245801 ps
CPU time 2.15 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:22:54 PM PDT 24
Peak memory 201788 kb
Host smart-7ab85286-e3fe-4bd8-ae34-06f37d2f37e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220742961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.4220742961
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.1238159110
Short name T484
Test name
Test status
Simulation time 2052872825 ps
CPU time 5.57 seconds
Started Apr 28 12:22:44 PM PDT 24
Finished Apr 28 12:22:58 PM PDT 24
Peak memory 201700 kb
Host smart-90a26f22-3ccb-4b5b-a160-ffd7f1010d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238159110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.1238159110
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3664713619
Short name T767
Test name
Test status
Simulation time 2525650771 ps
CPU time 2.23 seconds
Started Apr 28 12:23:04 PM PDT 24
Finished Apr 28 12:23:13 PM PDT 24
Peak memory 201772 kb
Host smart-7616826b-a2b3-4af9-85fe-564f170ca966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664713619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.3664713619
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.2898510878
Short name T497
Test name
Test status
Simulation time 2113932352 ps
CPU time 4.28 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:23:01 PM PDT 24
Peak memory 201568 kb
Host smart-f84327a5-94ff-46f4-9165-4707ba384ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898510878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.2898510878
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.3413420540
Short name T726
Test name
Test status
Simulation time 6721403483 ps
CPU time 17.36 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:15 PM PDT 24
Peak memory 201636 kb
Host smart-469f42ca-efac-4d7b-92c7-3c247f2cf4e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413420540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.3413420540
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.4118337753
Short name T548
Test name
Test status
Simulation time 5855594027 ps
CPU time 7.82 seconds
Started Apr 28 12:22:55 PM PDT 24
Finished Apr 28 12:23:13 PM PDT 24
Peak memory 201040 kb
Host smart-d071ad71-3027-4071-b2d9-b43b892d3d2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118337753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.4118337753
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.809041406
Short name T747
Test name
Test status
Simulation time 2041486183 ps
CPU time 1.25 seconds
Started Apr 28 12:22:55 PM PDT 24
Finished Apr 28 12:23:07 PM PDT 24
Peak memory 201704 kb
Host smart-7c1ad7d5-22ee-45d1-819d-67969e0e72e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809041406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_tes
t.809041406
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.943958101
Short name T422
Test name
Test status
Simulation time 3388380784 ps
CPU time 9.81 seconds
Started Apr 28 12:22:43 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 201824 kb
Host smart-a116870d-210f-42ac-a99d-ddceca2329a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943958101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.943958101
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.865881890
Short name T183
Test name
Test status
Simulation time 24100586217 ps
CPU time 17.53 seconds
Started Apr 28 12:22:46 PM PDT 24
Finished Apr 28 12:23:12 PM PDT 24
Peak memory 202004 kb
Host smart-2ad2c38c-3b1d-41ba-977f-11bd99ee9312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865881890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_wi
th_pre_cond.865881890
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3553559271
Short name T651
Test name
Test status
Simulation time 3838374729 ps
CPU time 5.25 seconds
Started Apr 28 12:23:00 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 201680 kb
Host smart-3d441b9d-e95c-440a-bea9-556d8e949089
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553559271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.3553559271
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.4189996962
Short name T543
Test name
Test status
Simulation time 3107706738 ps
CPU time 2.24 seconds
Started Apr 28 12:22:41 PM PDT 24
Finished Apr 28 12:22:48 PM PDT 24
Peak memory 201756 kb
Host smart-91ce25e9-1414-4dc7-a9c8-61d343e229bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189996962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.4189996962
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3469812591
Short name T62
Test name
Test status
Simulation time 2626534226 ps
CPU time 2.32 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 201652 kb
Host smart-7efb5188-94b2-4d3d-97bf-7c687390de83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469812591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.3469812591
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.73246543
Short name T450
Test name
Test status
Simulation time 2468401760 ps
CPU time 2.29 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 201620 kb
Host smart-2f3212fd-f43f-48bb-82c4-56fb428445f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73246543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.73246543
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2919116885
Short name T102
Test name
Test status
Simulation time 2265750902 ps
CPU time 3.64 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 201632 kb
Host smart-ec11280a-9cad-43e7-ac70-7d768d0ecc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919116885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.2919116885
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.2970081394
Short name T451
Test name
Test status
Simulation time 2510150283 ps
CPU time 6.79 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:08 PM PDT 24
Peak memory 201800 kb
Host smart-a69aadb4-ed8c-4897-b399-976a7b3dc1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970081394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.2970081394
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.3249116842
Short name T718
Test name
Test status
Simulation time 2115247542 ps
CPU time 4.54 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 201572 kb
Host smart-c4130ddd-1a97-4126-a463-4d11709b9b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249116842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.3249116842
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.1081752021
Short name T41
Test name
Test status
Simulation time 13175602677 ps
CPU time 9.09 seconds
Started Apr 28 12:22:55 PM PDT 24
Finished Apr 28 12:23:15 PM PDT 24
Peak memory 201880 kb
Host smart-1da2ddfa-39b6-42e2-96de-f0413005c9a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081752021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.1081752021
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.458515334
Short name T599
Test name
Test status
Simulation time 7978497387 ps
CPU time 3.9 seconds
Started Apr 28 12:22:54 PM PDT 24
Finished Apr 28 12:23:12 PM PDT 24
Peak memory 201736 kb
Host smart-a36a88bb-d6a5-4675-adce-762ee7a0f341
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458515334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_ultra_low_pwr.458515334
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.4156531895
Short name T126
Test name
Test status
Simulation time 2036247028 ps
CPU time 1.82 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 201692 kb
Host smart-cfc43bdb-022b-4322-a266-e7d3aa097db7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156531895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.4156531895
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.1600494681
Short name T49
Test name
Test status
Simulation time 3789144115 ps
CPU time 5.83 seconds
Started Apr 28 12:22:56 PM PDT 24
Finished Apr 28 12:23:12 PM PDT 24
Peak memory 201696 kb
Host smart-0e0b042b-fd3f-4442-82cf-85745a217750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600494681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.1
600494681
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.313228338
Short name T205
Test name
Test status
Simulation time 151661996428 ps
CPU time 94.42 seconds
Started Apr 28 12:22:45 PM PDT 24
Finished Apr 28 12:24:29 PM PDT 24
Peak memory 201908 kb
Host smart-d88c35af-eb32-4805-98fa-6047678f5333
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313228338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_combo_detect.313228338
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2558191409
Short name T564
Test name
Test status
Simulation time 23582404219 ps
CPU time 57.75 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:24:01 PM PDT 24
Peak memory 201896 kb
Host smart-97e3135f-3c0f-45de-be04-20ef8b04792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558191409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.2558191409
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.965663491
Short name T594
Test name
Test status
Simulation time 3219287336 ps
CPU time 4.88 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:08 PM PDT 24
Peak memory 200956 kb
Host smart-b45ebb1a-5152-47cc-9091-cc7ced53248d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965663491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_ec_pwr_on_rst.965663491
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.551725560
Short name T780
Test name
Test status
Simulation time 59615325085 ps
CPU time 21.36 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:23:25 PM PDT 24
Peak memory 201716 kb
Host smart-758eae22-855c-47d9-8880-51071717ca4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551725560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctr
l_edge_detect.551725560
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3778586712
Short name T596
Test name
Test status
Simulation time 2611817605 ps
CPU time 7.23 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 201464 kb
Host smart-c7eb1e78-a699-41f4-a21a-a7a36fea49ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778586712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3778586712
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.2296185651
Short name T502
Test name
Test status
Simulation time 2505781994 ps
CPU time 1.58 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 201636 kb
Host smart-ca64cead-c0b8-4c2e-bac1-f6600f79d29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296185651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.2296185651
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.3039572105
Short name T506
Test name
Test status
Simulation time 2200753928 ps
CPU time 2.33 seconds
Started Apr 28 12:22:45 PM PDT 24
Finished Apr 28 12:22:56 PM PDT 24
Peak memory 201756 kb
Host smart-79252dde-f0b4-4bc5-b43e-2f5fdab7ec35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039572105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.3039572105
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.4223134176
Short name T111
Test name
Test status
Simulation time 2521960213 ps
CPU time 3.29 seconds
Started Apr 28 12:23:00 PM PDT 24
Finished Apr 28 12:23:12 PM PDT 24
Peak memory 201788 kb
Host smart-fc481ad6-2fcb-4051-ac77-3cfd3585788d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223134176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.4223134176
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.21240242
Short name T168
Test name
Test status
Simulation time 2110281989 ps
CPU time 5.79 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:23:03 PM PDT 24
Peak memory 201588 kb
Host smart-fc56ee4a-3b1b-4860-bd8a-c51451ce99a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21240242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.21240242
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.961430662
Short name T63
Test name
Test status
Simulation time 11300166299 ps
CPU time 32.85 seconds
Started Apr 28 12:22:56 PM PDT 24
Finished Apr 28 12:23:39 PM PDT 24
Peak memory 201644 kb
Host smart-b892572c-b7c1-4c01-865f-c63c4a12994e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961430662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_st
ress_all.961430662
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1663395513
Short name T16
Test name
Test status
Simulation time 26110942292 ps
CPU time 69.81 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:25:14 PM PDT 24
Peak memory 207776 kb
Host smart-6a9ba277-0f68-4d68-bf5d-9db2341a1e52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663395513 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.1663395513
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.3725072896
Short name T72
Test name
Test status
Simulation time 7001088090 ps
CPU time 6 seconds
Started Apr 28 12:22:55 PM PDT 24
Finished Apr 28 12:23:12 PM PDT 24
Peak memory 201640 kb
Host smart-304b4290-87ac-4903-b814-58309ec09c7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725072896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.3725072896
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.1022740632
Short name T644
Test name
Test status
Simulation time 2094821339 ps
CPU time 0.97 seconds
Started Apr 28 12:22:56 PM PDT 24
Finished Apr 28 12:23:07 PM PDT 24
Peak memory 201760 kb
Host smart-7da3ad7b-82c3-4752-91c5-b4890f7616cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022740632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.1022740632
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.1361660944
Short name T730
Test name
Test status
Simulation time 3780198689 ps
CPU time 11.29 seconds
Started Apr 28 12:22:55 PM PDT 24
Finished Apr 28 12:23:17 PM PDT 24
Peak memory 201700 kb
Host smart-56f06315-37fc-4c82-a311-b4f59bebbca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361660944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.1
361660944
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3689107621
Short name T337
Test name
Test status
Simulation time 86071311142 ps
CPU time 124.63 seconds
Started Apr 28 12:22:56 PM PDT 24
Finished Apr 28 12:25:11 PM PDT 24
Peak memory 201824 kb
Host smart-b24ecb8f-6163-4b34-ad3e-69d6c993ba0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689107621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.3689107621
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.4221335033
Short name T439
Test name
Test status
Simulation time 3761535838 ps
CPU time 7.76 seconds
Started Apr 28 12:23:05 PM PDT 24
Finished Apr 28 12:23:19 PM PDT 24
Peak memory 201708 kb
Host smart-b72d28bc-5cd0-4d81-91d2-3344a9d668d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221335033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.4221335033
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.1008856076
Short name T448
Test name
Test status
Simulation time 3266087509 ps
CPU time 2.86 seconds
Started Apr 28 12:22:45 PM PDT 24
Finished Apr 28 12:22:57 PM PDT 24
Peak memory 201664 kb
Host smart-1796218e-db1e-4d10-a220-e4af84467562
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008856076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.1008856076
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1690038694
Short name T392
Test name
Test status
Simulation time 2720226706 ps
CPU time 1.19 seconds
Started Apr 28 12:22:45 PM PDT 24
Finished Apr 28 12:22:55 PM PDT 24
Peak memory 201660 kb
Host smart-2da92c1e-ea74-417c-b1ca-6f63c1282035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690038694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.1690038694
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.2335743845
Short name T732
Test name
Test status
Simulation time 2457562520 ps
CPU time 6.89 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:07 PM PDT 24
Peak memory 201692 kb
Host smart-05afabeb-e088-41e3-876f-070a079a74b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335743845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.2335743845
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3737202957
Short name T15
Test name
Test status
Simulation time 2028170623 ps
CPU time 3.48 seconds
Started Apr 28 12:22:46 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 201716 kb
Host smart-aa966e7c-f96f-4ec5-9852-82d7aebd398e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737202957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.3737202957
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.1778075925
Short name T141
Test name
Test status
Simulation time 2666413986 ps
CPU time 1.02 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 201716 kb
Host smart-25c078f4-9a7e-4f5b-8222-02c7484b2ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778075925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.1778075925
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.2502613179
Short name T510
Test name
Test status
Simulation time 2111952231 ps
CPU time 6.03 seconds
Started Apr 28 12:22:57 PM PDT 24
Finished Apr 28 12:23:13 PM PDT 24
Peak memory 201632 kb
Host smart-ce65eac1-a92d-4156-b89a-ffb042275ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502613179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.2502613179
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.2831344811
Short name T88
Test name
Test status
Simulation time 10900257144 ps
CPU time 8.59 seconds
Started Apr 28 12:23:07 PM PDT 24
Finished Apr 28 12:23:20 PM PDT 24
Peak memory 201712 kb
Host smart-ae23f023-c737-4446-8f6e-a3c98fba83d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831344811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.2831344811
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.626052559
Short name T92
Test name
Test status
Simulation time 520392947190 ps
CPU time 67.63 seconds
Started Apr 28 12:22:51 PM PDT 24
Finished Apr 28 12:24:10 PM PDT 24
Peak memory 210392 kb
Host smart-41be3f1c-ba9e-4b9a-b721-33ce29f3e854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626052559 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.626052559
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2202778923
Short name T58
Test name
Test status
Simulation time 2838899676 ps
CPU time 5.75 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:24:10 PM PDT 24
Peak memory 201120 kb
Host smart-9bb8913d-0f2a-45e5-8f5c-15f1aaf5813f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202778923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ultra_low_pwr.2202778923
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.989358720
Short name T617
Test name
Test status
Simulation time 2042540448 ps
CPU time 1.92 seconds
Started Apr 28 12:23:09 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 201752 kb
Host smart-b438c4df-fcff-4bcd-a8e0-add2ff78336d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989358720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_tes
t.989358720
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1839649022
Short name T692
Test name
Test status
Simulation time 3396541981 ps
CPU time 9.63 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:11 PM PDT 24
Peak memory 201792 kb
Host smart-d645129a-bd07-40ce-8574-1df8056c5596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839649022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.1
839649022
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.2750631828
Short name T29
Test name
Test status
Simulation time 105862801396 ps
CPU time 93.94 seconds
Started Apr 28 12:23:02 PM PDT 24
Finished Apr 28 12:24:43 PM PDT 24
Peak memory 201892 kb
Host smart-e43c9102-3951-412e-9dd4-6079dcd526fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750631828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.2750631828
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2681425989
Short name T688
Test name
Test status
Simulation time 4031632465 ps
CPU time 2.31 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 201456 kb
Host smart-a7430259-36d1-4dba-95e5-c6cd800355a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681425989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.2681425989
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1820130421
Short name T212
Test name
Test status
Simulation time 2465635075 ps
CPU time 5.98 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:23:10 PM PDT 24
Peak memory 201716 kb
Host smart-736b4750-12ba-404d-ad0c-a37589c1ba4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820130421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.1820130421
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.846802090
Short name T401
Test name
Test status
Simulation time 2625010283 ps
CPU time 2.32 seconds
Started Apr 28 12:23:09 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 201748 kb
Host smart-ab65c39c-af52-4938-99b7-51c1aedfc161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846802090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.846802090
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.3731478594
Short name T580
Test name
Test status
Simulation time 2483163273 ps
CPU time 2.27 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 201708 kb
Host smart-791e63f7-b6e6-405d-aa67-935cb807dfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731478594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.3731478594
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.669071475
Short name T74
Test name
Test status
Simulation time 2275032424 ps
CPU time 2.11 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 201684 kb
Host smart-77d97971-d185-4b71-a8c1-8cc2625820b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669071475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.669071475
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.3703786174
Short name T130
Test name
Test status
Simulation time 2511903886 ps
CPU time 6.89 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:24:11 PM PDT 24
Peak memory 200104 kb
Host smart-9760b3dd-b7c2-4ea7-b6c3-e013b4ee4def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703786174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.3703786174
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.2715575069
Short name T138
Test name
Test status
Simulation time 2112834317 ps
CPU time 3.13 seconds
Started Apr 28 12:22:56 PM PDT 24
Finished Apr 28 12:23:09 PM PDT 24
Peak memory 201552 kb
Host smart-752db196-b978-4236-98f1-fc61302f7d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715575069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.2715575069
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.2334608768
Short name T649
Test name
Test status
Simulation time 15548453685 ps
CPU time 33.85 seconds
Started Apr 28 12:23:00 PM PDT 24
Finished Apr 28 12:23:42 PM PDT 24
Peak memory 201772 kb
Host smart-182a74c0-1ab2-4c09-970e-842b620f4545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334608768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.2334608768
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1599215672
Short name T154
Test name
Test status
Simulation time 44032251821 ps
CPU time 6.13 seconds
Started Apr 28 12:22:45 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 211012 kb
Host smart-029b84e4-728a-409a-8e90-b5d51db4f19c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599215672 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.1599215672
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.3950631646
Short name T567
Test name
Test status
Simulation time 2012412343 ps
CPU time 5.55 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:24:10 PM PDT 24
Peak memory 199548 kb
Host smart-9dc63c85-f9c8-4bf7-bf45-f63256b96527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950631646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.3950631646
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2139345306
Short name T739
Test name
Test status
Simulation time 3687272097 ps
CPU time 4.98 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:24:09 PM PDT 24
Peak memory 199152 kb
Host smart-149028b7-6838-48ea-81dc-d461eabd4fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139345306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.2
139345306
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.431251586
Short name T782
Test name
Test status
Simulation time 108193645907 ps
CPU time 266.52 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:27:28 PM PDT 24
Peak memory 201808 kb
Host smart-900bc3fb-4fe9-47b0-a981-2b824e95dba3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431251586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_combo_detect.431251586
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1191189898
Short name T75
Test name
Test status
Simulation time 69537430381 ps
CPU time 42.63 seconds
Started Apr 28 12:23:08 PM PDT 24
Finished Apr 28 12:23:55 PM PDT 24
Peak memory 201880 kb
Host smart-606994e5-c909-4466-9662-a2d7174373e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191189898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.1191189898
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.4292671256
Short name T551
Test name
Test status
Simulation time 5363567044 ps
CPU time 14.48 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 201680 kb
Host smart-e904f0ba-bfef-4c88-99e5-669eb9710f17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292671256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.4292671256
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.3183252738
Short name T153
Test name
Test status
Simulation time 3097677264 ps
CPU time 2.3 seconds
Started Apr 28 12:23:01 PM PDT 24
Finished Apr 28 12:23:11 PM PDT 24
Peak memory 201720 kb
Host smart-e21432d6-c7a6-48dc-8ca5-847d2023c162
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183252738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.3183252738
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.657001494
Short name T470
Test name
Test status
Simulation time 2614430157 ps
CPU time 5.42 seconds
Started Apr 28 12:22:52 PM PDT 24
Finished Apr 28 12:23:09 PM PDT 24
Peak memory 201488 kb
Host smart-94c21484-4b35-4749-83dd-0e5992c25d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657001494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.657001494
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.2007995600
Short name T585
Test name
Test status
Simulation time 2454559551 ps
CPU time 4.29 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:24:08 PM PDT 24
Peak memory 199152 kb
Host smart-53bec714-9986-4ebf-9e26-31fd291b140a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007995600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.2007995600
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.1940498730
Short name T794
Test name
Test status
Simulation time 2217838021 ps
CPU time 6.61 seconds
Started Apr 28 12:22:45 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 201768 kb
Host smart-24b02583-6832-4364-b2b7-ca070b379c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940498730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.1940498730
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.3945954225
Short name T656
Test name
Test status
Simulation time 2518817839 ps
CPU time 3.81 seconds
Started Apr 28 12:23:59 PM PDT 24
Finished Apr 28 12:24:08 PM PDT 24
Peak memory 201372 kb
Host smart-53459762-ff09-4749-9a8f-641a89834ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945954225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.3945954225
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.931458421
Short name T387
Test name
Test status
Simulation time 2111774991 ps
CPU time 6.32 seconds
Started Apr 28 12:22:55 PM PDT 24
Finished Apr 28 12:23:12 PM PDT 24
Peak memory 201552 kb
Host smart-23844e40-56eb-4129-89ac-83975a42768a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931458421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.931458421
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.3428542749
Short name T180
Test name
Test status
Simulation time 276225821031 ps
CPU time 78.13 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:24:19 PM PDT 24
Peak memory 201876 kb
Host smart-74286647-eebe-4c51-a015-2c5fae77d21b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428542749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.3428542749
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2347766829
Short name T743
Test name
Test status
Simulation time 20276125794 ps
CPU time 55.31 seconds
Started Apr 28 12:24:08 PM PDT 24
Finished Apr 28 12:25:05 PM PDT 24
Peak memory 210024 kb
Host smart-e49638bd-3c24-4478-a65c-7c71d695fb80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347766829 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.2347766829
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.1780769424
Short name T56
Test name
Test status
Simulation time 7861044588 ps
CPU time 2.59 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:24:07 PM PDT 24
Peak memory 199608 kb
Host smart-8ad04041-5372-4d8c-a3d2-688f1a5eb42a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780769424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.1780769424
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.3732057732
Short name T252
Test name
Test status
Simulation time 2022349664 ps
CPU time 3.01 seconds
Started Apr 28 12:23:04 PM PDT 24
Finished Apr 28 12:23:13 PM PDT 24
Peak memory 201748 kb
Host smart-97eb0aab-22c1-4ad7-b6ee-5107047f73d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732057732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.3732057732
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3791395682
Short name T43
Test name
Test status
Simulation time 3480424306 ps
CPU time 9.54 seconds
Started Apr 28 12:23:21 PM PDT 24
Finished Apr 28 12:23:31 PM PDT 24
Peak memory 201768 kb
Host smart-d2981282-3779-49fe-965f-9e4c041f0c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791395682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3
791395682
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.1260456206
Short name T355
Test name
Test status
Simulation time 106255285947 ps
CPU time 277.44 seconds
Started Apr 28 12:24:00 PM PDT 24
Finished Apr 28 12:28:43 PM PDT 24
Peak memory 200416 kb
Host smart-da7811b7-40ad-4a4e-b1d7-79637d5ed549
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260456206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_combo_detect.1260456206
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2157223448
Short name T514
Test name
Test status
Simulation time 25584329686 ps
CPU time 31.12 seconds
Started Apr 28 12:22:58 PM PDT 24
Finished Apr 28 12:23:39 PM PDT 24
Peak memory 201956 kb
Host smart-5f4153af-3fd6-44b6-aab6-1ac7fcdd5483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157223448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.2157223448
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.792212922
Short name T581
Test name
Test status
Simulation time 3595550653 ps
CPU time 4.38 seconds
Started Apr 28 12:24:00 PM PDT 24
Finished Apr 28 12:24:10 PM PDT 24
Peak memory 200108 kb
Host smart-742c537d-724a-4dc4-b119-cf65c7983804
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792212922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_ec_pwr_on_rst.792212922
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.3427474502
Short name T670
Test name
Test status
Simulation time 3020257854 ps
CPU time 1.97 seconds
Started Apr 28 12:22:54 PM PDT 24
Finished Apr 28 12:23:06 PM PDT 24
Peak memory 201772 kb
Host smart-80c19fe4-8f5d-43e5-b87f-b24c3822931e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427474502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.3427474502
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2851954935
Short name T678
Test name
Test status
Simulation time 2637173757 ps
CPU time 2.28 seconds
Started Apr 28 12:23:13 PM PDT 24
Finished Apr 28 12:23:17 PM PDT 24
Peak memory 201676 kb
Host smart-d3131fec-f64e-4438-8fdd-31879e0aa1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851954935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.2851954935
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.1379269131
Short name T734
Test name
Test status
Simulation time 2456452126 ps
CPU time 4.53 seconds
Started Apr 28 12:23:13 PM PDT 24
Finished Apr 28 12:23:20 PM PDT 24
Peak memory 201700 kb
Host smart-e6db0ba8-e8ca-4a13-8873-1f8488856e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379269131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.1379269131
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2790296443
Short name T182
Test name
Test status
Simulation time 2105525605 ps
CPU time 1.78 seconds
Started Apr 28 12:22:56 PM PDT 24
Finished Apr 28 12:23:08 PM PDT 24
Peak memory 201636 kb
Host smart-b18f5600-9f3c-4942-b715-d7ddae9ba09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790296443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.2790296443
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.1889362847
Short name T505
Test name
Test status
Simulation time 2510526225 ps
CPU time 7.32 seconds
Started Apr 28 12:23:26 PM PDT 24
Finished Apr 28 12:23:34 PM PDT 24
Peak memory 201820 kb
Host smart-b25d7657-0aca-4892-96f6-b882420e1013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889362847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.1889362847
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.2669483953
Short name T288
Test name
Test status
Simulation time 2126417622 ps
CPU time 2.02 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:01 PM PDT 24
Peak memory 201664 kb
Host smart-3b98cf6e-991c-4e2c-97b0-bb5913408554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669483953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.2669483953
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.317860125
Short name T271
Test name
Test status
Simulation time 6127389261 ps
CPU time 4.2 seconds
Started Apr 28 12:23:24 PM PDT 24
Finished Apr 28 12:23:29 PM PDT 24
Peak memory 201704 kb
Host smart-18c2995d-270a-43e2-be50-c89c5904e8cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317860125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_st
ress_all.317860125
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1747915870
Short name T268
Test name
Test status
Simulation time 60485551107 ps
CPU time 168.37 seconds
Started Apr 28 12:23:06 PM PDT 24
Finished Apr 28 12:25:59 PM PDT 24
Peak memory 210376 kb
Host smart-ebcaa4f1-ba93-4990-a22d-cec41d5f3471
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747915870 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.1747915870
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3514383082
Short name T55
Test name
Test status
Simulation time 3707094585 ps
CPU time 1.62 seconds
Started Apr 28 12:24:22 PM PDT 24
Finished Apr 28 12:24:30 PM PDT 24
Peak memory 201660 kb
Host smart-ec97910f-de36-4512-85c5-6c946224d6e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514383082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.3514383082
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.1161994445
Short name T458
Test name
Test status
Simulation time 2020226219 ps
CPU time 3.13 seconds
Started Apr 28 12:23:07 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 201784 kb
Host smart-f0c93e16-e49b-4021-b664-92a352de7083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161994445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.1161994445
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.771512005
Short name T164
Test name
Test status
Simulation time 537037403346 ps
CPU time 115.69 seconds
Started Apr 28 12:24:25 PM PDT 24
Finished Apr 28 12:26:22 PM PDT 24
Peak memory 201724 kb
Host smart-76bfac85-d9c1-41f6-b75a-e07fa345d55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771512005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.771512005
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.4163617564
Short name T204
Test name
Test status
Simulation time 87560459327 ps
CPU time 25.1 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:23:22 PM PDT 24
Peak memory 201988 kb
Host smart-deb99a82-8430-4858-9302-d3ea2acd61d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163617564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.4163617564
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.113789976
Short name T97
Test name
Test status
Simulation time 26092162819 ps
CPU time 37.39 seconds
Started Apr 28 12:24:29 PM PDT 24
Finished Apr 28 12:25:10 PM PDT 24
Peak memory 201920 kb
Host smart-96f5cde1-4f54-427b-a1d2-5af45dc56ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113789976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_wi
th_pre_cond.113789976
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3563770776
Short name T709
Test name
Test status
Simulation time 4004200506 ps
CPU time 6.93 seconds
Started Apr 28 12:23:22 PM PDT 24
Finished Apr 28 12:23:30 PM PDT 24
Peak memory 201700 kb
Host smart-83b31f56-5eeb-4f45-955e-38c2e0dbc254
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563770776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.3563770776
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.2528401807
Short name T504
Test name
Test status
Simulation time 2557025948 ps
CPU time 7.92 seconds
Started Apr 28 12:22:55 PM PDT 24
Finished Apr 28 12:23:13 PM PDT 24
Peak memory 201776 kb
Host smart-476ed13e-3fd0-4353-a291-43f5a8237d46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528401807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.2528401807
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3739541996
Short name T384
Test name
Test status
Simulation time 2612202488 ps
CPU time 7.02 seconds
Started Apr 28 12:23:59 PM PDT 24
Finished Apr 28 12:24:12 PM PDT 24
Peak memory 201348 kb
Host smart-f180cdd4-4ce0-4dea-8eab-53cab6de5454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739541996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.3739541996
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2865750058
Short name T790
Test name
Test status
Simulation time 2452668449 ps
CPU time 4.61 seconds
Started Apr 28 12:23:58 PM PDT 24
Finished Apr 28 12:24:09 PM PDT 24
Peak memory 199692 kb
Host smart-9344f805-8e9e-4ee5-ae5f-8784e9a8d4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865750058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.2865750058
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.3014960040
Short name T482
Test name
Test status
Simulation time 2241754051 ps
CPU time 6.56 seconds
Started Apr 28 12:23:59 PM PDT 24
Finished Apr 28 12:24:11 PM PDT 24
Peak memory 201304 kb
Host smart-3f62c78b-48d2-43b5-b4fc-ca5d13de4944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014960040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.3014960040
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.10750003
Short name T461
Test name
Test status
Simulation time 2511898479 ps
CPU time 7.65 seconds
Started Apr 28 12:22:50 PM PDT 24
Finished Apr 28 12:23:09 PM PDT 24
Peak memory 201884 kb
Host smart-de8789bd-86a2-4679-ab00-5a8814c8bd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10750003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.10750003
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.1550798094
Short name T157
Test name
Test status
Simulation time 2111768166 ps
CPU time 6.45 seconds
Started Apr 28 12:23:26 PM PDT 24
Finished Apr 28 12:23:34 PM PDT 24
Peak memory 201628 kb
Host smart-ddf16b74-67a6-48b5-9d55-976939e7691b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550798094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.1550798094
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.2092295851
Short name T177
Test name
Test status
Simulation time 15222768692 ps
CPU time 38.25 seconds
Started Apr 28 12:23:00 PM PDT 24
Finished Apr 28 12:23:47 PM PDT 24
Peak memory 201712 kb
Host smart-7a03eaa9-90e3-4ad9-aa7f-7201ab9fe90d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092295851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.2092295851
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.3164895609
Short name T540
Test name
Test status
Simulation time 6482063381 ps
CPU time 2.06 seconds
Started Apr 28 12:23:09 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 201752 kb
Host smart-deae6448-0e31-4309-b52e-507056c04f2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164895609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.3164895609
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.254513217
Short name T724
Test name
Test status
Simulation time 2014837035 ps
CPU time 4.46 seconds
Started Apr 28 12:23:14 PM PDT 24
Finished Apr 28 12:23:20 PM PDT 24
Peak memory 201752 kb
Host smart-68c74eca-e02a-4e28-bf0a-548f7c9de5ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254513217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_tes
t.254513217
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.518493238
Short name T394
Test name
Test status
Simulation time 3395831849 ps
CPU time 9.79 seconds
Started Apr 28 12:24:18 PM PDT 24
Finished Apr 28 12:24:29 PM PDT 24
Peak memory 201712 kb
Host smart-1cab6f83-49f7-4404-ac13-812c52d19ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518493238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.518493238
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.2346535972
Short name T223
Test name
Test status
Simulation time 86546167265 ps
CPU time 22.03 seconds
Started Apr 28 12:23:05 PM PDT 24
Finished Apr 28 12:23:33 PM PDT 24
Peak memory 201572 kb
Host smart-01e02317-871d-4d66-8cba-d598bf08700a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346535972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.2346535972
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1456755658
Short name T643
Test name
Test status
Simulation time 46298935859 ps
CPU time 116.54 seconds
Started Apr 28 12:24:25 PM PDT 24
Finished Apr 28 12:26:23 PM PDT 24
Peak memory 201896 kb
Host smart-683a9005-cdc5-4ca4-9cec-afc2f969c861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456755658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.1456755658
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.3171817441
Short name T199
Test name
Test status
Simulation time 4783142638 ps
CPU time 11.33 seconds
Started Apr 28 12:23:18 PM PDT 24
Finished Apr 28 12:23:30 PM PDT 24
Peak memory 201764 kb
Host smart-11714435-8347-473a-84db-f17d29a94ecf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171817441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.3171817441
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1582434803
Short name T563
Test name
Test status
Simulation time 2623491022 ps
CPU time 2.39 seconds
Started Apr 28 12:24:19 PM PDT 24
Finished Apr 28 12:24:23 PM PDT 24
Peak memory 201652 kb
Host smart-5d3741a8-d016-4652-9e88-8b8a0d237cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582434803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.1582434803
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.811871999
Short name T485
Test name
Test status
Simulation time 2470842231 ps
CPU time 7.9 seconds
Started Apr 28 12:23:22 PM PDT 24
Finished Apr 28 12:23:31 PM PDT 24
Peak memory 201668 kb
Host smart-ec6c3abb-0ee0-4d10-9076-fbd87c2d41d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811871999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.811871999
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.1227802663
Short name T371
Test name
Test status
Simulation time 2185911449 ps
CPU time 6.33 seconds
Started Apr 28 12:23:18 PM PDT 24
Finished Apr 28 12:23:25 PM PDT 24
Peak memory 201744 kb
Host smart-3e7b4232-d6df-450a-83c8-6b437e749cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227802663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.1227802663
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.2199102285
Short name T546
Test name
Test status
Simulation time 2525044523 ps
CPU time 2.43 seconds
Started Apr 28 12:22:54 PM PDT 24
Finished Apr 28 12:23:07 PM PDT 24
Peak memory 201720 kb
Host smart-c36ce434-cde5-4bac-a0f0-cf56aa155234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199102285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.2199102285
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.2985430560
Short name T723
Test name
Test status
Simulation time 2118209204 ps
CPU time 3.54 seconds
Started Apr 28 12:23:06 PM PDT 24
Finished Apr 28 12:23:15 PM PDT 24
Peak memory 201660 kb
Host smart-d54aafaa-1855-465d-827b-585c05442e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985430560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.2985430560
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.716528220
Short name T172
Test name
Test status
Simulation time 8748491998 ps
CPU time 10.37 seconds
Started Apr 28 12:23:16 PM PDT 24
Finished Apr 28 12:23:27 PM PDT 24
Peak memory 201636 kb
Host smart-ca7920a9-b646-4dda-9e2e-2c2cedd8ba9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716528220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_st
ress_all.716528220
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.130392424
Short name T589
Test name
Test status
Simulation time 18432584898 ps
CPU time 12.27 seconds
Started Apr 28 12:22:55 PM PDT 24
Finished Apr 28 12:23:19 PM PDT 24
Peak memory 202252 kb
Host smart-7f1e1881-4353-48a1-97d5-b0d887e3a4ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130392424 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.130392424
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.2054616796
Short name T529
Test name
Test status
Simulation time 4121308969 ps
CPU time 3.8 seconds
Started Apr 28 12:23:05 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 201680 kb
Host smart-eaf3fe5c-4d15-441a-881c-b7ec6ba622b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054616796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.2054616796
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.2410392154
Short name T665
Test name
Test status
Simulation time 2027354720 ps
CPU time 2.45 seconds
Started Apr 28 12:24:25 PM PDT 24
Finished Apr 28 12:24:28 PM PDT 24
Peak memory 201712 kb
Host smart-4e74a8ae-d49d-4542-a6d7-507ed419c21e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410392154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.2410392154
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1859836427
Short name T708
Test name
Test status
Simulation time 3239395970 ps
CPU time 9.06 seconds
Started Apr 28 12:23:03 PM PDT 24
Finished Apr 28 12:23:19 PM PDT 24
Peak memory 201708 kb
Host smart-5fda47ad-341b-4886-9d8b-d732e42e18bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859836427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.1
859836427
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.2784835275
Short name T32
Test name
Test status
Simulation time 39274411858 ps
CPU time 20.27 seconds
Started Apr 28 12:23:00 PM PDT 24
Finished Apr 28 12:23:29 PM PDT 24
Peak memory 201968 kb
Host smart-84cb64af-6e35-42c0-b1ba-f77afe6f15e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784835275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.2784835275
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3948902381
Short name T408
Test name
Test status
Simulation time 5047082136 ps
CPU time 13.09 seconds
Started Apr 28 12:23:06 PM PDT 24
Finished Apr 28 12:23:24 PM PDT 24
Peak memory 201680 kb
Host smart-03a90bec-de86-43e9-b6d8-dcbf55f050a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948902381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.3948902381
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.686974940
Short name T211
Test name
Test status
Simulation time 2751569747 ps
CPU time 6.33 seconds
Started Apr 28 12:23:23 PM PDT 24
Finished Apr 28 12:23:31 PM PDT 24
Peak memory 201716 kb
Host smart-8c731df5-f8a9-41fc-bfd6-a9411e617317
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686974940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctr
l_edge_detect.686974940
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.4221503902
Short name T576
Test name
Test status
Simulation time 2635069357 ps
CPU time 2.43 seconds
Started Apr 28 12:23:16 PM PDT 24
Finished Apr 28 12:23:20 PM PDT 24
Peak memory 201668 kb
Host smart-fe9fd81c-35b7-4f22-a624-f3aed8c9ffb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221503902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.4221503902
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.2602580288
Short name T447
Test name
Test status
Simulation time 2477687958 ps
CPU time 7.33 seconds
Started Apr 28 12:23:28 PM PDT 24
Finished Apr 28 12:23:36 PM PDT 24
Peak memory 201704 kb
Host smart-8b3d7e46-7ba0-476b-b7d9-df39b5400641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602580288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.2602580288
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2661071113
Short name T714
Test name
Test status
Simulation time 2269856893 ps
CPU time 1.73 seconds
Started Apr 28 12:22:58 PM PDT 24
Finished Apr 28 12:23:09 PM PDT 24
Peak memory 201712 kb
Host smart-ae46c379-9cc5-4c77-94c9-5f9ae6225a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661071113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2661071113
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.2617812227
Short name T291
Test name
Test status
Simulation time 2512190433 ps
CPU time 4 seconds
Started Apr 28 12:24:22 PM PDT 24
Finished Apr 28 12:24:28 PM PDT 24
Peak memory 201720 kb
Host smart-2a6729c7-fef7-45c8-96f4-063ca57d684b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617812227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.2617812227
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.910568773
Short name T170
Test name
Test status
Simulation time 2191114541 ps
CPU time 1.09 seconds
Started Apr 28 12:23:16 PM PDT 24
Finished Apr 28 12:23:17 PM PDT 24
Peak memory 201684 kb
Host smart-300c6920-864f-4fa0-94f8-6800c25decaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910568773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.910568773
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.3252809612
Short name T31
Test name
Test status
Simulation time 228087601070 ps
CPU time 630.06 seconds
Started Apr 28 12:23:18 PM PDT 24
Finished Apr 28 12:33:49 PM PDT 24
Peak memory 201948 kb
Host smart-d87b346f-1900-425a-80a8-5d704581a559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252809612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.3252809612
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.988876278
Short name T176
Test name
Test status
Simulation time 48720699125 ps
CPU time 110.51 seconds
Started Apr 28 12:23:19 PM PDT 24
Finished Apr 28 12:25:11 PM PDT 24
Peak memory 210264 kb
Host smart-7f730809-df60-44bf-a433-4af66f10bd83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988876278 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.988876278
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.1226892463
Short name T796
Test name
Test status
Simulation time 4883737031 ps
CPU time 1.96 seconds
Started Apr 28 12:23:02 PM PDT 24
Finished Apr 28 12:23:11 PM PDT 24
Peak memory 201728 kb
Host smart-17606f4b-d3db-46d3-b68a-d1b59fef82be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226892463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.1226892463
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.2839755289
Short name T591
Test name
Test status
Simulation time 2012750301 ps
CPU time 5.55 seconds
Started Apr 28 12:21:53 PM PDT 24
Finished Apr 28 12:22:04 PM PDT 24
Peak memory 200188 kb
Host smart-84fdafa2-ea35-4807-af59-ff7b553a9f4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839755289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.2839755289
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.582247609
Short name T608
Test name
Test status
Simulation time 3451689343 ps
CPU time 1.72 seconds
Started Apr 28 12:18:57 PM PDT 24
Finished Apr 28 12:18:59 PM PDT 24
Peak memory 201804 kb
Host smart-84195a7c-7199-4016-986a-aecc4025680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582247609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.582247609
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.600399335
Short name T679
Test name
Test status
Simulation time 150423993558 ps
CPU time 388.54 seconds
Started Apr 28 12:22:45 PM PDT 24
Finished Apr 28 12:29:22 PM PDT 24
Peak memory 201560 kb
Host smart-bfca4e94-fcfe-455f-8314-6d79d9152275
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600399335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_combo_detect.600399335
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.4070545830
Short name T676
Test name
Test status
Simulation time 2417090486 ps
CPU time 6.95 seconds
Started Apr 28 12:20:37 PM PDT 24
Finished Apr 28 12:20:45 PM PDT 24
Peak memory 201712 kb
Host smart-c763344e-d0af-4e04-86e7-3da051fcc0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070545830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.4070545830
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.468421230
Short name T67
Test name
Test status
Simulation time 2508560847 ps
CPU time 3.05 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:02 PM PDT 24
Peak memory 201396 kb
Host smart-4ac96915-ba05-4980-805b-d435eccbfa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468421230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.468421230
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3527203279
Short name T541
Test name
Test status
Simulation time 67203881534 ps
CPU time 12.71 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:22:07 PM PDT 24
Peak memory 200448 kb
Host smart-111530a3-2ad1-4645-9a71-25b2e48fb1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527203279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.3527203279
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3880449792
Short name T18
Test name
Test status
Simulation time 3462047482 ps
CPU time 9.47 seconds
Started Apr 28 12:20:37 PM PDT 24
Finished Apr 28 12:20:47 PM PDT 24
Peak memory 201676 kb
Host smart-9e848960-b092-4572-8daa-b8d08acc150c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880449792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.3880449792
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.658500028
Short name T614
Test name
Test status
Simulation time 2944630109 ps
CPU time 7.4 seconds
Started Apr 28 12:22:13 PM PDT 24
Finished Apr 28 12:22:24 PM PDT 24
Peak memory 199932 kb
Host smart-5f489692-9284-43c2-be30-7e4868c20bc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658500028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_edge_detect.658500028
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.450675902
Short name T131
Test name
Test status
Simulation time 2653143168 ps
CPU time 1.91 seconds
Started Apr 28 12:18:52 PM PDT 24
Finished Apr 28 12:18:55 PM PDT 24
Peak memory 201724 kb
Host smart-7e797997-ba41-45a6-ba52-af151995a27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450675902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.450675902
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.3394536650
Short name T438
Test name
Test status
Simulation time 2471329998 ps
CPU time 3.95 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:02 PM PDT 24
Peak memory 201364 kb
Host smart-caa8a0cf-692e-423b-8134-b70c5998bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394536650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.3394536650
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.913226934
Short name T492
Test name
Test status
Simulation time 2120615577 ps
CPU time 3.08 seconds
Started Apr 28 12:22:37 PM PDT 24
Finished Apr 28 12:22:45 PM PDT 24
Peak memory 201628 kb
Host smart-b3995131-31a5-434f-bdeb-4fbac5f320a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913226934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.913226934
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.3468284149
Short name T659
Test name
Test status
Simulation time 2508080035 ps
CPU time 7.41 seconds
Started Apr 28 12:19:45 PM PDT 24
Finished Apr 28 12:19:54 PM PDT 24
Peak memory 201808 kb
Host smart-9c30d1cb-5adf-45ae-9309-a1ae3e2a6e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468284149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.3468284149
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.1117387996
Short name T534
Test name
Test status
Simulation time 2166330594 ps
CPU time 1.18 seconds
Started Apr 28 12:20:06 PM PDT 24
Finished Apr 28 12:20:08 PM PDT 24
Peak memory 201408 kb
Host smart-391bc928-5d5b-48bf-833d-771803d4d165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117387996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.1117387996
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.3084130966
Short name T664
Test name
Test status
Simulation time 9057802109 ps
CPU time 6.78 seconds
Started Apr 28 12:21:52 PM PDT 24
Finished Apr 28 12:22:01 PM PDT 24
Peak memory 199944 kb
Host smart-88810caa-269c-40eb-94e4-eb90b2d9cf18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084130966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.3084130966
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1132549559
Short name T642
Test name
Test status
Simulation time 22512459252 ps
CPU time 29.58 seconds
Started Apr 28 12:18:54 PM PDT 24
Finished Apr 28 12:19:24 PM PDT 24
Peak memory 217980 kb
Host smart-12e37a94-a79c-4015-8c4f-16c6e27a596e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132549559 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.1132549559
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3506000430
Short name T117
Test name
Test status
Simulation time 5473296075 ps
CPU time 5.97 seconds
Started Apr 28 12:18:52 PM PDT 24
Finished Apr 28 12:18:59 PM PDT 24
Peak memory 201728 kb
Host smart-5f377365-8e6b-401e-8d10-52524bd271e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506000430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.3506000430
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.1723230389
Short name T554
Test name
Test status
Simulation time 2008735948 ps
CPU time 5.92 seconds
Started Apr 28 12:23:02 PM PDT 24
Finished Apr 28 12:23:15 PM PDT 24
Peak memory 201708 kb
Host smart-24b56b18-2188-4abe-acc7-d949aba34d6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723230389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.1723230389
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3461881001
Short name T120
Test name
Test status
Simulation time 3595521755 ps
CPU time 3.02 seconds
Started Apr 28 12:23:06 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 201768 kb
Host smart-ea4d8059-6f11-4846-a71b-08dfd32d38ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461881001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.3
461881001
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3545574910
Short name T231
Test name
Test status
Simulation time 120834127439 ps
CPU time 325.67 seconds
Started Apr 28 12:23:14 PM PDT 24
Finished Apr 28 12:28:41 PM PDT 24
Peak memory 201868 kb
Host smart-ccec5774-c3a0-487f-998c-644ffc60f986
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545574910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.3545574910
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.3025129402
Short name T46
Test name
Test status
Simulation time 27993164710 ps
CPU time 14.4 seconds
Started Apr 28 12:23:29 PM PDT 24
Finished Apr 28 12:23:44 PM PDT 24
Peak memory 201992 kb
Host smart-cb2cf7d3-aa55-4169-ad6a-019d7bf590ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025129402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.3025129402
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.165610562
Short name T412
Test name
Test status
Simulation time 478834356687 ps
CPU time 125.72 seconds
Started Apr 28 12:23:07 PM PDT 24
Finished Apr 28 12:25:17 PM PDT 24
Peak memory 201632 kb
Host smart-66992cc3-ea9d-4a73-b2c6-1b173693690d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165610562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_ec_pwr_on_rst.165610562
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.643822721
Short name T181
Test name
Test status
Simulation time 2682210938 ps
CPU time 7.5 seconds
Started Apr 28 12:23:22 PM PDT 24
Finished Apr 28 12:23:31 PM PDT 24
Peak memory 201652 kb
Host smart-8410527d-eeb3-4bb6-bfcf-49df3658daf9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643822721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctr
l_edge_detect.643822721
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1057232839
Short name T751
Test name
Test status
Simulation time 2677417832 ps
CPU time 1.39 seconds
Started Apr 28 12:23:27 PM PDT 24
Finished Apr 28 12:23:30 PM PDT 24
Peak memory 201732 kb
Host smart-d0011aed-22e0-45e8-90e4-60cabc3bf547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057232839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.1057232839
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2145987228
Short name T710
Test name
Test status
Simulation time 2484108971 ps
CPU time 1.51 seconds
Started Apr 28 12:23:13 PM PDT 24
Finished Apr 28 12:23:17 PM PDT 24
Peak memory 201688 kb
Host smart-635be4f8-6bca-48f9-b9fe-cccaffdc47e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145987228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.2145987228
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.4097952774
Short name T740
Test name
Test status
Simulation time 2043391889 ps
CPU time 3.38 seconds
Started Apr 28 12:23:19 PM PDT 24
Finished Apr 28 12:23:29 PM PDT 24
Peak memory 201596 kb
Host smart-bd281f27-27e8-474a-ab99-3f0d6922ea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097952774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.4097952774
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.4124255590
Short name T417
Test name
Test status
Simulation time 2515161127 ps
CPU time 6.9 seconds
Started Apr 28 12:23:20 PM PDT 24
Finished Apr 28 12:23:28 PM PDT 24
Peak memory 201724 kb
Host smart-f14b3a0a-df97-481a-9e8d-07cbab3fd5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124255590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.4124255590
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.3480535148
Short name T370
Test name
Test status
Simulation time 2136617802 ps
CPU time 1.53 seconds
Started Apr 28 12:23:15 PM PDT 24
Finished Apr 28 12:23:18 PM PDT 24
Peak memory 201596 kb
Host smart-36f8d005-38bd-4b36-81c9-3aa1c5dafb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480535148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.3480535148
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.3106216684
Short name T173
Test name
Test status
Simulation time 46225590013 ps
CPU time 126.23 seconds
Started Apr 28 12:23:24 PM PDT 24
Finished Apr 28 12:25:31 PM PDT 24
Peak memory 201700 kb
Host smart-c7166cfc-5797-45a6-b114-f8e9f03c0a52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106216684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.3106216684
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1688715422
Short name T240
Test name
Test status
Simulation time 68501133336 ps
CPU time 42.07 seconds
Started Apr 28 12:23:05 PM PDT 24
Finished Apr 28 12:23:53 PM PDT 24
Peak memory 218444 kb
Host smart-055b9ac4-4fdc-4a93-aece-61ec33962d8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688715422 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.1688715422
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3059847256
Short name T615
Test name
Test status
Simulation time 3849439558 ps
CPU time 5.98 seconds
Started Apr 28 12:23:03 PM PDT 24
Finished Apr 28 12:23:16 PM PDT 24
Peak memory 201376 kb
Host smart-03ebb61c-4091-49ca-960c-938c154c5dc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059847256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.3059847256
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.1098027677
Short name T295
Test name
Test status
Simulation time 2033871720 ps
CPU time 2.02 seconds
Started Apr 28 12:23:05 PM PDT 24
Finished Apr 28 12:23:13 PM PDT 24
Peak memory 201464 kb
Host smart-5bd7a671-abab-4455-a7bc-0ad44a00a7ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098027677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.1098027677
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1992548635
Short name T625
Test name
Test status
Simulation time 2938155910 ps
CPU time 8.96 seconds
Started Apr 28 12:23:02 PM PDT 24
Finished Apr 28 12:23:18 PM PDT 24
Peak memory 201712 kb
Host smart-ff58de3b-5523-4a97-a89f-ba19018bfd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992548635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.1
992548635
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.1524035
Short name T45
Test name
Test status
Simulation time 64487516272 ps
CPU time 71.13 seconds
Started Apr 28 12:23:09 PM PDT 24
Finished Apr 28 12:24:23 PM PDT 24
Peak memory 201808 kb
Host smart-bd3a5611-aae5-49f9-a1d1-777fdf1c0531
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl
_combo_detect.1524035
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1963895457
Short name T490
Test name
Test status
Simulation time 362825373926 ps
CPU time 938.26 seconds
Started Apr 28 12:23:03 PM PDT 24
Finished Apr 28 12:38:48 PM PDT 24
Peak memory 201636 kb
Host smart-6da82b93-cc79-4eae-938a-fff24335e2a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963895457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.1963895457
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.740527830
Short name T673
Test name
Test status
Simulation time 2838529808 ps
CPU time 2.52 seconds
Started Apr 28 12:23:07 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 201660 kb
Host smart-2dbc709a-ad2f-4732-b9e2-15e82b9f06d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740527830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctr
l_edge_detect.740527830
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2454415887
Short name T498
Test name
Test status
Simulation time 2611913924 ps
CPU time 7.71 seconds
Started Apr 28 12:23:15 PM PDT 24
Finished Apr 28 12:23:24 PM PDT 24
Peak memory 201672 kb
Host smart-19962f60-c5f5-4e71-965b-dca319a882fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454415887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.2454415887
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1747953691
Short name T396
Test name
Test status
Simulation time 2513291294 ps
CPU time 1.5 seconds
Started Apr 28 12:23:05 PM PDT 24
Finished Apr 28 12:23:12 PM PDT 24
Peak memory 201664 kb
Host smart-da734c9d-d84d-464d-ac61-7af91d9c29ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747953691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.1747953691
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1276568963
Short name T633
Test name
Test status
Simulation time 2113837584 ps
CPU time 5.03 seconds
Started Apr 28 12:23:03 PM PDT 24
Finished Apr 28 12:23:15 PM PDT 24
Peak memory 201588 kb
Host smart-82532dc4-8395-4752-b5fa-e3423a40fd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276568963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.1276568963
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.1384342284
Short name T150
Test name
Test status
Simulation time 2518282913 ps
CPU time 3.73 seconds
Started Apr 28 12:23:27 PM PDT 24
Finished Apr 28 12:23:31 PM PDT 24
Peak memory 201724 kb
Host smart-9b14b5a1-97d1-4308-9b20-639e23d41037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384342284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.1384342284
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.2996937089
Short name T294
Test name
Test status
Simulation time 2114207872 ps
CPU time 3.45 seconds
Started Apr 28 12:22:58 PM PDT 24
Finished Apr 28 12:23:11 PM PDT 24
Peak memory 201656 kb
Host smart-13c2a5d7-6610-4418-bded-9a0f02ac8e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996937089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.2996937089
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.2765534106
Short name T143
Test name
Test status
Simulation time 15440635099 ps
CPU time 10.53 seconds
Started Apr 28 12:24:06 PM PDT 24
Finished Apr 28 12:24:19 PM PDT 24
Peak memory 200244 kb
Host smart-de084838-0323-40b2-8d18-2a722027eb95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765534106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.2765534106
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2270125747
Short name T35
Test name
Test status
Simulation time 29369061924 ps
CPU time 78.78 seconds
Started Apr 28 12:23:13 PM PDT 24
Finished Apr 28 12:24:34 PM PDT 24
Peak memory 210420 kb
Host smart-0fbd80ba-2f68-4f03-9319-b40b885f4607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270125747 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.2270125747
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1536184012
Short name T132
Test name
Test status
Simulation time 4133074424 ps
CPU time 3.99 seconds
Started Apr 28 12:23:03 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 201372 kb
Host smart-ec9eac24-3a2c-4a4b-a660-44fe1cdcc18e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536184012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.1536184012
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.1371344305
Short name T731
Test name
Test status
Simulation time 2022736108 ps
CPU time 3.08 seconds
Started Apr 28 12:24:29 PM PDT 24
Finished Apr 28 12:24:35 PM PDT 24
Peak memory 201744 kb
Host smart-f0c14c1e-fb03-479b-8aa8-826a19b405ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371344305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.1371344305
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1218212692
Short name T446
Test name
Test status
Simulation time 3520751431 ps
CPU time 2.42 seconds
Started Apr 28 12:23:09 PM PDT 24
Finished Apr 28 12:23:15 PM PDT 24
Peak memory 201720 kb
Host smart-464a1ca7-53d5-419b-9102-4a30fea4e59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218212692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.1
218212692
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.2718049286
Short name T167
Test name
Test status
Simulation time 139388342469 ps
CPU time 361.86 seconds
Started Apr 28 12:22:58 PM PDT 24
Finished Apr 28 12:29:10 PM PDT 24
Peak memory 201988 kb
Host smart-718cc124-6a49-4212-8bcc-80fac1379613
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718049286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.2718049286
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3530756021
Short name T358
Test name
Test status
Simulation time 84082073270 ps
CPU time 222.32 seconds
Started Apr 28 12:24:29 PM PDT 24
Finished Apr 28 12:28:13 PM PDT 24
Peak memory 201920 kb
Host smart-7ae8b876-4228-4db5-b28a-c0b51c3d0051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530756021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.3530756021
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3040105009
Short name T772
Test name
Test status
Simulation time 4842962574 ps
CPU time 3.18 seconds
Started Apr 28 12:23:11 PM PDT 24
Finished Apr 28 12:23:16 PM PDT 24
Peak memory 201708 kb
Host smart-0723be59-7516-46d3-aa0b-01558e6230a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040105009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.3040105009
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.3234990776
Short name T142
Test name
Test status
Simulation time 1018986256726 ps
CPU time 1501.15 seconds
Started Apr 28 12:24:06 PM PDT 24
Finished Apr 28 12:49:09 PM PDT 24
Peak memory 200272 kb
Host smart-a4e3c80f-c025-45b7-9ce7-7c9618527704
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234990776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.3234990776
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.528048371
Short name T683
Test name
Test status
Simulation time 2614191982 ps
CPU time 7.24 seconds
Started Apr 28 12:24:06 PM PDT 24
Finished Apr 28 12:24:15 PM PDT 24
Peak memory 199992 kb
Host smart-c047a9f7-e0e5-4833-881d-92778fbfc979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528048371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.528048371
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2812260774
Short name T59
Test name
Test status
Simulation time 2477491638 ps
CPU time 3.57 seconds
Started Apr 28 12:23:12 PM PDT 24
Finished Apr 28 12:23:17 PM PDT 24
Peak memory 201648 kb
Host smart-0c61413b-1e64-461f-9c1a-ac5863d5d8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812260774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.2812260774
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.69064410
Short name T190
Test name
Test status
Simulation time 2244954258 ps
CPU time 1.87 seconds
Started Apr 28 12:23:19 PM PDT 24
Finished Apr 28 12:23:22 PM PDT 24
Peak memory 201632 kb
Host smart-aa664fd7-a4aa-4984-a213-4a82f9df8844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69064410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.69064410
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2876632508
Short name T400
Test name
Test status
Simulation time 2530516205 ps
CPU time 3.12 seconds
Started Apr 28 12:24:29 PM PDT 24
Finished Apr 28 12:24:35 PM PDT 24
Peak memory 201776 kb
Host smart-1bd998c4-3e83-4cd3-a61c-19cae73127ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876632508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.2876632508
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.2075391473
Short name T774
Test name
Test status
Simulation time 2144838098 ps
CPU time 1.56 seconds
Started Apr 28 12:23:24 PM PDT 24
Finished Apr 28 12:23:27 PM PDT 24
Peak memory 201592 kb
Host smart-e6a70363-206c-4d13-a2eb-05ad2997d744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075391473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.2075391473
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.3588640678
Short name T239
Test name
Test status
Simulation time 212904895800 ps
CPU time 45.59 seconds
Started Apr 28 12:23:07 PM PDT 24
Finished Apr 28 12:23:57 PM PDT 24
Peak memory 201956 kb
Host smart-e3b4c44c-de55-4748-bc88-084ddf24b650
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588640678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.3588640678
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2792969018
Short name T179
Test name
Test status
Simulation time 57131814631 ps
CPU time 36.81 seconds
Started Apr 28 12:24:06 PM PDT 24
Finished Apr 28 12:24:45 PM PDT 24
Peak memory 209028 kb
Host smart-213866eb-c7e9-4645-bf3a-ddfba3f1d5dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792969018 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.2792969018
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.682497256
Short name T436
Test name
Test status
Simulation time 4547481502 ps
CPU time 7.3 seconds
Started Apr 28 12:23:07 PM PDT 24
Finished Apr 28 12:23:19 PM PDT 24
Peak memory 201652 kb
Host smart-9936c0a4-b8d1-4d46-9683-08cf83b920e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682497256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_ultra_low_pwr.682497256
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.2728831497
Short name T636
Test name
Test status
Simulation time 2019272480 ps
CPU time 3.3 seconds
Started Apr 28 12:23:25 PM PDT 24
Finished Apr 28 12:23:30 PM PDT 24
Peak memory 201764 kb
Host smart-30583122-88b5-4695-81fe-e38605636666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728831497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.2728831497
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1243338985
Short name T528
Test name
Test status
Simulation time 2914161632 ps
CPU time 4.11 seconds
Started Apr 28 12:23:07 PM PDT 24
Finished Apr 28 12:23:16 PM PDT 24
Peak memory 201708 kb
Host smart-c5d0f50a-2185-4156-83e4-87565555261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243338985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.1
243338985
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.2888440224
Short name T356
Test name
Test status
Simulation time 173692082266 ps
CPU time 86.84 seconds
Started Apr 28 12:23:07 PM PDT 24
Finished Apr 28 12:24:38 PM PDT 24
Peak memory 201868 kb
Host smart-eeb62e25-676a-4460-b779-45fdedfc203b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888440224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.2888440224
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.837596433
Short name T342
Test name
Test status
Simulation time 165563588351 ps
CPU time 213.97 seconds
Started Apr 28 12:23:24 PM PDT 24
Finished Apr 28 12:26:59 PM PDT 24
Peak memory 201864 kb
Host smart-48384475-a857-435a-b52f-ef96169cfaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837596433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_wi
th_pre_cond.837596433
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2209217330
Short name T763
Test name
Test status
Simulation time 2750728152 ps
CPU time 2.32 seconds
Started Apr 28 12:24:26 PM PDT 24
Finished Apr 28 12:24:30 PM PDT 24
Peak memory 201692 kb
Host smart-bcb60612-c07e-47d4-86d4-f7c590b9c31a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209217330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.2209217330
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.3629269096
Short name T641
Test name
Test status
Simulation time 3021392866 ps
CPU time 2.6 seconds
Started Apr 28 12:23:22 PM PDT 24
Finished Apr 28 12:23:26 PM PDT 24
Peak memory 201680 kb
Host smart-797292bf-aa37-49d7-a4cc-662010a5deda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629269096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.3629269096
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3011606269
Short name T483
Test name
Test status
Simulation time 2607349532 ps
CPU time 6.76 seconds
Started Apr 28 12:23:24 PM PDT 24
Finished Apr 28 12:23:33 PM PDT 24
Peak memory 201756 kb
Host smart-023bbe87-5ab1-4a01-b5cc-80f434f2038b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011606269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.3011606269
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.167799270
Short name T667
Test name
Test status
Simulation time 2472257617 ps
CPU time 5.79 seconds
Started Apr 28 12:23:28 PM PDT 24
Finished Apr 28 12:23:34 PM PDT 24
Peak memory 201644 kb
Host smart-98adafb1-b415-4871-8873-9363f02657cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167799270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.167799270
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1980039096
Short name T186
Test name
Test status
Simulation time 2163629892 ps
CPU time 1.65 seconds
Started Apr 28 12:23:27 PM PDT 24
Finished Apr 28 12:23:29 PM PDT 24
Peak memory 201648 kb
Host smart-7c0f60b2-bad5-4d81-aa05-3961d0e5a800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980039096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.1980039096
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3581195810
Short name T166
Test name
Test status
Simulation time 2508251262 ps
CPU time 7.37 seconds
Started Apr 28 12:22:58 PM PDT 24
Finished Apr 28 12:23:15 PM PDT 24
Peak memory 201836 kb
Host smart-d0434134-b37a-4819-82d6-cdec25b15fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581195810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.3581195810
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.2328337548
Short name T193
Test name
Test status
Simulation time 2112634650 ps
CPU time 6.02 seconds
Started Apr 28 12:23:27 PM PDT 24
Finished Apr 28 12:23:34 PM PDT 24
Peak memory 201592 kb
Host smart-27c4769d-de79-4eda-9b7e-843a42a4898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328337548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.2328337548
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.3509115867
Short name T9
Test name
Test status
Simulation time 9424967103 ps
CPU time 11.51 seconds
Started Apr 28 12:23:24 PM PDT 24
Finished Apr 28 12:23:37 PM PDT 24
Peak memory 201768 kb
Host smart-581cbd2a-a7c3-4dc5-a157-84ae42a983e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509115867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.3509115867
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3243545372
Short name T114
Test name
Test status
Simulation time 101099725167 ps
CPU time 59.74 seconds
Started Apr 28 12:23:09 PM PDT 24
Finished Apr 28 12:24:12 PM PDT 24
Peak memory 218356 kb
Host smart-7a7edd66-237e-40af-8672-6e6b9f61e44f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243545372 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.3243545372
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2756220271
Short name T590
Test name
Test status
Simulation time 9153287372 ps
CPU time 2.98 seconds
Started Apr 28 12:23:30 PM PDT 24
Finished Apr 28 12:23:34 PM PDT 24
Peak memory 201684 kb
Host smart-c315f03b-28ac-4c5c-8c32-a932d638b6b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756220271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.2756220271
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.394752285
Short name T785
Test name
Test status
Simulation time 2056891197 ps
CPU time 1.3 seconds
Started Apr 28 12:23:21 PM PDT 24
Finished Apr 28 12:23:23 PM PDT 24
Peak memory 201692 kb
Host smart-e93afea1-04de-4a40-8204-b76d801a0ee3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394752285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_tes
t.394752285
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1287206113
Short name T90
Test name
Test status
Simulation time 3089012522 ps
CPU time 2.67 seconds
Started Apr 28 12:23:28 PM PDT 24
Finished Apr 28 12:23:31 PM PDT 24
Peak memory 201776 kb
Host smart-f6b4105c-df22-4994-9064-bceb3fd2a6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287206113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.1
287206113
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1367403253
Short name T99
Test name
Test status
Simulation time 69947223278 ps
CPU time 192.8 seconds
Started Apr 28 12:23:23 PM PDT 24
Finished Apr 28 12:26:37 PM PDT 24
Peak memory 201928 kb
Host smart-2fea80f4-c4bf-4916-bcf3-d014b1d499b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367403253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.1367403253
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1832249058
Short name T81
Test name
Test status
Simulation time 77398837861 ps
CPU time 36.46 seconds
Started Apr 28 12:23:20 PM PDT 24
Finished Apr 28 12:23:58 PM PDT 24
Peak memory 201836 kb
Host smart-5bfc9bf6-9b18-4370-81dd-1b6f7ff49f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832249058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.1832249058
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2427108064
Short name T698
Test name
Test status
Simulation time 3306340016 ps
CPU time 7.47 seconds
Started Apr 28 12:23:04 PM PDT 24
Finished Apr 28 12:23:17 PM PDT 24
Peak memory 201640 kb
Host smart-40f99ded-eea0-4795-b27e-4f10f82da142
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427108064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.2427108064
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2642884751
Short name T536
Test name
Test status
Simulation time 2613443165 ps
CPU time 6.56 seconds
Started Apr 28 12:23:28 PM PDT 24
Finished Apr 28 12:23:35 PM PDT 24
Peak memory 201664 kb
Host smart-32b8db3a-aa62-46d8-a024-6ea51e605a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642884751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.2642884751
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.582995211
Short name T545
Test name
Test status
Simulation time 2496623877 ps
CPU time 2.51 seconds
Started Apr 28 12:23:26 PM PDT 24
Finished Apr 28 12:23:29 PM PDT 24
Peak memory 201824 kb
Host smart-7e6f90e8-0461-4cb6-baf3-709d31ae73ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582995211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.582995211
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.879919718
Short name T404
Test name
Test status
Simulation time 2220555347 ps
CPU time 3.74 seconds
Started Apr 28 12:23:13 PM PDT 24
Finished Apr 28 12:23:18 PM PDT 24
Peak memory 201644 kb
Host smart-ccb54baa-37a9-4259-9633-703c7f3841a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879919718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.879919718
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2772187525
Short name T124
Test name
Test status
Simulation time 2516700123 ps
CPU time 3.92 seconds
Started Apr 28 12:23:19 PM PDT 24
Finished Apr 28 12:23:24 PM PDT 24
Peak memory 201712 kb
Host smart-93f0dbbd-5797-47d8-8f8d-3936c6169a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772187525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.2772187525
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.1976091156
Short name T672
Test name
Test status
Simulation time 2134290135 ps
CPU time 1.91 seconds
Started Apr 28 12:23:13 PM PDT 24
Finished Apr 28 12:23:17 PM PDT 24
Peak memory 201568 kb
Host smart-4f2ca1db-91ae-433b-afd4-808bfbf4a4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976091156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.1976091156
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.1728788956
Short name T163
Test name
Test status
Simulation time 76530832171 ps
CPU time 93.58 seconds
Started Apr 28 12:23:20 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 201984 kb
Host smart-f8af7a12-0e9f-42bb-b2ec-48113e473907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728788956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.1728788956
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3195054462
Short name T380
Test name
Test status
Simulation time 13228798400 ps
CPU time 35.81 seconds
Started Apr 28 12:23:18 PM PDT 24
Finished Apr 28 12:23:55 PM PDT 24
Peak memory 202144 kb
Host smart-12c243b9-178c-41a0-b930-d881dcea8aee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195054462 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.3195054462
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2121246435
Short name T86
Test name
Test status
Simulation time 7085850554 ps
CPU time 2.53 seconds
Started Apr 28 12:23:27 PM PDT 24
Finished Apr 28 12:23:30 PM PDT 24
Peak memory 201780 kb
Host smart-14a1c8fd-784a-46af-8ed7-f9e746b4782f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121246435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.2121246435
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.992094066
Short name T701
Test name
Test status
Simulation time 2031607619 ps
CPU time 1.99 seconds
Started Apr 28 12:23:24 PM PDT 24
Finished Apr 28 12:23:27 PM PDT 24
Peak memory 201740 kb
Host smart-94b3ad4e-c078-4a6c-88a6-104470ead1d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992094066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_tes
t.992094066
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3323838644
Short name T265
Test name
Test status
Simulation time 3765368844 ps
CPU time 9.94 seconds
Started Apr 28 12:23:19 PM PDT 24
Finished Apr 28 12:23:30 PM PDT 24
Peak memory 201812 kb
Host smart-7c998ecb-5363-4b3d-97b4-f9f62d552805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323838644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.3
323838644
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.3084782844
Short name T98
Test name
Test status
Simulation time 65733020544 ps
CPU time 31.32 seconds
Started Apr 28 12:23:22 PM PDT 24
Finished Apr 28 12:23:54 PM PDT 24
Peak memory 201816 kb
Host smart-6e2aaf83-dda3-4414-8324-6ea546af7f8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084782844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.3084782844
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3819442547
Short name T5
Test name
Test status
Simulation time 2911685184 ps
CPU time 0.98 seconds
Started Apr 28 12:23:28 PM PDT 24
Finished Apr 28 12:23:30 PM PDT 24
Peak memory 201632 kb
Host smart-4fac6ed5-b05d-40e0-8ae4-57c619ec591b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819442547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.3819442547
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.2064173717
Short name T686
Test name
Test status
Simulation time 4343447839 ps
CPU time 7.03 seconds
Started Apr 28 12:23:14 PM PDT 24
Finished Apr 28 12:23:22 PM PDT 24
Peak memory 201756 kb
Host smart-8d210f4f-6c39-4a9c-88f6-a7438108ada7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064173717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.2064173717
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2029319640
Short name T64
Test name
Test status
Simulation time 2643073481 ps
CPU time 1.59 seconds
Started Apr 28 12:23:10 PM PDT 24
Finished Apr 28 12:23:18 PM PDT 24
Peak memory 201644 kb
Host smart-2ef21bac-1878-47c2-aa6b-024e31f7cb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029319640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.2029319640
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1469303238
Short name T395
Test name
Test status
Simulation time 2455935010 ps
CPU time 7.95 seconds
Started Apr 28 12:23:23 PM PDT 24
Finished Apr 28 12:23:33 PM PDT 24
Peak memory 201692 kb
Host smart-b1ba597a-36ae-439b-9347-9c8f39d5a156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469303238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.1469303238
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.3461179592
Short name T440
Test name
Test status
Simulation time 2089848166 ps
CPU time 3.48 seconds
Started Apr 28 12:23:20 PM PDT 24
Finished Apr 28 12:23:25 PM PDT 24
Peak memory 201548 kb
Host smart-b41733cd-6aed-402c-a34a-265fe221c477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461179592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.3461179592
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1554931444
Short name T640
Test name
Test status
Simulation time 2526539210 ps
CPU time 2.29 seconds
Started Apr 28 12:23:20 PM PDT 24
Finished Apr 28 12:23:24 PM PDT 24
Peak memory 201716 kb
Host smart-92b614d7-8d66-4aec-92e6-3e90173fcebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554931444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.1554931444
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.2260974565
Short name T488
Test name
Test status
Simulation time 2112802329 ps
CPU time 3.43 seconds
Started Apr 28 12:23:05 PM PDT 24
Finished Apr 28 12:23:14 PM PDT 24
Peak memory 201664 kb
Host smart-afd72d1e-8b89-4cbb-aa21-95379b3079eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260974565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.2260974565
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.2678164208
Short name T657
Test name
Test status
Simulation time 8849074056 ps
CPU time 13.04 seconds
Started Apr 28 12:23:09 PM PDT 24
Finished Apr 28 12:23:26 PM PDT 24
Peak memory 201412 kb
Host smart-003854df-3bc1-4a3d-b661-3074467b0697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678164208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.2678164208
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3183112266
Short name T123
Test name
Test status
Simulation time 42111960357 ps
CPU time 117.87 seconds
Started Apr 28 12:23:36 PM PDT 24
Finished Apr 28 12:25:34 PM PDT 24
Peak memory 210224 kb
Host smart-79645ba5-a4fe-4307-9b50-9a7d326c1978
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183112266 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.3183112266
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.509289755
Short name T693
Test name
Test status
Simulation time 5652111556 ps
CPU time 6.6 seconds
Started Apr 28 12:23:37 PM PDT 24
Finished Apr 28 12:23:44 PM PDT 24
Peak memory 201704 kb
Host smart-cd217ef4-1831-49d6-a345-ee1c96b0bf52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509289755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_ultra_low_pwr.509289755
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.1573723330
Short name T185
Test name
Test status
Simulation time 2028224441 ps
CPU time 2 seconds
Started Apr 28 12:23:22 PM PDT 24
Finished Apr 28 12:23:25 PM PDT 24
Peak memory 201708 kb
Host smart-7007f703-9c7f-457c-91bd-d2ec2f8a2b35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573723330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.1573723330
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1420102530
Short name T654
Test name
Test status
Simulation time 3414979299 ps
CPU time 2.81 seconds
Started Apr 28 12:23:26 PM PDT 24
Finished Apr 28 12:23:30 PM PDT 24
Peak memory 201808 kb
Host smart-e0badaae-960c-4f2c-b27f-eb4c2b79b72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420102530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.1
420102530
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.1379643490
Short name T242
Test name
Test status
Simulation time 91372758947 ps
CPU time 27.97 seconds
Started Apr 28 12:23:22 PM PDT 24
Finished Apr 28 12:23:51 PM PDT 24
Peak memory 201888 kb
Host smart-0cf8caba-7c81-416f-9775-dc99400edfbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379643490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.1379643490
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.167372089
Short name T663
Test name
Test status
Simulation time 2974394094 ps
CPU time 1.92 seconds
Started Apr 28 12:23:14 PM PDT 24
Finished Apr 28 12:23:18 PM PDT 24
Peak memory 201752 kb
Host smart-7b0413da-0990-4194-ad3d-4f54a14e862f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167372089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ec_pwr_on_rst.167372089
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.3172664632
Short name T627
Test name
Test status
Simulation time 3104770829 ps
CPU time 2.17 seconds
Started Apr 28 12:23:17 PM PDT 24
Finished Apr 28 12:23:19 PM PDT 24
Peak memory 201644 kb
Host smart-51c25077-57b5-4753-b5fd-89cc65931b8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172664632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.3172664632
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3354937171
Short name T523
Test name
Test status
Simulation time 2650231744 ps
CPU time 1.81 seconds
Started Apr 28 12:23:21 PM PDT 24
Finished Apr 28 12:23:24 PM PDT 24
Peak memory 201732 kb
Host smart-4438c4bb-625e-4658-850f-f0dab74e7a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354937171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.3354937171
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2855127620
Short name T738
Test name
Test status
Simulation time 2469358500 ps
CPU time 2.69 seconds
Started Apr 28 12:23:18 PM PDT 24
Finished Apr 28 12:23:23 PM PDT 24
Peak memory 201732 kb
Host smart-30259746-c926-4e56-8cdd-a69fe2a63380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855127620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.2855127620
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2067123233
Short name T414
Test name
Test status
Simulation time 2162674804 ps
CPU time 3 seconds
Started Apr 28 12:23:32 PM PDT 24
Finished Apr 28 12:23:35 PM PDT 24
Peak memory 201672 kb
Host smart-203481cd-cc2d-4784-a576-749c7952960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067123233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.2067123233
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3241718171
Short name T697
Test name
Test status
Simulation time 2519405415 ps
CPU time 3.96 seconds
Started Apr 28 12:23:35 PM PDT 24
Finished Apr 28 12:23:39 PM PDT 24
Peak memory 201772 kb
Host smart-213dcb7b-9889-444b-86a8-c92ef3e0553c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241718171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.3241718171
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.4075032656
Short name T112
Test name
Test status
Simulation time 2129983468 ps
CPU time 2.11 seconds
Started Apr 28 12:23:21 PM PDT 24
Finished Apr 28 12:23:24 PM PDT 24
Peak memory 201596 kb
Host smart-952a2d8e-ca53-414a-807f-17c473caf325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075032656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.4075032656
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.3764835102
Short name T760
Test name
Test status
Simulation time 9734685462 ps
CPU time 6.32 seconds
Started Apr 28 12:23:43 PM PDT 24
Finished Apr 28 12:23:51 PM PDT 24
Peak memory 201700 kb
Host smart-2d1811f3-659b-4e03-9c40-5fe15c9ef158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764835102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.3764835102
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.665744072
Short name T493
Test name
Test status
Simulation time 1699239619092 ps
CPU time 28.03 seconds
Started Apr 28 12:23:32 PM PDT 24
Finished Apr 28 12:24:01 PM PDT 24
Peak memory 201800 kb
Host smart-7dbae3cf-2c8c-4ee8-9c9f-d64ab6e11778
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665744072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ultra_low_pwr.665744072
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.3982252133
Short name T725
Test name
Test status
Simulation time 2011614212 ps
CPU time 5.73 seconds
Started Apr 28 12:23:42 PM PDT 24
Finished Apr 28 12:23:49 PM PDT 24
Peak memory 201696 kb
Host smart-4ac323c5-da09-4b64-930a-c521daa82fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982252133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.3982252133
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3442259913
Short name T616
Test name
Test status
Simulation time 3832157435 ps
CPU time 5.89 seconds
Started Apr 28 12:24:31 PM PDT 24
Finished Apr 28 12:24:41 PM PDT 24
Peak memory 201748 kb
Host smart-7bdbbc7b-6f46-4e90-a6ac-2934b0fdf6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442259913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.3
442259913
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.999203918
Short name T221
Test name
Test status
Simulation time 158180550029 ps
CPU time 207.13 seconds
Started Apr 28 12:23:28 PM PDT 24
Finished Apr 28 12:26:56 PM PDT 24
Peak memory 201924 kb
Host smart-7f45c7c2-b127-46de-9651-52027d8ec001
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999203918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_combo_detect.999203918
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.92207865
Short name T338
Test name
Test status
Simulation time 64405823881 ps
CPU time 162.57 seconds
Started Apr 28 12:23:18 PM PDT 24
Finished Apr 28 12:26:03 PM PDT 24
Peak memory 201896 kb
Host smart-1a29ce6f-fe51-4fad-b0ef-b05daeecfc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92207865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_wit
h_pre_cond.92207865
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3004753691
Short name T402
Test name
Test status
Simulation time 4694402333 ps
CPU time 2.82 seconds
Started Apr 28 12:23:19 PM PDT 24
Finished Apr 28 12:23:23 PM PDT 24
Peak memory 201668 kb
Host smart-b0d3f411-12d4-4fd7-9839-31c5c9899947
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004753691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.3004753691
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.1746701604
Short name T687
Test name
Test status
Simulation time 2818040239 ps
CPU time 5.7 seconds
Started Apr 28 12:23:40 PM PDT 24
Finished Apr 28 12:23:46 PM PDT 24
Peak memory 201664 kb
Host smart-7b0cbda9-4d6d-4829-84c3-0f6f5a8d37f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746701604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.1746701604
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.4086322517
Short name T381
Test name
Test status
Simulation time 2631986964 ps
CPU time 2.5 seconds
Started Apr 28 12:23:29 PM PDT 24
Finished Apr 28 12:23:32 PM PDT 24
Peak memory 201656 kb
Host smart-9eb60acc-bddf-47fb-9c88-f122808ee131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086322517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.4086322517
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.637902298
Short name T60
Test name
Test status
Simulation time 2441632993 ps
CPU time 7.55 seconds
Started Apr 28 12:23:19 PM PDT 24
Finished Apr 28 12:23:28 PM PDT 24
Peak memory 201600 kb
Host smart-736460e6-02da-4ebf-93e6-d12e05803316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637902298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.637902298
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3001969939
Short name T703
Test name
Test status
Simulation time 2217040437 ps
CPU time 2.23 seconds
Started Apr 28 12:23:39 PM PDT 24
Finished Apr 28 12:23:42 PM PDT 24
Peak memory 201636 kb
Host smart-677b779a-5ac4-4c34-918a-e74774a8ea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001969939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.3001969939
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1681100070
Short name T426
Test name
Test status
Simulation time 2547471150 ps
CPU time 1.96 seconds
Started Apr 28 12:23:19 PM PDT 24
Finished Apr 28 12:23:22 PM PDT 24
Peak memory 201752 kb
Host smart-f9e66329-de81-4820-87df-7c304b219c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681100070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1681100070
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.3300162396
Short name T675
Test name
Test status
Simulation time 2136459311 ps
CPU time 1.91 seconds
Started Apr 28 12:23:25 PM PDT 24
Finished Apr 28 12:23:28 PM PDT 24
Peak memory 201600 kb
Host smart-cee771c9-3d6b-4d34-95e9-3e8a5858027c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300162396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.3300162396
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1932479706
Short name T713
Test name
Test status
Simulation time 16255992038 ps
CPU time 42.89 seconds
Started Apr 28 12:23:16 PM PDT 24
Finished Apr 28 12:23:59 PM PDT 24
Peak memory 201860 kb
Host smart-24dd71e4-47a9-41c0-8bf9-5b29c326eebc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932479706 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.1932479706
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2496245165
Short name T137
Test name
Test status
Simulation time 6191662876 ps
CPU time 1.46 seconds
Started Apr 28 12:23:27 PM PDT 24
Finished Apr 28 12:23:29 PM PDT 24
Peak memory 201688 kb
Host smart-6d3728e5-dbac-43aa-9528-4896d1b6a70f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496245165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.2496245165
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.3922269716
Short name T727
Test name
Test status
Simulation time 2027147988 ps
CPU time 2.05 seconds
Started Apr 28 12:23:40 PM PDT 24
Finished Apr 28 12:23:43 PM PDT 24
Peak memory 201756 kb
Host smart-42f84b3a-55c4-4f61-bdd6-47f6fa69bb24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922269716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.3922269716
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3641499061
Short name T779
Test name
Test status
Simulation time 3215596908 ps
CPU time 5.72 seconds
Started Apr 28 12:23:43 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 201768 kb
Host smart-550f5f65-3787-4c03-8da8-156174a902ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641499061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.3
641499061
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.22732424
Short name T722
Test name
Test status
Simulation time 67753676919 ps
CPU time 19.63 seconds
Started Apr 28 12:23:32 PM PDT 24
Finished Apr 28 12:23:52 PM PDT 24
Peak memory 201832 kb
Host smart-b65aa6db-78ef-4960-b313-47add600f3ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22732424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctr
l_combo_detect.22732424
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3811741777
Short name T103
Test name
Test status
Simulation time 2745449346 ps
CPU time 7.43 seconds
Started Apr 28 12:23:49 PM PDT 24
Finished Apr 28 12:23:58 PM PDT 24
Peak memory 201740 kb
Host smart-fc6e4e8c-eda1-4239-8308-fd99b0e1bcdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811741777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.3811741777
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.4114934230
Short name T428
Test name
Test status
Simulation time 2750006048 ps
CPU time 3.23 seconds
Started Apr 28 12:23:44 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 201692 kb
Host smart-87224f34-4b23-4eb0-a81e-73d80ede21ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114934230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.4114934230
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2934664464
Short name T711
Test name
Test status
Simulation time 2713243333 ps
CPU time 1.16 seconds
Started Apr 28 12:23:46 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 201648 kb
Host smart-77b5764a-5c4d-410f-b01f-df94193c38f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934664464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.2934664464
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2318005491
Short name T158
Test name
Test status
Simulation time 2477823633 ps
CPU time 2.43 seconds
Started Apr 28 12:23:34 PM PDT 24
Finished Apr 28 12:23:37 PM PDT 24
Peak memory 201688 kb
Host smart-e5562cfb-ae87-43da-bee2-53c62a9efd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318005491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.2318005491
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2005164297
Short name T471
Test name
Test status
Simulation time 2040281825 ps
CPU time 5.88 seconds
Started Apr 28 12:23:51 PM PDT 24
Finished Apr 28 12:23:58 PM PDT 24
Peak memory 201572 kb
Host smart-0106b319-026c-4696-8783-2708f08b2f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005164297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.2005164297
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1851715745
Short name T431
Test name
Test status
Simulation time 2512935613 ps
CPU time 7.37 seconds
Started Apr 28 12:23:37 PM PDT 24
Finished Apr 28 12:23:45 PM PDT 24
Peak memory 201800 kb
Host smart-9055dbe4-87e1-46f0-b7a3-69a2b18263ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851715745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.1851715745
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.3789431193
Short name T695
Test name
Test status
Simulation time 2114636927 ps
CPU time 6.33 seconds
Started Apr 28 12:23:43 PM PDT 24
Finished Apr 28 12:23:51 PM PDT 24
Peak memory 201664 kb
Host smart-d8ab8edc-f85e-4c9f-8ca5-d18ff3b7a84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789431193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3789431193
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3815472534
Short name T423
Test name
Test status
Simulation time 65511158481 ps
CPU time 106.59 seconds
Started Apr 28 12:23:38 PM PDT 24
Finished Apr 28 12:25:26 PM PDT 24
Peak memory 210308 kb
Host smart-4f17dce0-cb78-4437-84c6-a55d42440992
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815472534 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.3815472534
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1770356147
Short name T11
Test name
Test status
Simulation time 11153048242 ps
CPU time 3.23 seconds
Started Apr 28 12:23:44 PM PDT 24
Finished Apr 28 12:23:50 PM PDT 24
Peak memory 201648 kb
Host smart-a7e07065-9f5e-4bfd-94c4-5a7f41b1570b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770356147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.1770356147
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.553734135
Short name T620
Test name
Test status
Simulation time 2035490970 ps
CPU time 2.01 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:04 PM PDT 24
Peak memory 201700 kb
Host smart-a7d6abfe-14e7-4b9f-873d-2ddcf7714fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553734135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_tes
t.553734135
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2909665750
Short name T533
Test name
Test status
Simulation time 3485831797 ps
CPU time 4.91 seconds
Started Apr 28 12:23:43 PM PDT 24
Finished Apr 28 12:23:54 PM PDT 24
Peak memory 201740 kb
Host smart-f13a5afa-5eda-49ce-b402-86cfcac7a3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909665750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.2
909665750
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.3815451814
Short name T788
Test name
Test status
Simulation time 51936237180 ps
CPU time 41.96 seconds
Started Apr 28 12:23:38 PM PDT 24
Finished Apr 28 12:24:21 PM PDT 24
Peak memory 201972 kb
Host smart-01842763-1c91-4c4b-a46a-659889aaecb7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815451814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.3815451814
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1606517538
Short name T225
Test name
Test status
Simulation time 39660188051 ps
CPU time 110.59 seconds
Started Apr 28 12:23:50 PM PDT 24
Finished Apr 28 12:25:42 PM PDT 24
Peak memory 201880 kb
Host smart-c8d70155-776e-4f0e-91e8-e3b3de960f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606517538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.1606517538
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2237047724
Short name T425
Test name
Test status
Simulation time 2883872157 ps
CPU time 2.31 seconds
Started Apr 28 12:23:43 PM PDT 24
Finished Apr 28 12:23:46 PM PDT 24
Peak memory 201688 kb
Host smart-4046c928-3ee8-4af6-837b-ebb3c8983f15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237047724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.2237047724
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.2210585028
Short name T155
Test name
Test status
Simulation time 4444409280 ps
CPU time 9.94 seconds
Started Apr 28 12:23:54 PM PDT 24
Finished Apr 28 12:24:08 PM PDT 24
Peak memory 201760 kb
Host smart-da9c9693-f0d6-4e21-b9ec-7e54d12af92f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210585028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.2210585028
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1018013218
Short name T452
Test name
Test status
Simulation time 2610483975 ps
CPU time 7.6 seconds
Started Apr 28 12:23:45 PM PDT 24
Finished Apr 28 12:23:55 PM PDT 24
Peak memory 201612 kb
Host smart-8cd76dec-35cb-4464-8360-a05f7332f712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018013218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.1018013218
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.4154941718
Short name T652
Test name
Test status
Simulation time 2485639258 ps
CPU time 2.2 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:03 PM PDT 24
Peak memory 201692 kb
Host smart-2566ccde-33bf-459d-bdbf-e6af7cbefe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154941718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.4154941718
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.4047301810
Short name T367
Test name
Test status
Simulation time 2263995358 ps
CPU time 2.26 seconds
Started Apr 28 12:23:35 PM PDT 24
Finished Apr 28 12:23:38 PM PDT 24
Peak memory 201636 kb
Host smart-8fe41c96-88fe-46f6-99da-b9fe57c85f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047301810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.4047301810
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1063551275
Short name T584
Test name
Test status
Simulation time 2515728967 ps
CPU time 3.96 seconds
Started Apr 28 12:23:42 PM PDT 24
Finished Apr 28 12:23:48 PM PDT 24
Peak memory 201768 kb
Host smart-940479f0-a3eb-4725-8553-03f304f963dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063551275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.1063551275
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.4036432541
Short name T784
Test name
Test status
Simulation time 2108142294 ps
CPU time 5.71 seconds
Started Apr 28 12:23:29 PM PDT 24
Finished Apr 28 12:23:36 PM PDT 24
Peak memory 201348 kb
Host smart-930384b4-be2e-4292-8897-674ed7f427e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036432541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.4036432541
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.2645307681
Short name T148
Test name
Test status
Simulation time 8724820320 ps
CPU time 21.92 seconds
Started Apr 28 12:23:50 PM PDT 24
Finished Apr 28 12:24:13 PM PDT 24
Peak memory 201664 kb
Host smart-412ba3bf-839f-4fa3-bec9-10c7d082d5c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645307681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.2645307681
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2923877297
Short name T146
Test name
Test status
Simulation time 72772261432 ps
CPU time 48.68 seconds
Started Apr 28 12:23:43 PM PDT 24
Finished Apr 28 12:24:34 PM PDT 24
Peak memory 218524 kb
Host smart-3ed8c0bf-9213-481e-b3d7-9747b7ee51a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923877297 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.2923877297
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.126499906
Short name T281
Test name
Test status
Simulation time 4574371719 ps
CPU time 6.48 seconds
Started Apr 28 12:23:56 PM PDT 24
Finished Apr 28 12:24:08 PM PDT 24
Peak memory 201756 kb
Host smart-86f4e94f-4d84-452c-8019-60ccb1a9cdc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126499906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_ultra_low_pwr.126499906
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.1943176810
Short name T556
Test name
Test status
Simulation time 2011175253 ps
CPU time 5.76 seconds
Started Apr 28 12:22:09 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 201536 kb
Host smart-c71a678f-9e1a-4166-9510-8cc78ab9553d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943176810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.1943176810
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1380837083
Short name T566
Test name
Test status
Simulation time 3789235512 ps
CPU time 11.35 seconds
Started Apr 28 12:19:17 PM PDT 24
Finished Apr 28 12:19:29 PM PDT 24
Peak memory 201816 kb
Host smart-06d30dd1-525d-4f38-9b36-eec5c27aa97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380837083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.1380837083
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3099996391
Short name T315
Test name
Test status
Simulation time 98568037436 ps
CPU time 242.87 seconds
Started Apr 28 12:22:49 PM PDT 24
Finished Apr 28 12:27:04 PM PDT 24
Peak memory 201904 kb
Host smart-4b68080e-f258-4f4e-9cd9-2e343163e9cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099996391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.3099996391
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1163655273
Short name T635
Test name
Test status
Simulation time 3787732412 ps
CPU time 3.07 seconds
Started Apr 28 12:19:10 PM PDT 24
Finished Apr 28 12:19:13 PM PDT 24
Peak memory 201740 kb
Host smart-5a065b39-0c15-4099-a387-cf8c93b9fc3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163655273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.1163655273
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.1495254235
Short name T145
Test name
Test status
Simulation time 3697248366 ps
CPU time 3.11 seconds
Started Apr 28 12:19:15 PM PDT 24
Finished Apr 28 12:19:19 PM PDT 24
Peak memory 201808 kb
Host smart-bedfcb29-4af7-443d-a060-21809d4abf98
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495254235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.1495254235
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3019595886
Short name T496
Test name
Test status
Simulation time 2726621131 ps
CPU time 1.13 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 201544 kb
Host smart-351204bd-2e64-45db-be47-bd9dc0fd96bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019595886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.3019595886
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.4157788344
Short name T462
Test name
Test status
Simulation time 2472171666 ps
CPU time 6.95 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:23:05 PM PDT 24
Peak memory 201684 kb
Host smart-fddb2a2d-8c7a-4b9c-89a5-3671ce7e9eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157788344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.4157788344
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.217070959
Short name T403
Test name
Test status
Simulation time 2207911599 ps
CPU time 6.57 seconds
Started Apr 28 12:19:06 PM PDT 24
Finished Apr 28 12:19:13 PM PDT 24
Peak memory 201736 kb
Host smart-7e58052d-57e6-4f1c-adef-33ccbc99f07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217070959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.217070959
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.805064229
Short name T511
Test name
Test status
Simulation time 2511962262 ps
CPU time 7.29 seconds
Started Apr 28 12:19:09 PM PDT 24
Finished Apr 28 12:19:16 PM PDT 24
Peak memory 201504 kb
Host smart-9b03d208-e385-4f84-b42d-b5be5747c7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805064229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.805064229
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.3579578420
Short name T125
Test name
Test status
Simulation time 2115212292 ps
CPU time 3.46 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:23:01 PM PDT 24
Peak memory 201584 kb
Host smart-dbee2b92-474f-4e6f-9535-bc407bdd83e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579578420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.3579578420
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.3027533849
Short name T156
Test name
Test status
Simulation time 1128426758449 ps
CPU time 2124.16 seconds
Started Apr 28 12:19:20 PM PDT 24
Finished Apr 28 12:54:45 PM PDT 24
Peak memory 201760 kb
Host smart-5bea81c4-b9e5-4c64-8d92-96ac660d9d45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027533849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.3027533849
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3923356381
Short name T71
Test name
Test status
Simulation time 6898054443 ps
CPU time 2.24 seconds
Started Apr 28 12:22:57 PM PDT 24
Finished Apr 28 12:23:09 PM PDT 24
Peak memory 201752 kb
Host smart-30c99c3a-1611-4245-8489-e4657fcf1140
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923356381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.3923356381
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1671964999
Short name T606
Test name
Test status
Simulation time 59646414109 ps
CPU time 152.69 seconds
Started Apr 28 12:23:46 PM PDT 24
Finished Apr 28 12:26:22 PM PDT 24
Peak memory 201900 kb
Host smart-fcb4c877-1009-4ba4-9aa9-c01acbb7b718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671964999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.1671964999
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1738541100
Short name T748
Test name
Test status
Simulation time 57983197783 ps
CPU time 41.14 seconds
Started Apr 28 12:23:45 PM PDT 24
Finished Apr 28 12:24:29 PM PDT 24
Peak memory 201996 kb
Host smart-bbbe3a3a-6986-4e5d-b704-2a8e8c58e46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738541100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.1738541100
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2041927901
Short name T759
Test name
Test status
Simulation time 27080442739 ps
CPU time 69.2 seconds
Started Apr 28 12:23:38 PM PDT 24
Finished Apr 28 12:24:47 PM PDT 24
Peak memory 201924 kb
Host smart-3655adf9-7cb6-47fb-a80d-af5744b3ef4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041927901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_w
ith_pre_cond.2041927901
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.30560089
Short name T349
Test name
Test status
Simulation time 34207192050 ps
CPU time 99.74 seconds
Started Apr 28 12:24:10 PM PDT 24
Finished Apr 28 12:25:51 PM PDT 24
Peak memory 201836 kb
Host smart-510e7039-3b3f-4724-a32d-265ea85a117b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30560089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_wit
h_pre_cond.30560089
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1046694392
Short name T30
Test name
Test status
Simulation time 44863754475 ps
CPU time 109.63 seconds
Started Apr 28 12:23:43 PM PDT 24
Finished Apr 28 12:25:34 PM PDT 24
Peak memory 201912 kb
Host smart-caff17d7-9cd2-4a22-a4b1-5ca80f5df2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046694392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.1046694392
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.479967762
Short name T94
Test name
Test status
Simulation time 42015020956 ps
CPU time 30.12 seconds
Started Apr 28 12:23:43 PM PDT 24
Finished Apr 28 12:24:15 PM PDT 24
Peak memory 201820 kb
Host smart-7a123c49-3b69-448d-8714-7a6f6f9c6462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479967762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_wi
th_pre_cond.479967762
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3949520802
Short name T219
Test name
Test status
Simulation time 42769414298 ps
CPU time 52.96 seconds
Started Apr 28 12:23:35 PM PDT 24
Finished Apr 28 12:24:28 PM PDT 24
Peak memory 201968 kb
Host smart-ed8bc180-c7a6-4486-9e5e-0e6e46275c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949520802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.3949520802
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.2748527514
Short name T648
Test name
Test status
Simulation time 2030544449 ps
CPU time 2.01 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:00 PM PDT 24
Peak memory 200432 kb
Host smart-68ccbeb2-5e14-4cf8-a2c7-31475b90e80e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748527514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.2748527514
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3239089317
Short name T129
Test name
Test status
Simulation time 3368674322 ps
CPU time 9.34 seconds
Started Apr 28 12:22:53 PM PDT 24
Finished Apr 28 12:23:13 PM PDT 24
Peak memory 201420 kb
Host smart-3e5a2265-1f5b-4aec-8f5f-5f88b5793379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239089317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.3239089317
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.785915584
Short name T715
Test name
Test status
Simulation time 66756153940 ps
CPU time 183.72 seconds
Started Apr 28 12:19:26 PM PDT 24
Finished Apr 28 12:22:30 PM PDT 24
Peak memory 201976 kb
Host smart-c2e26dcd-0ffc-42bc-9330-f14f5e40a016
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785915584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_combo_detect.785915584
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2977599550
Short name T399
Test name
Test status
Simulation time 4653876967 ps
CPU time 1.82 seconds
Started Apr 28 12:19:30 PM PDT 24
Finished Apr 28 12:19:32 PM PDT 24
Peak memory 201756 kb
Host smart-eda2ce5f-20a8-48df-bb19-623e63a66ffd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977599550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.2977599550
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1778589650
Short name T10
Test name
Test status
Simulation time 2875532992 ps
CPU time 2.86 seconds
Started Apr 28 12:19:20 PM PDT 24
Finished Apr 28 12:19:24 PM PDT 24
Peak memory 201764 kb
Host smart-cb663585-d871-4ee4-90ae-850d0f6ba826
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778589650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.1778589650
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3119637700
Short name T52
Test name
Test status
Simulation time 2626944718 ps
CPU time 2.44 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:00 PM PDT 24
Peak memory 199844 kb
Host smart-e77de69b-a1cb-4002-b19c-8055c947393b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119637700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.3119637700
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2565117708
Short name T781
Test name
Test status
Simulation time 2530477597 ps
CPU time 1.31 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 201456 kb
Host smart-72a4ef49-3d06-4271-b840-933528364439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565117708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.2565117708
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2494158491
Short name T416
Test name
Test status
Simulation time 2097359205 ps
CPU time 3.28 seconds
Started Apr 28 12:22:48 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 201388 kb
Host smart-d550cd18-4090-447b-8a28-5b2da268f259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494158491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.2494158491
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2249612227
Short name T284
Test name
Test status
Simulation time 2508441140 ps
CPU time 6.98 seconds
Started Apr 28 12:21:54 PM PDT 24
Finished Apr 28 12:22:05 PM PDT 24
Peak memory 201440 kb
Host smart-3d118886-92d7-41ba-8d7a-3ee00aff4b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249612227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.2249612227
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.3578127523
Short name T720
Test name
Test status
Simulation time 2126125748 ps
CPU time 2.17 seconds
Started Apr 28 12:22:43 PM PDT 24
Finished Apr 28 12:22:51 PM PDT 24
Peak memory 200804 kb
Host smart-d746a869-f1d9-416c-b953-a6a6b955132b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578127523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.3578127523
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.1384013049
Short name T472
Test name
Test status
Simulation time 90749376505 ps
CPU time 58.75 seconds
Started Apr 28 12:19:28 PM PDT 24
Finished Apr 28 12:20:27 PM PDT 24
Peak memory 201888 kb
Host smart-7dcc42b9-bfe9-4425-bb8c-65b5c2392427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384013049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.1384013049
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1462745307
Short name T561
Test name
Test status
Simulation time 4816290055 ps
CPU time 6.57 seconds
Started Apr 28 12:19:26 PM PDT 24
Finished Apr 28 12:19:33 PM PDT 24
Peak memory 201760 kb
Host smart-da6da237-76bb-4235-8971-01b736660ecb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462745307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.1462745307
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.4204603422
Short name T353
Test name
Test status
Simulation time 74418400608 ps
CPU time 50.07 seconds
Started Apr 28 12:23:50 PM PDT 24
Finished Apr 28 12:24:42 PM PDT 24
Peak memory 201796 kb
Host smart-ad453213-1320-4c4b-88d5-cbba16b50daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204603422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.4204603422
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.3982382793
Short name T532
Test name
Test status
Simulation time 82820637643 ps
CPU time 54.34 seconds
Started Apr 28 12:23:40 PM PDT 24
Finished Apr 28 12:24:35 PM PDT 24
Peak memory 201840 kb
Host smart-485e2e9d-868e-4fc7-85a9-44889df0614c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982382793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.3982382793
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3771184716
Short name T786
Test name
Test status
Simulation time 115079942057 ps
CPU time 299.84 seconds
Started Apr 28 12:23:45 PM PDT 24
Finished Apr 28 12:28:48 PM PDT 24
Peak memory 201856 kb
Host smart-db9ff57e-8ec5-404a-9913-d364365f4a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771184716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.3771184716
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1452740063
Short name T741
Test name
Test status
Simulation time 67576451437 ps
CPU time 177.02 seconds
Started Apr 28 12:23:50 PM PDT 24
Finished Apr 28 12:26:49 PM PDT 24
Peak memory 201924 kb
Host smart-0e958821-499a-447c-9d37-002136de1211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452740063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.1452740063
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.4128080445
Short name T128
Test name
Test status
Simulation time 100510185362 ps
CPU time 64.85 seconds
Started Apr 28 12:23:42 PM PDT 24
Finished Apr 28 12:24:49 PM PDT 24
Peak memory 202016 kb
Host smart-2fd09c47-83e6-4d91-a31c-456bcc07e7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128080445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.4128080445
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1888511850
Short name T520
Test name
Test status
Simulation time 49859827109 ps
CPU time 31.76 seconds
Started Apr 28 12:24:44 PM PDT 24
Finished Apr 28 12:25:17 PM PDT 24
Peak memory 199724 kb
Host smart-7d1bdf39-8efd-44f1-bdfb-2403d9b3461c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888511850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.1888511850
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2254605216
Short name T79
Test name
Test status
Simulation time 76548668790 ps
CPU time 104.93 seconds
Started Apr 28 12:23:39 PM PDT 24
Finished Apr 28 12:25:25 PM PDT 24
Peak memory 201860 kb
Host smart-e274d230-b624-4bfd-951d-e8d965db6c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254605216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.2254605216
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.309806754
Short name T538
Test name
Test status
Simulation time 42315021268 ps
CPU time 24.17 seconds
Started Apr 28 12:23:49 PM PDT 24
Finished Apr 28 12:24:15 PM PDT 24
Peak memory 201896 kb
Host smart-d1a35c37-f8d6-4807-9b9b-c73b30a35e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309806754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_wi
th_pre_cond.309806754
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.2866804933
Short name T391
Test name
Test status
Simulation time 2042711621 ps
CPU time 2.23 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 201716 kb
Host smart-b6b6f375-60e1-49f5-a942-738eb54af6ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866804933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.2866804933
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1280150768
Short name T266
Test name
Test status
Simulation time 3171792141 ps
CPU time 9.03 seconds
Started Apr 28 12:19:32 PM PDT 24
Finished Apr 28 12:19:42 PM PDT 24
Peak memory 201784 kb
Host smart-f0f710d1-d0f2-4270-8432-09894c28493b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280150768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.1280150768
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.2351132907
Short name T238
Test name
Test status
Simulation time 108622752087 ps
CPU time 147.89 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:25:09 PM PDT 24
Peak memory 201432 kb
Host smart-09a67eff-8c0f-4996-9762-8f2bdf2ea018
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351132907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.2351132907
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1959230710
Short name T565
Test name
Test status
Simulation time 118113760672 ps
CPU time 75.18 seconds
Started Apr 28 12:22:46 PM PDT 24
Finished Apr 28 12:24:11 PM PDT 24
Peak memory 201844 kb
Host smart-c2047f0a-419b-41be-87fc-98d23f34b19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959230710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.1959230710
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.3583381011
Short name T108
Test name
Test status
Simulation time 3213569546 ps
CPU time 3.65 seconds
Started Apr 28 12:22:10 PM PDT 24
Finished Apr 28 12:22:16 PM PDT 24
Peak memory 201500 kb
Host smart-56abdad3-fe08-4253-b9ac-64c608f8f02b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583381011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.3583381011
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2256248776
Short name T364
Test name
Test status
Simulation time 2609518386 ps
CPU time 7.54 seconds
Started Apr 28 12:20:42 PM PDT 24
Finished Apr 28 12:20:51 PM PDT 24
Peak memory 201788 kb
Host smart-a9e11f5c-9081-420c-9846-2c4a12a8fad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256248776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.2256248776
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3045670192
Short name T474
Test name
Test status
Simulation time 2479669494 ps
CPU time 2.5 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:43 PM PDT 24
Peak memory 200320 kb
Host smart-7fe45d07-d5ea-4d90-b403-73169f340bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045670192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.3045670192
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1836420561
Short name T465
Test name
Test status
Simulation time 2243208632 ps
CPU time 6.61 seconds
Started Apr 28 12:19:35 PM PDT 24
Finished Apr 28 12:19:43 PM PDT 24
Peak memory 201736 kb
Host smart-a3e6e6d8-e7fa-474e-959a-36df888bc1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836420561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.1836420561
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2243913101
Short name T437
Test name
Test status
Simulation time 2516204177 ps
CPU time 4.3 seconds
Started Apr 28 12:22:08 PM PDT 24
Finished Apr 28 12:22:15 PM PDT 24
Peak memory 201540 kb
Host smart-35f93a14-bc1b-4d78-ae52-c576f4894b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243913101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.2243913101
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.1772844565
Short name T453
Test name
Test status
Simulation time 2131944585 ps
CPU time 1.64 seconds
Started Apr 28 12:22:39 PM PDT 24
Finished Apr 28 12:22:46 PM PDT 24
Peak memory 200144 kb
Host smart-82f447fc-4d24-4442-881a-bac556fe1761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772844565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.1772844565
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.1977258202
Short name T91
Test name
Test status
Simulation time 239841028758 ps
CPU time 145.23 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:25:22 PM PDT 24
Peak memory 201836 kb
Host smart-af2c9e26-3603-4952-b15c-638e307855dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977258202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.1977258202
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1670056247
Short name T3
Test name
Test status
Simulation time 56192668543 ps
CPU time 149.08 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:25:10 PM PDT 24
Peak memory 216588 kb
Host smart-f1eb51f1-15b8-4539-a622-ccea42971f31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670056247 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.1670056247
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3899069910
Short name T508
Test name
Test status
Simulation time 3098168547 ps
CPU time 5.71 seconds
Started Apr 28 12:20:41 PM PDT 24
Finished Apr 28 12:20:48 PM PDT 24
Peak memory 201760 kb
Host smart-44096bf9-70c2-4d61-bac8-e6d6885c251c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899069910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ultra_low_pwr.3899069910
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1423562522
Short name T557
Test name
Test status
Simulation time 33497537187 ps
CPU time 95.13 seconds
Started Apr 28 12:23:47 PM PDT 24
Finished Apr 28 12:25:24 PM PDT 24
Peak memory 201840 kb
Host smart-8011c7a4-7e06-4258-bd40-e94d6a6f53d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423562522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.1423562522
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3040877480
Short name T793
Test name
Test status
Simulation time 68699787114 ps
CPU time 104.42 seconds
Started Apr 28 12:25:12 PM PDT 24
Finished Apr 28 12:26:58 PM PDT 24
Peak memory 201812 kb
Host smart-bcc09986-ee6d-4f1f-9c23-3e2e9c2a8e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040877480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.3040877480
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1359291900
Short name T489
Test name
Test status
Simulation time 27609534121 ps
CPU time 19.17 seconds
Started Apr 28 12:23:28 PM PDT 24
Finished Apr 28 12:23:49 PM PDT 24
Peak memory 201884 kb
Host smart-f0dc018f-a58a-4260-afbe-0242bd4021d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359291900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.1359291900
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.896008835
Short name T499
Test name
Test status
Simulation time 30083018020 ps
CPU time 22.13 seconds
Started Apr 28 12:23:44 PM PDT 24
Finished Apr 28 12:24:08 PM PDT 24
Peak memory 201852 kb
Host smart-0d5f122a-6f3d-4aa0-a580-f4b20640881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896008835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_wi
th_pre_cond.896008835
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1286690021
Short name T95
Test name
Test status
Simulation time 26864954346 ps
CPU time 16.56 seconds
Started Apr 28 12:23:39 PM PDT 24
Finished Apr 28 12:23:57 PM PDT 24
Peak memory 201900 kb
Host smart-1fd35848-938c-4b0f-9de2-635f51c16c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286690021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.1286690021
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4044618168
Short name T344
Test name
Test status
Simulation time 100292797983 ps
CPU time 268.33 seconds
Started Apr 28 12:23:38 PM PDT 24
Finished Apr 28 12:28:06 PM PDT 24
Peak memory 201856 kb
Host smart-684b2419-c209-4a44-884a-e128248caaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044618168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.4044618168
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2064415350
Short name T68
Test name
Test status
Simulation time 43633505011 ps
CPU time 96.15 seconds
Started Apr 28 12:23:48 PM PDT 24
Finished Apr 28 12:25:26 PM PDT 24
Peak memory 201976 kb
Host smart-41f25c8b-49e8-4fab-bd7a-5a4b07dad014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064415350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.2064415350
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.1764963327
Short name T51
Test name
Test status
Simulation time 2032064133 ps
CPU time 2.06 seconds
Started Apr 28 12:22:37 PM PDT 24
Finished Apr 28 12:22:45 PM PDT 24
Peak memory 200432 kb
Host smart-f5b0107f-ad81-4674-bf01-832f705ce43d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764963327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.1764963327
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1701745145
Short name T624
Test name
Test status
Simulation time 3871616345 ps
CPU time 3.15 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:22:59 PM PDT 24
Peak memory 201356 kb
Host smart-110c6a4f-1ecc-4759-bce3-feb660fea97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701745145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.1701745145
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3164108788
Short name T348
Test name
Test status
Simulation time 88627659186 ps
CPU time 51.1 seconds
Started Apr 28 12:19:40 PM PDT 24
Finished Apr 28 12:20:32 PM PDT 24
Peak memory 201968 kb
Host smart-f948ef23-1810-412b-af1f-1407e9a68103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164108788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.3164108788
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.221801657
Short name T376
Test name
Test status
Simulation time 2739629220 ps
CPU time 8.18 seconds
Started Apr 28 12:19:38 PM PDT 24
Finished Apr 28 12:19:47 PM PDT 24
Peak memory 201736 kb
Host smart-3cb9600e-a25c-4d05-98ec-94a114e2b5c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221801657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_ec_pwr_on_rst.221801657
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.3284676081
Short name T626
Test name
Test status
Simulation time 3837413824 ps
CPU time 4.3 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:23:02 PM PDT 24
Peak memory 201312 kb
Host smart-d2fce08c-d718-4902-90f2-8971fe29f3fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284676081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.3284676081
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3902103830
Short name T209
Test name
Test status
Simulation time 2627341073 ps
CPU time 2.77 seconds
Started Apr 28 12:21:59 PM PDT 24
Finished Apr 28 12:22:04 PM PDT 24
Peak memory 200608 kb
Host smart-33900261-7d40-4cdb-b849-adbf3638e639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902103830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.3902103830
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1949255796
Short name T613
Test name
Test status
Simulation time 2480936720 ps
CPU time 3.81 seconds
Started Apr 28 12:22:47 PM PDT 24
Finished Apr 28 12:23:00 PM PDT 24
Peak memory 201664 kb
Host smart-7a8211ac-3b45-4261-8f3f-13ed0e64a79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949255796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.1949255796
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.1110067920
Short name T375
Test name
Test status
Simulation time 2153325320 ps
CPU time 3.34 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:44 PM PDT 24
Peak memory 200616 kb
Host smart-0a417714-509f-4784-a7df-8b1149400231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110067920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.1110067920
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1486298697
Short name T162
Test name
Test status
Simulation time 2539963263 ps
CPU time 1.54 seconds
Started Apr 28 12:22:15 PM PDT 24
Finished Apr 28 12:22:20 PM PDT 24
Peak memory 201716 kb
Host smart-05bac707-33e8-4818-bb30-f70354982564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486298697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.1486298697
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.3245721330
Short name T706
Test name
Test status
Simulation time 2110666137 ps
CPU time 5.95 seconds
Started Apr 28 12:22:36 PM PDT 24
Finished Apr 28 12:22:47 PM PDT 24
Peak memory 201176 kb
Host smart-93788600-504c-41a8-995a-d98312e6ff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245721330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.3245721330
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.1415486331
Short name T272
Test name
Test status
Simulation time 11230628070 ps
CPU time 9.43 seconds
Started Apr 28 12:22:58 PM PDT 24
Finished Apr 28 12:23:17 PM PDT 24
Peak memory 200072 kb
Host smart-5f007d85-be68-48cb-861e-0e305eee14f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415486331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.1415486331
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.661501005
Short name T719
Test name
Test status
Simulation time 5267298250 ps
CPU time 0.95 seconds
Started Apr 28 12:22:14 PM PDT 24
Finished Apr 28 12:22:18 PM PDT 24
Peak memory 201660 kb
Host smart-46a57da8-980a-43ab-8344-b67568793966
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661501005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_ultra_low_pwr.661501005
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1957286698
Short name T69
Test name
Test status
Simulation time 69348472128 ps
CPU time 12.98 seconds
Started Apr 28 12:24:45 PM PDT 24
Finished Apr 28 12:24:59 PM PDT 24
Peak memory 201464 kb
Host smart-24cc74a4-9dcf-409c-97b5-9c1d4c4c6693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957286698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.1957286698
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3193790483
Short name T229
Test name
Test status
Simulation time 25106386198 ps
CPU time 16.78 seconds
Started Apr 28 12:23:45 PM PDT 24
Finished Apr 28 12:24:05 PM PDT 24
Peak memory 201900 kb
Host smart-3c05b5a2-9b0c-4a5a-b2a0-f177f255f5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193790483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.3193790483
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.295948431
Short name T354
Test name
Test status
Simulation time 186470593768 ps
CPU time 486.15 seconds
Started Apr 28 12:23:45 PM PDT 24
Finished Apr 28 12:31:54 PM PDT 24
Peak memory 201920 kb
Host smart-a7995d8d-a94c-4a84-9b1e-12f8bb2e16c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295948431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_wi
th_pre_cond.295948431
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.565094933
Short name T217
Test name
Test status
Simulation time 116825722466 ps
CPU time 309.22 seconds
Started Apr 28 12:23:53 PM PDT 24
Finished Apr 28 12:29:05 PM PDT 24
Peak memory 201864 kb
Host smart-f729830b-1b72-492e-b979-209cd256a502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565094933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_wi
th_pre_cond.565094933
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3644392915
Short name T539
Test name
Test status
Simulation time 22085708538 ps
CPU time 25.02 seconds
Started Apr 28 12:23:50 PM PDT 24
Finished Apr 28 12:24:17 PM PDT 24
Peak memory 201856 kb
Host smart-42bd532a-07e8-4fed-ba41-8fc16cf841b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644392915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w
ith_pre_cond.3644392915
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.742543816
Short name T717
Test name
Test status
Simulation time 105732969114 ps
CPU time 73.85 seconds
Started Apr 28 12:25:14 PM PDT 24
Finished Apr 28 12:26:29 PM PDT 24
Peak memory 201872 kb
Host smart-32548a7f-ad5a-48bb-b945-d74458e33be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742543816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_wi
th_pre_cond.742543816
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3025278682
Short name T682
Test name
Test status
Simulation time 25836093675 ps
CPU time 49.4 seconds
Started Apr 28 12:23:41 PM PDT 24
Finished Apr 28 12:24:32 PM PDT 24
Peak memory 201900 kb
Host smart-bb321fd0-c558-4085-9dc9-a0f444860c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025278682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.3025278682
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3576587417
Short name T230
Test name
Test status
Simulation time 121663039555 ps
CPU time 311.62 seconds
Started Apr 28 12:23:41 PM PDT 24
Finished Apr 28 12:28:54 PM PDT 24
Peak memory 201940 kb
Host smart-ddc568b2-b6dc-42f0-87e4-cb1c3740ce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576587417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.3576587417
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.434596812
Short name T517
Test name
Test status
Simulation time 119020352132 ps
CPU time 284.85 seconds
Started Apr 28 12:24:44 PM PDT 24
Finished Apr 28 12:29:30 PM PDT 24
Peak memory 199600 kb
Host smart-6ba8a6aa-df7c-482b-813e-383cae172445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434596812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_wi
th_pre_cond.434596812
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.134250384
Short name T110
Test name
Test status
Simulation time 2158135529 ps
CPU time 0.97 seconds
Started Apr 28 12:22:58 PM PDT 24
Finished Apr 28 12:23:09 PM PDT 24
Peak memory 201808 kb
Host smart-52b085e1-37c2-466a-ac0a-07394e256fdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134250384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test
.134250384
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1099502547
Short name T662
Test name
Test status
Simulation time 3879647311 ps
CPU time 1.87 seconds
Started Apr 28 12:19:45 PM PDT 24
Finished Apr 28 12:19:49 PM PDT 24
Peak memory 201808 kb
Host smart-70ba5819-0e48-45f8-8c54-73aa6d0ca873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099502547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.1099502547
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.2306255954
Short name T750
Test name
Test status
Simulation time 81759023749 ps
CPU time 47.86 seconds
Started Apr 28 12:19:50 PM PDT 24
Finished Apr 28 12:20:39 PM PDT 24
Peak memory 201924 kb
Host smart-fa73cba9-2a28-457d-aad4-dc1edf8d22d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306255954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.2306255954
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.139254686
Short name T716
Test name
Test status
Simulation time 72426581670 ps
CPU time 48.42 seconds
Started Apr 28 12:19:54 PM PDT 24
Finished Apr 28 12:20:43 PM PDT 24
Peak memory 201988 kb
Host smart-4a1ef4cd-c0b9-4710-bd86-f08ce2c9dd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139254686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wit
h_pre_cond.139254686
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.637640917
Short name T207
Test name
Test status
Simulation time 3306272336 ps
CPU time 1.56 seconds
Started Apr 28 12:22:39 PM PDT 24
Finished Apr 28 12:22:45 PM PDT 24
Peak memory 201384 kb
Host smart-5961c3de-971c-4170-8920-4f15a8a7c176
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637640917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_ec_pwr_on_rst.637640917
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3314701630
Short name T40
Test name
Test status
Simulation time 471021878500 ps
CPU time 105.65 seconds
Started Apr 28 12:21:55 PM PDT 24
Finished Apr 28 12:23:45 PM PDT 24
Peak memory 201448 kb
Host smart-5049a5f9-6205-4287-8179-d797d07968cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314701630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.3314701630
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2665530907
Short name T721
Test name
Test status
Simulation time 2634991163 ps
CPU time 1.97 seconds
Started Apr 28 12:21:56 PM PDT 24
Finished Apr 28 12:22:02 PM PDT 24
Peak memory 200892 kb
Host smart-b6da620b-141d-4cee-a0e6-a80204d7e220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665530907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.2665530907
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3085205360
Short name T771
Test name
Test status
Simulation time 2469435555 ps
CPU time 6.16 seconds
Started Apr 28 12:22:39 PM PDT 24
Finished Apr 28 12:22:50 PM PDT 24
Peak memory 201388 kb
Host smart-55875d48-380d-4b34-8a45-15883389343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085205360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.3085205360
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.4291706891
Short name T210
Test name
Test status
Simulation time 2199971069 ps
CPU time 2.11 seconds
Started Apr 28 12:19:41 PM PDT 24
Finished Apr 28 12:19:44 PM PDT 24
Peak memory 201784 kb
Host smart-3ceacd47-7697-49d3-932a-bdc1e1305f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291706891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.4291706891
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.35717132
Short name T188
Test name
Test status
Simulation time 2519050887 ps
CPU time 3.86 seconds
Started Apr 28 12:19:45 PM PDT 24
Finished Apr 28 12:19:50 PM PDT 24
Peak memory 201800 kb
Host smart-f8de4631-e0ab-4ec1-865b-562096e3a723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35717132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.35717132
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.1829254918
Short name T755
Test name
Test status
Simulation time 2123621810 ps
CPU time 1.94 seconds
Started Apr 28 12:21:57 PM PDT 24
Finished Apr 28 12:22:02 PM PDT 24
Peak memory 200376 kb
Host smart-ff1e3143-2668-4a07-b441-d3f4153723a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829254918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.1829254918
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.1014336485
Short name T152
Test name
Test status
Simulation time 14026389295 ps
CPU time 2.88 seconds
Started Apr 28 12:19:57 PM PDT 24
Finished Apr 28 12:20:00 PM PDT 24
Peak memory 201760 kb
Host smart-4ea99870-a383-4f2a-abe2-3f57417c38ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014336485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.1014336485
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.485740668
Short name T478
Test name
Test status
Simulation time 3092246711 ps
CPU time 5.93 seconds
Started Apr 28 12:19:43 PM PDT 24
Finished Apr 28 12:19:51 PM PDT 24
Peak memory 201800 kb
Host smart-97fa29bc-6066-4deb-9926-5bca94dcd024
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485740668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_ultra_low_pwr.485740668
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1067987394
Short name T705
Test name
Test status
Simulation time 28578588622 ps
CPU time 62.99 seconds
Started Apr 28 12:23:51 PM PDT 24
Finished Apr 28 12:24:56 PM PDT 24
Peak memory 201984 kb
Host smart-3ea3ea26-4412-4cdd-b18f-53df35483c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067987394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.1067987394
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2942232309
Short name T101
Test name
Test status
Simulation time 25330579423 ps
CPU time 66.59 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:25:07 PM PDT 24
Peak memory 201916 kb
Host smart-a89b5dac-4d87-43fb-9552-25e879c09441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942232309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.2942232309
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2940594990
Short name T360
Test name
Test status
Simulation time 70877631344 ps
CPU time 20.6 seconds
Started Apr 28 12:23:50 PM PDT 24
Finished Apr 28 12:24:12 PM PDT 24
Peak memory 201912 kb
Host smart-71ea2551-3d82-48f2-89ed-b4def22b2d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940594990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.2940594990
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2161698614
Short name T610
Test name
Test status
Simulation time 26081458655 ps
CPU time 66.61 seconds
Started Apr 28 12:23:45 PM PDT 24
Finished Apr 28 12:24:55 PM PDT 24
Peak memory 201928 kb
Host smart-6a7f9db1-bff9-473b-a201-8058e6e7e11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161698614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.2161698614
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3259068708
Short name T346
Test name
Test status
Simulation time 63085090474 ps
CPU time 43.26 seconds
Started Apr 28 12:23:55 PM PDT 24
Finished Apr 28 12:24:44 PM PDT 24
Peak memory 201916 kb
Host smart-aa5a563c-4228-4575-84de-7cccdc02710d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259068708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.3259068708
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.545754461
Short name T668
Test name
Test status
Simulation time 39701203719 ps
CPU time 108.99 seconds
Started Apr 28 12:23:50 PM PDT 24
Finished Apr 28 12:25:41 PM PDT 24
Peak memory 201936 kb
Host smart-d29e416e-d12e-43a2-ac1b-f96028e8441c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545754461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_wi
th_pre_cond.545754461
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3753445646
Short name T756
Test name
Test status
Simulation time 71556098865 ps
CPU time 86.39 seconds
Started Apr 28 12:24:18 PM PDT 24
Finished Apr 28 12:25:45 PM PDT 24
Peak memory 201872 kb
Host smart-b0c91e58-fbda-47b2-8d48-723c7db536d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753445646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.3753445646
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1756510895
Short name T340
Test name
Test status
Simulation time 151386914212 ps
CPU time 217.49 seconds
Started Apr 28 12:23:57 PM PDT 24
Finished Apr 28 12:27:40 PM PDT 24
Peak memory 202036 kb
Host smart-d1c504c8-9dd7-4047-ae74-162a2b6315e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756510895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.1756510895
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest
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