Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T4,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T4,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T4,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T20
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T4,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T20
0	1	Covered	T92,T93,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T20
0	1	Covered	T1,T4,T20
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T4,T20
1	-	Covered	T1,T4,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T4,T20
DetectSt	168	Covered	T1,T4,T20
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T4,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T4,T20
DebounceSt->IdleSt	163	Covered	T1,T4,T42
DetectSt->IdleSt	186	Covered	T92,T93,T95
DetectSt->StableSt	191	Covered	T1,T4,T20
IdleSt->DebounceSt	148	Covered	T1,T4,T20
StableSt->IdleSt	206	Covered	T1,T4,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T4,T20
0	1	Covered	T1,T4,T20
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T20
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T4,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T43
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T4,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T76,T117
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T4,T20
DetectSt	-	-	-	-	1	-	-	Covered	T92,T93,T95
DetectSt	-	-	-	-	0	1	-	Covered	T1,T4,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T4,T20
StableSt	-	-	-	-	-	-	0	Covered	T1,T4,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	276	0	0
CntIncr_A	6463474	157968	0	0
CntNoWrap_A	6463474	5797684	0	0
DetectStDropOut_A	6463474	3	0	0
DetectedOut_A	6463474	792	0	0
DetectedPulseOut_A	6463474	125	0	0
DisabledIdleSt_A	6463474	5633573	0	0
DisabledNoDetection_A	6463474	5635862	0	0
EnterDebounceSt_A	6463474	155	0	0
EnterDetectSt_A	6463474	128	0	0
EnterStableSt_A	6463474	125	0	0
PulseIsPulse_A	6463474	125	0	0
StayInStableSt	6463474	667	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6463474	6941	0	0
gen_low_level_sva.LowLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	125	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	276	0	0
T1	13100	4	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	3	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T20	0	2	0	0
T35	0	4	0	0
T36	0	4	0	0
T39	0	4	0	0
T42	0	1	0	0
T77	0	2	0	0
T78	0	4	0	0
T79	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	157968	0	0
T1	13100	390	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	103	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T20	0	34	0	0
T28	0	27488	0	0
T35	0	150	0	0
T36	0	140	0	0
T39	0	183	0	0
T42	0	18	0	0
T77	0	36	0	0
T78	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797684	0	0
T1	13100	4845	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	335	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	3	0	0
T92	3108	1	0	0
T93	0	1	0	0
T95	0	1	0	0
T103	422	0	0	0
T104	422	0	0	0
T105	21238	0	0	0
T106	15421	0	0	0
T107	1072	0	0	0
T108	494	0	0	0
T109	579	0	0	0
T110	13276	0	0	0
T111	667	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	792	0	0
T1	13100	17	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	10	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T20	0	2	0	0
T35	0	2	0	0
T36	0	15	0	0
T39	0	8	0	0
T66	0	24	0	0
T77	0	5	0	0
T78	0	9	0	0
T79	0	6	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	125	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	1	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T66	0	3	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5633573	0	0
T1	13100	4331	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	141	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5635862	0	0
T1	13100	4355	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	142	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	155	0	0
T1	13100	3	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	2	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T20	0	1	0	0
T28	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T42	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	128	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	1	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T66	0	3	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	125	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	1	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T66	0	3	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	125	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	1	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T66	0	3	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	667	0	0
T1	13100	15	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	9	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T20	0	1	0	0
T32	0	17	0	0
T36	0	13	0	0
T39	0	6	0	0
T66	0	21	0	0
T77	0	4	0	0
T78	0	7	0	0
T79	0	5	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	6941	0	0
T1	13100	48	0	0
T2	34899	30	0	0
T3	2173	14	0	0
T4	739	3	0	0
T5	5381	17	0	0
T6	9368	13	0	0
T12	1551	2	0	0
T13	6878	25	0	0
T14	495	7	0	0
T15	498	10	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	125	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	1	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T66	0	3	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T11,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T44
0	1	Covered	T3,T74,T75
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T44
0	1	Unreachable
1	0	Covered	T3,T11,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T11
DetectSt	168	Covered	T3,T11,T44
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T3,T11,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T44
DebounceSt->IdleSt	163	Covered	T1,T3,T42
DetectSt->IdleSt	186	Covered	T3,T74,T75
DetectSt->StableSt	191	Covered	T3,T11,T44
IdleSt->DebounceSt	148	Covered	T1,T3,T11
StableSt->IdleSt	206	Covered	T3,T11,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T11
0	1	Covered	T1,T3,T11
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T44
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T43
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T3,T28
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T3,T74,T75
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T11,T44
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	186	0	0
CntIncr_A	6463474	168174	0	0
CntNoWrap_A	6463474	5797774	0	0
DetectStDropOut_A	6463474	10	0	0
DetectedOut_A	6463474	412712	0	0
DetectedPulseOut_A	6463474	65	0	0
DisabledIdleSt_A	6463474	5140761	0	0
DisabledNoDetection_A	6463474	5143106	0	0
EnterDebounceSt_A	6463474	111	0	0
EnterDetectSt_A	6463474	75	0	0
EnterStableSt_A	6463474	65	0	0
PulseIsPulse_A	6463474	65	0	0
StayInStableSt	6463474	412647	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6463474	6941	0	0
gen_low_level_sva.LowLevelEvent_A	6463474	5800306	0	0
gen_sticky_sva.StableStDropOut_A	6463474	71684	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	186	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	17	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	2	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	4	0	0
T42	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T65	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	168174	0	0
T1	13100	82	0	0
T2	34899	0	0	0
T3	2173	639	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	31	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	220	0	0
T42	0	62	0	0
T44	0	16	0	0
T45	0	26	0	0
T48	0	49	0	0
T49	0	12	0	0
T65	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797774	0	0
T1	13100	4847	0	0
T2	34899	34416	0	0
T3	2173	1755	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	10	0	0
T3	2173	7	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	699	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T80	447	0	0	0
T118	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	412712	0	0
T3	2173	1	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	699	0	0	0
T11	0	263	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T44	0	7	0	0
T45	0	118	0	0
T48	0	316	0	0
T49	0	49	0	0
T65	0	176	0	0
T69	0	357	0	0
T80	447	0	0	0
T115	0	169	0	0
T116	0	108	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	65	0	0
T3	2173	1	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	699	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T65	0	1	0	0
T69	0	1	0	0
T80	447	0	0	0
T115	0	2	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5140761	0	0
T1	13100	4475	0	0
T2	34899	34416	0	0
T3	2173	656	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5143106	0	0
T1	13100	4501	0	0
T2	34899	34428	0	0
T3	2173	657	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	111	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	9	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	4	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T65	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	75	0	0
T3	2173	8	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	699	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T65	0	1	0	0
T69	0	1	0	0
T80	447	0	0	0
T115	0	2	0	0
T116	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	65	0	0
T3	2173	1	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	699	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T65	0	1	0	0
T69	0	1	0	0
T80	447	0	0	0
T115	0	2	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	65	0	0
T3	2173	1	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	699	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T65	0	1	0	0
T69	0	1	0	0
T80	447	0	0	0
T115	0	2	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	412647	0	0
T11	1710	262	0	0
T20	3199	0	0	0
T29	1391	0	0	0
T44	0	6	0	0
T45	0	117	0	0
T47	38246	0	0	0
T48	0	315	0	0
T49	0	48	0	0
T51	490	0	0	0
T55	525	0	0	0
T56	502	0	0	0
T65	0	175	0	0
T69	0	356	0	0
T115	0	167	0	0
T116	0	107	0	0
T119	0	310	0	0
T120	419	0	0	0
T121	444	0	0	0
T122	405	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	6941	0	0
T1	13100	48	0	0
T2	34899	30	0	0
T3	2173	14	0	0
T4	739	3	0	0
T5	5381	17	0	0
T6	9368	13	0	0
T12	1551	2	0	0
T13	6878	25	0	0
T14	495	7	0	0
T15	498	10	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	71684	0	0
T3	2173	53	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	699	0	0	0
T11	0	311	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T44	0	80	0	0
T45	0	503	0	0
T48	0	78	0	0
T49	0	333	0	0
T65	0	95	0	0
T69	0	155	0	0
T80	447	0	0	0
T115	0	60970	0	0
T116	0	97	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T3,T12
1	1	Covered	T1,T3,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T3,T12
1	1	Covered	T1,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T71,T72,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Unreachable
1	0	Covered	T1,T3,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T11
DetectSt	168	Covered	T1,T3,T11
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T11
DebounceSt->IdleSt	163	Covered	T42,T69,T115
DetectSt->IdleSt	186	Covered	T71,T72,T73
DetectSt->StableSt	191	Covered	T1,T3,T11
IdleSt->DebounceSt	148	Covered	T1,T3,T11
StableSt->IdleSt	206	Covered	T1,T3,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T11
0	1	Covered	T1,T3,T11
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T11
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T43
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T69,T115,T123
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T71,T72,T73
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	195	0	0
CntIncr_A	6463474	66910	0	0
CntNoWrap_A	6463474	5797765	0	0
DetectStDropOut_A	6463474	11	0	0
DetectedOut_A	6463474	10255	0	0
DetectedPulseOut_A	6463474	55	0	0
DisabledIdleSt_A	6463474	5140761	0	0
DisabledNoDetection_A	6463474	5143106	0	0
EnterDebounceSt_A	6463474	129	0	0
EnterDetectSt_A	6463474	66	0	0
EnterStableSt_A	6463474	55	0	0
PulseIsPulse_A	6463474	55	0	0
StayInStableSt	6463474	10200	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_sticky_sva.StableStDropOut_A	6463474	454147	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	195	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	4	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	2	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T42	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T65	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	66910	0	0
T1	13100	82	0	0
T2	34899	0	0	0
T3	2173	40	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	70	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	76	0	0
T42	0	61	0	0
T44	0	36	0	0
T45	0	96	0	0
T48	0	72	0	0
T49	0	66	0	0
T65	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797765	0	0
T1	13100	4847	0	0
T2	34899	34416	0	0
T3	2173	1768	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	11	0	0
T71	10347	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T124	0	1	0	0
T125	0	5	0	0
T126	636	0	0	0
T127	568	0	0	0
T128	422	0	0	0
T129	876	0	0	0
T130	17789	0	0	0
T131	426	0	0	0
T132	498	0	0	0
T133	5316	0	0	0
T134	125983	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	10255	0	0
T1	13100	169	0	0
T2	34899	0	0	0
T3	2173	209	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	457	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	288	0	0
T30	0	181	0	0
T44	0	23	0	0
T45	0	476	0	0
T48	0	228	0	0
T49	0	259	0	0
T65	0	95	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	55	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	2	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T65	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5140761	0	0
T1	13100	4475	0	0
T2	34899	34416	0	0
T3	2173	656	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5143106	0	0
T1	13100	4501	0	0
T2	34899	34428	0	0
T3	2173	657	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	129	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	2	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T65	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	66	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	2	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T65	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	55	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	2	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T65	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	55	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	2	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T65	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	10200	0	0
T1	13100	168	0	0
T2	34899	0	0	0
T3	2173	207	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	456	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	287	0	0
T30	0	180	0	0
T44	0	22	0	0
T45	0	475	0	0
T48	0	227	0	0
T49	0	258	0	0
T65	0	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	454147	0	0
T1	13100	109	0	0
T2	34899	0	0	0
T3	2173	819	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	83	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	244	0	0
T30	0	97	0	0
T44	0	49	0	0
T45	0	80	0	0
T48	0	138	0	0
T49	0	69	0	0
T65	0	160	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T44,T48,T69
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Unreachable
1	0	Covered	T1,T3,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T11
DetectSt	168	Covered	T1,T3,T11
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T11
DebounceSt->IdleSt	163	Covered	T48,T42,T49
DetectSt->IdleSt	186	Covered	T44,T48,T69
DetectSt->StableSt	191	Covered	T1,T3,T11
IdleSt->DebounceSt	148	Covered	T1,T3,T11
StableSt->IdleSt	206	Covered	T1,T3,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T11
0	1	Covered	T1,T3,T11
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T11
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T43
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T49,T65
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T44,T48,T69
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	214	0	0
CntIncr_A	6463474	7670	0	0
CntNoWrap_A	6463474	5797746	0	0
DetectStDropOut_A	6463474	24	0	0
DetectedOut_A	6463474	11261	0	0
DetectedPulseOut_A	6463474	58	0	0
DisabledIdleSt_A	6463474	5140761	0	0
DisabledNoDetection_A	6463474	5143106	0	0
EnterDebounceSt_A	6463474	132	0	0
EnterDetectSt_A	6463474	82	0	0
EnterStableSt_A	6463474	58	0	0
PulseIsPulse_A	6463474	58	0	0
StayInStableSt	6463474	11203	0	0
gen_high_event_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_sticky_sva.StableStDropOut_A	6463474	632634	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	214	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	4	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	2	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	4	0	0
T42	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T48	0	7	0	0
T49	0	3	0	0
T65	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	7670	0	0
T1	13100	52	0	0
T2	34899	0	0	0
T3	2173	178	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	76	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	128	0	0
T42	0	65	0	0
T44	0	86	0	0
T45	0	44	0	0
T48	0	184	0	0
T49	0	68	0	0
T65	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797746	0	0
T1	13100	4847	0	0
T2	34899	34416	0	0
T3	2173	1768	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	24	0	0
T38	27369	0	0	0
T39	737	0	0	0
T44	1427	1	0	0
T45	1105	0	0	0
T48	1476	2	0	0
T69	0	3	0	0
T73	0	2	0	0
T74	0	1	0	0
T123	0	2	0	0
T135	0	4	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	522	0	0	0
T140	439	0	0	0
T141	402	0	0	0
T142	522	0	0	0
T143	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	11261	0	0
T1	13100	156	0	0
T2	34899	0	0	0
T3	2173	825	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	424	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T30	0	97	0	0
T45	0	140	0	0
T48	0	1	0	0
T49	0	36	0	0
T114	0	229	0	0
T115	0	273	0	0
T116	0	52	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	58	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	2	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5140761	0	0
T1	13100	4475	0	0
T2	34899	34416	0	0
T3	2173	656	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5143106	0	0
T1	13100	4501	0	0
T2	34899	34428	0	0
T3	2173	657	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	132	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	2	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	4	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	4	0	0
T49	0	2	0	0
T65	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	82	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	2	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T30	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	3	0	0
T49	0	1	0	0
T69	0	3	0	0
T114	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	58	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	2	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	58	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	2	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	11203	0	0
T1	13100	155	0	0
T2	34899	0	0	0
T3	2173	823	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	423	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T30	0	96	0	0
T45	0	139	0	0
T49	0	35	0	0
T114	0	228	0	0
T115	0	271	0	0
T116	0	51	0	0
T119	0	154	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	632634	0	0
T1	13100	160	0	0
T2	34899	0	0	0
T3	2173	99	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T11	0	121	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T30	0	191	0	0
T45	0	470	0	0
T48	0	75	0	0
T49	0	212	0	0
T114	0	291	0	0
T115	0	60900	0	0
T116	0	161	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T42,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T42,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T28,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T60,T42
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T42,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T33
0	1	Covered	T1,T28,T32
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T28,T33
1	-	Covered	T1,T28,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T42,T28
DetectSt	168	Covered	T1,T28,T33
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T28,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T28,T33
DebounceSt->IdleSt	163	Covered	T1,T42,T144
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T28,T33
IdleSt->DebounceSt	148	Covered	T1,T42,T28
StableSt->IdleSt	206	Covered	T1,T28,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T42,T28
0	1	Covered	T1,T42,T28
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T28,T33
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T42,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T28,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T144,T145
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T42,T28
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T28,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T28,T32
StableSt	-	-	-	-	-	-	0	Covered	T1,T28,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	96	0	0
CntIncr_A	6463474	201181	0	0
CntNoWrap_A	6463474	5797864	0	0
DetectStDropOut_A	6463474	0	0	0
DetectedOut_A	6463474	122848	0	0
DetectedPulseOut_A	6463474	46	0	0
DisabledIdleSt_A	6463474	4987786	0	0
DisabledNoDetection_A	6463474	4990076	0	0
EnterDebounceSt_A	6463474	50	0	0
EnterDetectSt_A	6463474	46	0	0
EnterStableSt_A	6463474	46	0	0
PulseIsPulse_A	6463474	46	0	0
StayInStableSt	6463474	122776	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	96	0	0
T1	13100	5	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T32	0	4	0	0
T33	0	2	0	0
T42	0	1	0	0
T146	0	2	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	201181	0	0
T1	13100	193	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	56286	0	0
T32	0	158	0	0
T33	0	69	0	0
T42	0	25	0	0
T146	0	92	0	0
T147	0	144	0	0
T148	0	27	0	0
T149	0	92	0	0
T150	0	93	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797864	0	0
T1	13100	4844	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	122848	0	0
T1	13100	169	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	119638	0	0
T32	0	295	0	0
T33	0	39	0	0
T68	0	162	0	0
T146	0	41	0	0
T147	0	200	0	0
T148	0	7	0	0
T149	0	41	0	0
T150	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	46	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	0	2	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	4987786	0	0
T1	13100	3902	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	4990076	0	0
T1	13100	3926	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	50	0	0
T1	13100	3	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T42	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	46	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	0	2	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	46	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	0	2	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	46	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T68	0	2	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	122776	0	0
T1	13100	166	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	119637	0	0
T32	0	292	0	0
T33	0	37	0	0
T68	0	158	0	0
T146	0	39	0	0
T147	0	198	0	0
T148	0	6	0	0
T149	0	39	0	0
T150	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	19	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T32	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T42,T30,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T42,T30,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T30,T31,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T60,T42,T30
1	0	Covered	T1,T2,T12
1	1	Covered	T42,T30,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T126,T151
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T31,T155,T146
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T32
1	-	Covered	T31,T155,T146

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T42,T30,T31
DetectSt	168	Covered	T30,T31,T32
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T30,T31,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T30,T31,T32
DebounceSt->IdleSt	163	Covered	T42,T69,T123
DetectSt->IdleSt	186	Covered	T126,T151
DetectSt->StableSt	191	Covered	T30,T31,T32
IdleSt->DebounceSt	148	Covered	T42,T30,T31
StableSt->IdleSt	206	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T42,T30,T31
0	1	Covered	T42,T30,T31
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T42,T30,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42
DebounceSt	-	0	1	1	-	-	-	Covered	T30,T31,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T69,T123,T73
DebounceSt	-	0	0	-	-	-	-	Covered	T42,T30,T31
DetectSt	-	-	-	-	1	-	-	Covered	T126,T151
DetectSt	-	-	-	-	0	1	-	Covered	T30,T31,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T155,T146
StableSt	-	-	-	-	-	-	0	Covered	T30,T31,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	133	0	0
CntIncr_A	6463474	197387	0	0
CntNoWrap_A	6463474	5797827	0	0
DetectStDropOut_A	6463474	2	0	0
DetectedOut_A	6463474	238339	0	0
DetectedPulseOut_A	6463474	61	0	0
DisabledIdleSt_A	6463474	5141307	0	0
DisabledNoDetection_A	6463474	5143598	0	0
EnterDebounceSt_A	6463474	71	0	0
EnterDetectSt_A	6463474	63	0	0
EnterStableSt_A	6463474	61	0	0
PulseIsPulse_A	6463474	61	0	0
StayInStableSt	6463474	238254	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6463474	2767	0	0
gen_low_level_sva.LowLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	133	0	0
T26	23121	0	0	0
T30	0	2	0	0
T31	0	4	0	0
T32	0	2	0	0
T42	6802	1	0	0
T49	980	0	0	0
T62	7746	0	0	0
T65	1156	0	0	0
T67	0	2	0	0
T68	0	2	0	0
T70	0	2	0	0
T146	0	2	0	0
T150	0	4	0	0
T155	0	2	0	0
T156	412	0	0	0
T157	424	0	0	0
T158	8473	0	0	0
T159	1267	0	0	0
T160	4414	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	197387	0	0
T26	23121	0	0	0
T30	0	59	0	0
T31	0	160	0	0
T32	0	87	0	0
T42	6802	25	0	0
T49	980	0	0	0
T62	7746	0	0	0
T65	1156	0	0	0
T67	0	89	0	0
T68	0	95	0	0
T70	0	62	0	0
T146	0	92	0	0
T150	0	186	0	0
T155	0	32	0	0
T156	412	0	0	0
T157	424	0	0	0
T158	8473	0	0	0
T159	1267	0	0	0
T160	4414	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797827	0	0
T1	13100	4849	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	2	0	0
T72	667	0	0	0
T126	636	1	0	0
T127	568	0	0	0
T128	422	0	0	0
T129	876	0	0	0
T130	17789	0	0	0
T131	426	0	0	0
T132	498	0	0	0
T133	5316	0	0	0
T134	125983	0	0	0
T151	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	238339	0	0
T30	15535	129	0	0
T31	0	190	0	0
T32	0	53	0	0
T67	0	1	0	0
T68	0	62	0	0
T70	0	41	0	0
T77	9320	0	0	0
T78	638	0	0	0
T96	492	0	0	0
T97	493	0	0	0
T98	636	0	0	0
T99	451	0	0	0
T100	414	0	0	0
T101	523	0	0	0
T102	5556	0	0	0
T144	0	107	0	0
T146	0	433	0	0
T150	0	320	0	0
T155	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	61	0	0
T30	15535	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	0	1	0	0
T77	9320	0	0	0
T78	638	0	0	0
T96	492	0	0	0
T97	493	0	0	0
T98	636	0	0	0
T99	451	0	0	0
T100	414	0	0	0
T101	523	0	0	0
T102	5556	0	0	0
T144	0	2	0	0
T146	0	1	0	0
T150	0	2	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5141307	0	0
T1	13100	4849	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5143598	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	71	0	0
T26	23121	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T42	6802	1	0	0
T49	980	0	0	0
T62	7746	0	0	0
T65	1156	0	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	0	1	0	0
T146	0	1	0	0
T150	0	2	0	0
T155	0	1	0	0
T156	412	0	0	0
T157	424	0	0	0
T158	8473	0	0	0
T159	1267	0	0	0
T160	4414	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	63	0	0
T30	15535	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	0	1	0	0
T77	9320	0	0	0
T78	638	0	0	0
T96	492	0	0	0
T97	493	0	0	0
T98	636	0	0	0
T99	451	0	0	0
T100	414	0	0	0
T101	523	0	0	0
T102	5556	0	0	0
T144	0	2	0	0
T146	0	1	0	0
T150	0	2	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	61	0	0
T30	15535	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	0	1	0	0
T77	9320	0	0	0
T78	638	0	0	0
T96	492	0	0	0
T97	493	0	0	0
T98	636	0	0	0
T99	451	0	0	0
T100	414	0	0	0
T101	523	0	0	0
T102	5556	0	0	0
T144	0	2	0	0
T146	0	1	0	0
T150	0	2	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	61	0	0
T30	15535	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	0	1	0	0
T77	9320	0	0	0
T78	638	0	0	0
T96	492	0	0	0
T97	493	0	0	0
T98	636	0	0	0
T99	451	0	0	0
T100	414	0	0	0
T101	523	0	0	0
T102	5556	0	0	0
T144	0	2	0	0
T146	0	1	0	0
T150	0	2	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	238254	0	0
T30	15535	127	0	0
T31	0	187	0	0
T32	0	51	0	0
T68	0	60	0	0
T70	0	39	0	0
T77	9320	0	0	0
T78	638	0	0	0
T96	492	0	0	0
T97	493	0	0	0
T98	636	0	0	0
T99	451	0	0	0
T100	414	0	0	0
T101	523	0	0	0
T102	5556	0	0	0
T144	0	104	0	0
T146	0	432	0	0
T150	0	317	0	0
T155	0	8	0	0
T161	0	147	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	2767	0	0
T1	13100	40	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	18	0	0
T6	9368	0	0	0
T7	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	4	0	0
T15	498	5	0	0
T19	0	4	0	0
T20	0	9	0	0
T50	0	6	0	0
T54	0	6	0	0
T80	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	36	0	0
T31	9232	1	0	0
T33	587	0	0	0
T64	5285	0	0	0
T67	0	1	0	0
T112	497	0	0	0
T113	501	0	0	0
T123	0	1	0	0
T126	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T150	0	1	0	0
T155	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	524	0	0	0
T164	523	0	0	0
T165	742	0	0	0
T166	40425	0	0	0
T167	17883	0	0	0