Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T7,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T7,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T7,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T42
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T7,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T30
0	1	Covered	T7,T126,T168
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T30
0	1	Covered	T1,T28,T30
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T28,T30
1	-	Covered	T1,T28,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T42
DetectSt	168	Covered	T1,T7,T28
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T28,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T28
DebounceSt->IdleSt	163	Covered	T42
DetectSt->IdleSt	186	Covered	T7,T126,T168
DetectSt->StableSt	191	Covered	T1,T28,T30
IdleSt->DebounceSt	148	Covered	T1,T7,T42
StableSt->IdleSt	206	Covered	T1,T28,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T42
0	1	Covered	T1,T7,T42
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T28
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T28
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T42
DetectSt	-	-	-	-	1	-	-	Covered	T7,T126,T168
DetectSt	-	-	-	-	0	1	-	Covered	T1,T28,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T28,T30
StableSt	-	-	-	-	-	-	0	Covered	T1,T28,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	121	0	0
CntIncr_A	6463474	189332	0	0
CntNoWrap_A	6463474	5797839	0	0
DetectStDropOut_A	6463474	3	0	0
DetectedOut_A	6463474	233147	0	0
DetectedPulseOut_A	6463474	57	0	0
DisabledIdleSt_A	6463474	4674721	0	0
DisabledNoDetection_A	6463474	4676997	0	0
EnterDebounceSt_A	6463474	61	0	0
EnterDetectSt_A	6463474	60	0	0
EnterStableSt_A	6463474	57	0	0
PulseIsPulse_A	6463474	57	0	0
StayInStableSt	6463474	233060	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	121	0	0
T1	13100	6	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	0	2	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	4	0	0
T30	0	4	0	0
T31	0	2	0	0
T32	0	2	0	0
T42	0	1	0	0
T146	0	2	0	0
T147	0	4	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	189332	0	0
T1	13100	193	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	0	52	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	56316	0	0
T30	0	106	0	0
T31	0	32	0	0
T32	0	87	0	0
T42	0	25	0	0
T146	0	92	0	0
T147	0	144	0	0
T165	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797839	0	0
T1	13100	4843	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	3	0	0
T7	699	1	0	0
T8	19937	0	0	0
T9	501	0	0	0
T10	23734	0	0	0
T11	1710	0	0	0
T20	3199	0	0	0
T21	19067	0	0	0
T46	785	0	0	0
T50	491	0	0	0
T54	502	0	0	0
T126	0	1	0	0
T168	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	233147	0	0
T1	13100	212	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	176190	0	0
T30	0	320	0	0
T31	0	44	0	0
T32	0	53	0	0
T68	0	62	0	0
T144	0	106	0	0
T146	0	187	0	0
T147	0	310	0	0
T165	0	173	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	57	0	0
T1	13100	3	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T68	0	1	0	0
T144	0	2	0	0
T146	0	1	0	0
T147	0	2	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	4674721	0	0
T1	13100	3902	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	4676997	0	0
T1	13100	3926	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	61	0	0
T1	13100	3	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T42	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	60	0	0
T1	13100	3	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T68	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	57	0	0
T1	13100	3	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T68	0	1	0	0
T144	0	2	0	0
T146	0	1	0	0
T147	0	2	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	57	0	0
T1	13100	3	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T68	0	1	0	0
T144	0	2	0	0
T146	0	1	0	0
T147	0	2	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	233060	0	0
T1	13100	207	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	176187	0	0
T30	0	317	0	0
T31	0	43	0	0
T32	0	51	0	0
T68	0	60	0	0
T144	0	103	0	0
T146	0	185	0	0
T147	0	307	0	0
T165	0	172	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	26	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T134	0	1	0	0
T144	0	1	0	0
T147	0	1	0	0
T161	0	1	0	0
T165	0	1	0	0
T169	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T42,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T42,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T28,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T42,T28
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T42,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T30
0	1	Covered	T67,T134
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T30
0	1	Covered	T1,T28,T30
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T28,T30
1	-	Covered	T1,T28,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T42,T28
DetectSt	168	Covered	T1,T28,T30
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T28,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T28,T30
DebounceSt->IdleSt	163	Covered	T42,T28,T68
DetectSt->IdleSt	186	Covered	T67,T134
DetectSt->StableSt	191	Covered	T1,T28,T30
IdleSt->DebounceSt	148	Covered	T1,T42,T28
StableSt->IdleSt	206	Covered	T1,T28,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T42,T28
0	1	Covered	T1,T42,T28
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T28,T30
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T42,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T28,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T68,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T42,T28
DetectSt	-	-	-	-	1	-	-	Covered	T67,T134
DetectSt	-	-	-	-	0	1	-	Covered	T1,T28,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T28,T30
StableSt	-	-	-	-	-	-	0	Covered	T1,T28,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	136	0	0
CntIncr_A	6463474	272267	0	0
CntNoWrap_A	6463474	5797824	0	0
DetectStDropOut_A	6463474	2	0	0
DetectedOut_A	6463474	99976	0	0
DetectedPulseOut_A	6463474	62	0	0
DisabledIdleSt_A	6463474	4960845	0	0
DisabledNoDetection_A	6463474	4963134	0	0
EnterDebounceSt_A	6463474	73	0	0
EnterDetectSt_A	6463474	64	0	0
EnterStableSt_A	6463474	62	0	0
PulseIsPulse_A	6463474	62	0	0
StayInStableSt	6463474	99888	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6463474	3137	0	0
gen_low_level_sva.LowLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	136	0	0
T1	13100	4	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	5	0	0
T30	0	6	0	0
T31	0	4	0	0
T32	0	4	0	0
T42	0	1	0	0
T67	0	2	0	0
T150	0	4	0	0
T155	0	2	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	272267	0	0
T1	13100	168	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	112602	0	0
T30	0	165	0	0
T31	0	64	0	0
T32	0	158	0	0
T42	0	25	0	0
T67	0	89	0	0
T150	0	186	0	0
T155	0	32	0	0
T170	0	82	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797824	0	0
T1	13100	4845	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	2	0	0
T67	635	1	0	0
T134	0	1	0	0
T147	987	0	0	0
T171	697	0	0	0
T172	519	0	0	0
T173	895	0	0	0
T174	7497	0	0	0
T175	495	0	0	0
T176	522	0	0	0
T177	1486	0	0	0
T178	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	99976	0	0
T1	13100	207	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	145	0	0
T30	0	129	0	0
T31	0	94	0	0
T32	0	125	0	0
T69	0	57	0	0
T144	0	41	0	0
T150	0	281	0	0
T155	0	81	0	0
T170	0	63	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	62	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	2	0	0
T69	0	1	0	0
T144	0	1	0	0
T150	0	2	0	0
T155	0	1	0	0
T170	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	4960845	0	0
T1	13100	4109	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	4963134	0	0
T1	13100	4134	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	73	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	3	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	2	0	0
T42	0	1	0	0
T67	0	1	0	0
T150	0	2	0	0
T155	0	1	0	0
T170	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	64	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	2	0	0
T67	0	1	0	0
T144	0	1	0	0
T150	0	2	0	0
T155	0	1	0	0
T170	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	62	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	2	0	0
T69	0	1	0	0
T144	0	1	0	0
T150	0	2	0	0
T155	0	1	0	0
T170	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	62	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	2	0	0
T69	0	1	0	0
T144	0	1	0	0
T150	0	2	0	0
T155	0	1	0	0
T170	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	99888	0	0
T1	13100	205	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	142	0	0
T30	0	125	0	0
T31	0	91	0	0
T32	0	122	0	0
T69	0	55	0	0
T144	0	40	0	0
T150	0	279	0	0
T155	0	79	0	0
T170	0	62	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	3137	0	0
T1	13100	36	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	23	0	0
T6	9368	0	0	0
T7	0	2	0	0
T12	1551	3	0	0
T13	6878	0	0	0
T14	495	7	0	0
T15	498	7	0	0
T19	0	6	0	0
T46	0	2	0	0
T50	0	4	0	0
T80	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	35	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T126	0	1	0	0
T144	0	1	0	0
T150	0	2	0	0
T170	0	1	0	0
T179	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T29,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T29,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T29,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T29,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T29,T28
0	1	Covered	T180,T181
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T29,T28
0	1	Covered	T29,T28,T30
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T29,T28
1	-	Covered	T29,T28,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T29,T42
DetectSt	168	Covered	T1,T29,T28
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T29,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T29,T28
DebounceSt->IdleSt	163	Covered	T42,T28,T134
DetectSt->IdleSt	186	Covered	T180,T181
DetectSt->StableSt	191	Covered	T1,T29,T28
IdleSt->DebounceSt	148	Covered	T1,T29,T42
StableSt->IdleSt	206	Covered	T1,T29,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T29,T42
0	1	Covered	T1,T29,T42
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T29,T28
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T29,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T29,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T28
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T29,T42
DetectSt	-	-	-	-	1	-	-	Covered	T180,T181
DetectSt	-	-	-	-	0	1	-	Covered	T1,T29,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T28,T30
StableSt	-	-	-	-	-	-	0	Covered	T1,T29,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	148	0	0
CntIncr_A	6463474	274753	0	0
CntNoWrap_A	6463474	5797812	0	0
DetectStDropOut_A	6463474	2	0	0
DetectedOut_A	6463474	72994	0	0
DetectedPulseOut_A	6463474	71	0	0
DisabledIdleSt_A	6463474	5283168	0	0
DisabledNoDetection_A	6463474	5285460	0	0
EnterDebounceSt_A	6463474	76	0	0
EnterDetectSt_A	6463474	73	0	0
EnterStableSt_A	6463474	71	0	0
PulseIsPulse_A	6463474	71	0	0
StayInStableSt	6463474	72896	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	43	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	148	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	5	0	0
T29	0	2	0	0
T30	0	2	0	0
T31	0	2	0	0
T42	0	1	0	0
T66	0	2	0	0
T70	0	2	0	0
T147	0	4	0	0
T165	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	274753	0	0
T1	13100	25	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	168858	0	0
T29	0	46	0	0
T30	0	59	0	0
T31	0	32	0	0
T42	0	26	0	0
T66	0	19	0	0
T70	0	62	0	0
T147	0	144	0	0
T165	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797812	0	0
T1	13100	4847	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	2	0	0
T180	589	1	0	0
T181	0	1	0	0
T182	4097	0	0	0
T183	500	0	0	0
T184	403	0	0	0
T185	686	0	0	0
T186	436	0	0	0
T187	427	0	0	0
T188	62108	0	0	0
T189	703	0	0	0
T190	5271	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	72994	0	0
T1	13100	128	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	63403	0	0
T29	0	32	0	0
T30	0	43	0	0
T31	0	43	0	0
T66	0	47	0	0
T68	0	63	0	0
T70	0	104	0	0
T147	0	93	0	0
T165	0	121	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	71	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T70	0	1	0	0
T147	0	2	0	0
T165	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5283168	0	0
T1	13100	4642	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5285460	0	0
T1	13100	4667	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	76	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	3	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T42	0	1	0	0
T66	0	1	0	0
T70	0	1	0	0
T147	0	2	0	0
T165	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	73	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T70	0	1	0	0
T147	0	2	0	0
T165	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	71	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T70	0	1	0	0
T147	0	2	0	0
T165	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	71	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T70	0	1	0	0
T147	0	2	0	0
T165	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	72896	0	0
T1	13100	126	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	63400	0	0
T29	0	31	0	0
T30	0	42	0	0
T31	0	42	0	0
T66	0	45	0	0
T68	0	61	0	0
T70	0	102	0	0
T147	0	91	0	0
T165	0	118	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	43	0	0
T25	13811	0	0	0
T28	0	1	0	0
T29	1391	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T56	502	0	0	0
T57	505	0	0	0
T58	527	0	0	0
T60	551	0	0	0
T73	0	1	0	0
T115	0	1	0	0
T122	405	0	0	0
T134	0	1	0	0
T147	0	2	0	0
T165	0	1	0	0
T191	0	1	0	0
T192	50513	0	0	0
T193	598	0	0	0
T194	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T5,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T5,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T5,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T28
0	1	Covered	T32
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T28
0	1	Covered	T28,T32,T155
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T28
1	-	Covered	T28,T32,T155

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T42
DetectSt	168	Covered	T1,T5,T28
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T5,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T28
DebounceSt->IdleSt	163	Covered	T42,T195
DetectSt->IdleSt	186	Covered	T32
DetectSt->StableSt	191	Covered	T1,T5,T28
IdleSt->DebounceSt	148	Covered	T1,T5,T42
StableSt->IdleSt	206	Covered	T1,T5,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T5,T42
0	1	Covered	T1,T5,T42
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T28
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T195
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T42
DetectSt	-	-	-	-	1	-	-	Covered	T32
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T32,T155
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	114	0	0
CntIncr_A	6463474	177196	0	0
CntNoWrap_A	6463474	5797846	0	0
DetectStDropOut_A	6463474	1	0	0
DetectedOut_A	6463474	65219	0	0
DetectedPulseOut_A	6463474	55	0	0
DisabledIdleSt_A	6463474	5050981	0	0
DisabledNoDetection_A	6463474	5053264	0	0
EnterDebounceSt_A	6463474	58	0	0
EnterDetectSt_A	6463474	56	0	0
EnterStableSt_A	6463474	55	0	0
PulseIsPulse_A	6463474	55	0	0
StayInStableSt	6463474	65140	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6463474	6646	0	0
gen_low_level_sva.LowLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	114	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	2	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	6	0	0
T31	0	2	0	0
T32	0	4	0	0
T33	0	2	0	0
T42	0	1	0	0
T147	0	4	0	0
T148	0	4	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	177196	0	0
T1	13100	84	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	71	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	112602	0	0
T31	0	80	0	0
T32	0	158	0	0
T33	0	69	0	0
T42	0	24	0	0
T147	0	144	0	0
T148	0	54	0	0
T155	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797846	0	0
T1	13100	4847	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1097	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	1	0	0
T32	9978	1	0	0
T196	736	0	0	0
T197	407	0	0	0
T198	411	0	0	0
T199	15389	0	0	0
T200	710	0	0	0
T201	19712	0	0	0
T202	263502	0	0	0
T203	12002	0	0	0
T204	668	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	65219	0	0
T1	13100	420	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	224	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	112	0	0
T31	0	486	0	0
T32	0	43	0	0
T33	0	38	0	0
T147	0	193	0	0
T148	0	86	0	0
T150	0	188	0	0
T155	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	55	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T147	0	2	0	0
T148	0	2	0	0
T150	0	2	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5050981	0	0
T1	13100	3902	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	698	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5053264	0	0
T1	13100	3926	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	706	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	58	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	3	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T42	0	1	0	0
T147	0	2	0	0
T148	0	2	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	56	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	3	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T147	0	2	0	0
T148	0	2	0	0
T150	0	2	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	55	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T147	0	2	0	0
T148	0	2	0	0
T150	0	2	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	55	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T147	0	2	0	0
T148	0	2	0	0
T150	0	2	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	65140	0	0
T1	13100	418	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	222	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	108	0	0
T31	0	484	0	0
T32	0	42	0	0
T33	0	36	0	0
T147	0	190	0	0
T148	0	83	0	0
T150	0	185	0	0
T155	0	81	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	6646	0	0
T1	13100	39	0	0
T2	34899	30	0	0
T3	2173	14	0	0
T4	739	0	0	0
T5	5381	21	0	0
T6	9368	12	0	0
T12	1551	2	0	0
T13	6878	26	0	0
T14	495	6	0	0
T15	498	6	0	0
T19	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	30	0	0
T28	369743	2	0	0
T30	15535	0	0	0
T32	0	1	0	0
T69	0	1	0	0
T77	9320	0	0	0
T96	492	0	0	0
T97	493	0	0	0
T98	636	0	0	0
T99	451	0	0	0
T100	414	0	0	0
T101	523	0	0	0
T102	5556	0	0	0
T115	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T155	0	1	0	0
T161	0	1	0	0
T205	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T5,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T5,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T5,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T29
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T5,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T29
0	1	Covered	T61
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T29
0	1	Covered	T1,T28,T30
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T29
1	-	Covered	T1,T28,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T29
DetectSt	168	Covered	T1,T5,T29
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T5,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T29
DebounceSt->IdleSt	163	Covered	T1,T42,T155
DetectSt->IdleSt	186	Covered	T61
DetectSt->StableSt	191	Covered	T1,T5,T29
IdleSt->DebounceSt	148	Covered	T1,T5,T29
StableSt->IdleSt	206	Covered	T1,T5,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T5,T29
0	1	Covered	T1,T5,T29
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T29
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T29
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T155,T206
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T29
DetectSt	-	-	-	-	1	-	-	Covered	T61
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T28,T30
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	140	0	0
CntIncr_A	6463474	112602	0	0
CntNoWrap_A	6463474	5797820	0	0
DetectStDropOut_A	6463474	1	0	0
DetectedOut_A	6463474	54915	0	0
DetectedPulseOut_A	6463474	65	0	0
DisabledIdleSt_A	6463474	5391623	0	0
DisabledNoDetection_A	6463474	5393912	0	0
EnterDebounceSt_A	6463474	75	0	0
EnterDetectSt_A	6463474	66	0	0
EnterStableSt_A	6463474	65	0	0
PulseIsPulse_A	6463474	65	0	0
StayInStableSt	6463474	54820	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	140	0	0
T1	13100	3	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	2	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	4	0	0
T29	0	2	0	0
T30	0	6	0	0
T31	0	2	0	0
T42	0	1	0	0
T61	0	2	0	0
T66	0	2	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	112602	0	0
T1	13100	168	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	71	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	60	0	0
T29	0	46	0	0
T30	0	165	0	0
T31	0	32	0	0
T42	0	25	0	0
T61	0	34	0	0
T66	0	19	0	0
T165	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797820	0	0
T1	13100	4846	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1097	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	1	0	0
T31	9232	0	0	0
T33	587	0	0	0
T61	521	1	0	0
T64	5285	0	0	0
T112	497	0	0	0
T113	501	0	0	0
T163	524	0	0	0
T164	523	0	0	0
T165	742	0	0	0
T166	40425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	54915	0	0
T1	13100	82	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	325	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	245	0	0
T29	0	121	0	0
T30	0	325	0	0
T31	0	204	0	0
T32	0	178	0	0
T66	0	47	0	0
T70	0	43	0	0
T165	0	156	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	65	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T30	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T66	0	1	0	0
T70	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5391623	0	0
T1	13100	4109	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	698	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5393912	0	0
T1	13100	4134	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	706	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	75	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T30	0	3	0	0
T31	0	1	0	0
T42	0	1	0	0
T61	0	1	0	0
T66	0	1	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	66	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T30	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T61	0	1	0	0
T66	0	1	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	65	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T30	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T66	0	1	0	0
T70	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	65	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T30	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T66	0	1	0	0
T70	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	54820	0	0
T1	13100	81	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	323	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	242	0	0
T29	0	119	0	0
T30	0	322	0	0
T31	0	202	0	0
T32	0	176	0	0
T66	0	45	0	0
T70	0	42	0	0
T165	0	154	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	34	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T30	0	3	0	0
T70	0	1	0	0
T115	0	1	0	0
T126	0	1	0	0
T144	0	2	0	0
T150	0	1	0	0
T155	0	1	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T42,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T42,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T28,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T60
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T42,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T31
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T31
0	1	Covered	T28,T31,T32
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T28,T31
1	-	Covered	T28,T31,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T42,T28
DetectSt	168	Covered	T1,T28,T31
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T28,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T28,T31
DebounceSt->IdleSt	163	Covered	T42,T147,T144
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T28,T31
IdleSt->DebounceSt	148	Covered	T1,T42,T28
StableSt->IdleSt	206	Covered	T1,T28,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T42,T28
0	1	Covered	T1,T42,T28
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T28,T31
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T42,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T28,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T147,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T42,T28
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T28,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T31,T32
StableSt	-	-	-	-	-	-	0	Covered	T1,T28,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	77	0	0
CntIncr_A	6463474	55922	0	0
CntNoWrap_A	6463474	5797883	0	0
DetectStDropOut_A	6463474	0	0	0
DetectedOut_A	6463474	12484	0	0
DetectedPulseOut_A	6463474	37	0	0
DisabledIdleSt_A	6463474	5124679	0	0
DisabledNoDetection_A	6463474	5126971	0	0
EnterDebounceSt_A	6463474	40	0	0
EnterDetectSt_A	6463474	37	0	0
EnterStableSt_A	6463474	37	0	0
PulseIsPulse_A	6463474	37	0	0
StayInStableSt	6463474	12430	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6463474	6260	0	0
gen_low_level_sva.LowLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	77	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T31	0	4	0	0
T32	0	4	0	0
T42	0	1	0	0
T115	0	2	0	0
T144	0	3	0	0
T146	0	2	0	0
T147	0	3	0	0
T161	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	55922	0	0
T1	13100	25	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	30	0	0
T31	0	160	0	0
T32	0	158	0	0
T42	0	25	0	0
T115	0	13	0	0
T144	0	30	0	0
T146	0	92	0	0
T147	0	144	0	0
T161	0	39	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797883	0	0
T1	13100	4847	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	12484	0	0
T1	13100	127	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	39	0	0
T31	0	87	0	0
T32	0	161	0	0
T43	0	9	0	0
T115	0	38	0	0
T144	0	65	0	0
T146	0	41	0	0
T147	0	41	0	0
T161	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	37	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T31	0	2	0	0
T32	0	2	0	0
T43	0	1	0	0
T115	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5124679	0	0
T1	13100	4642	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5126971	0	0
T1	13100	4667	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	40	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T31	0	2	0	0
T32	0	2	0	0
T42	0	1	0	0
T115	0	1	0	0
T144	0	2	0	0
T146	0	1	0	0
T147	0	2	0	0
T161	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	37	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T31	0	2	0	0
T32	0	2	0	0
T43	0	1	0	0
T115	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	37	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T31	0	2	0	0
T32	0	2	0	0
T43	0	1	0	0
T115	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	37	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T31	0	2	0	0
T32	0	2	0	0
T43	0	1	0	0
T115	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	12430	0	0
T1	13100	125	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	38	0	0
T31	0	85	0	0
T32	0	159	0	0
T43	0	8	0	0
T115	0	36	0	0
T144	0	64	0	0
T146	0	39	0	0
T147	0	40	0	0
T161	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	6260	0	0
T1	13100	40	0	0
T2	34899	34	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	22	0	0
T6	9368	16	0	0
T7	0	1	0	0
T12	1551	0	0	0
T13	6878	23	0	0
T14	495	5	0	0
T15	498	7	0	0
T19	0	3	0	0
T80	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	19	0	0
T28	369743	1	0	0
T30	15535	0	0	0
T31	0	2	0	0
T32	0	2	0	0
T77	9320	0	0	0
T96	492	0	0	0
T97	493	0	0	0
T98	636	0	0	0
T99	451	0	0	0
T100	414	0	0	0
T101	523	0	0	0
T102	5556	0	0	0
T144	0	1	0	0
T147	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T161	0	1	0	0
T179	0	1	0	0
T207	0	1	0	0