Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T5,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T5,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T5,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T5,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T28
0	1	Covered	T7,T208,T209
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T28
0	1	Covered	T1,T28,T31
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T28
1	-	Covered	T1,T28,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T7
DetectSt	168	Covered	T1,T5,T7
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T5,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T7
DebounceSt->IdleSt	163	Covered	T42,T206,T151
DetectSt->IdleSt	186	Covered	T7,T208,T209
DetectSt->StableSt	191	Covered	T1,T5,T28
IdleSt->DebounceSt	148	Covered	T1,T5,T7
StableSt->IdleSt	206	Covered	T1,T5,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T5,T7
0	1	Covered	T1,T5,T7
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T206,T151,T109
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T7
DetectSt	-	-	-	-	1	-	-	Covered	T7,T208,T209
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T28,T31
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	171	0	0
CntIncr_A	6463474	126918	0	0
CntNoWrap_A	6463474	5797789	0	0
DetectStDropOut_A	6463474	3	0	0
DetectedOut_A	6463474	91127	0	0
DetectedPulseOut_A	6463474	80	0	0
DisabledIdleSt_A	6463474	5222591	0	0
DisabledNoDetection_A	6463474	5224870	0	0
EnterDebounceSt_A	6463474	88	0	0
EnterDetectSt_A	6463474	83	0	0
EnterStableSt_A	6463474	80	0	0
PulseIsPulse_A	6463474	80	0	0
StayInStableSt	6463474	91011	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	43	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	171	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	2	0	0
T6	9368	0	0	0
T7	0	2	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	4	0	0
T31	0	4	0	0
T33	0	2	0	0
T42	0	1	0	0
T61	0	2	0	0
T66	0	4	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	126918	0	0
T1	13100	25	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	71	0	0
T6	9368	0	0	0
T7	0	52	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	56316	0	0
T31	0	64	0	0
T33	0	69	0	0
T42	0	25	0	0
T61	0	34	0	0
T66	0	80	0	0
T165	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797789	0	0
T1	13100	4847	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1097	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	3	0	0
T7	699	1	0	0
T8	19937	0	0	0
T9	501	0	0	0
T10	23734	0	0	0
T11	1710	0	0	0
T20	3199	0	0	0
T21	19067	0	0	0
T46	785	0	0	0
T50	491	0	0	0
T54	502	0	0	0
T208	0	1	0	0
T209	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	91127	0	0
T1	13100	43	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	40	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	236	0	0
T31	0	64	0	0
T32	0	248	0	0
T33	0	38	0	0
T61	0	43	0	0
T66	0	168	0	0
T155	0	154	0	0
T165	0	103	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	80	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T61	0	1	0	0
T66	0	2	0	0
T155	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5222591	0	0
T1	13100	4642	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	698	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5224870	0	0
T1	13100	4667	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	706	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	88	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T7	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T31	0	2	0	0
T33	0	1	0	0
T42	0	1	0	0
T61	0	1	0	0
T66	0	2	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	83	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T7	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T61	0	1	0	0
T66	0	2	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	80	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T61	0	1	0	0
T66	0	2	0	0
T155	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	80	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T61	0	1	0	0
T66	0	2	0	0
T155	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	91011	0	0
T1	13100	42	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	38	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	234	0	0
T31	0	61	0	0
T32	0	245	0	0
T33	0	36	0	0
T61	0	41	0	0
T66	0	165	0	0
T155	0	152	0	0
T165	0	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	43	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T66	0	1	0	0
T69	0	1	0	0
T144	0	1	0	0
T148	0	1	0	0
T161	0	1	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T7,T42,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T7,T42,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T7,T28,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T29
1	0	Covered	T1,T2,T12
1	1	Covered	T7,T42,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T28,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T28,T30
0	1	Covered	T30,T31,T32
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T28,T30
1	-	Covered	T30,T31,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T42,T28
DetectSt	168	Covered	T7,T28,T30
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T7,T28,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T28,T30
DebounceSt->IdleSt	163	Covered	T42,T153,T210
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T28,T30
IdleSt->DebounceSt	148	Covered	T7,T42,T28
StableSt->IdleSt	206	Covered	T28,T30,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T42,T28
0	1	Covered	T7,T42,T28
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T28,T30
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T42,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T28,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T153,T210,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T42,T28
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T28,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T31,T32
StableSt	-	-	-	-	-	-	0	Covered	T7,T28,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	84	0	0
CntIncr_A	6463474	251694	0	0
CntNoWrap_A	6463474	5797876	0	0
DetectStDropOut_A	6463474	0	0	0
DetectedOut_A	6463474	138109	0	0
DetectedPulseOut_A	6463474	40	0	0
DisabledIdleSt_A	6463474	4853117	0	0
DisabledNoDetection_A	6463474	4855405	0	0
EnterDebounceSt_A	6463474	44	0	0
EnterDetectSt_A	6463474	40	0	0
EnterStableSt_A	6463474	40	0	0
PulseIsPulse_A	6463474	40	0	0
StayInStableSt	6463474	138044	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6463474	6196	0	0
gen_low_level_sva.LowLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	84	0	0
T7	699	2	0	0
T8	19937	0	0	0
T9	501	0	0	0
T10	23734	0	0	0
T11	1710	0	0	0
T20	3199	0	0	0
T21	19067	0	0	0
T28	0	4	0	0
T30	0	4	0	0
T31	0	6	0	0
T32	0	2	0	0
T42	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T54	502	0	0	0
T68	0	2	0	0
T115	0	4	0	0
T148	0	2	0	0
T150	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	251694	0	0
T7	699	52	0	0
T8	19937	0	0	0
T9	501	0	0	0
T10	23734	0	0	0
T11	1710	0	0	0
T20	3199	0	0	0
T21	19067	0	0	0
T28	0	56316	0	0
T30	0	118	0	0
T31	0	192	0	0
T32	0	79	0	0
T42	0	25	0	0
T46	785	0	0	0
T50	491	0	0	0
T54	502	0	0	0
T68	0	95	0	0
T115	0	58	0	0
T148	0	27	0	0
T150	0	93	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797876	0	0
T1	13100	4849	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	138109	0	0
T7	699	184	0	0
T8	19937	0	0	0
T9	501	0	0	0
T10	23734	0	0	0
T11	1710	0	0	0
T20	3199	0	0	0
T21	19067	0	0	0
T28	0	56462	0	0
T30	0	69	0	0
T31	0	237	0	0
T32	0	120	0	0
T43	0	8	0	0
T46	785	0	0	0
T50	491	0	0	0
T54	502	0	0	0
T68	0	63	0	0
T115	0	136	0	0
T148	0	79	0	0
T150	0	413	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	40	0	0
T7	699	1	0	0
T8	19937	0	0	0
T9	501	0	0	0
T10	23734	0	0	0
T11	1710	0	0	0
T20	3199	0	0	0
T21	19067	0	0	0
T28	0	2	0	0
T30	0	2	0	0
T31	0	3	0	0
T32	0	1	0	0
T43	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T54	502	0	0	0
T68	0	1	0	0
T115	0	2	0	0
T148	0	1	0	0
T150	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	4853117	0	0
T1	13100	4849	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	698	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	4855405	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	706	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	44	0	0
T7	699	1	0	0
T8	19937	0	0	0
T9	501	0	0	0
T10	23734	0	0	0
T11	1710	0	0	0
T20	3199	0	0	0
T21	19067	0	0	0
T28	0	2	0	0
T30	0	2	0	0
T31	0	3	0	0
T32	0	1	0	0
T42	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T54	502	0	0	0
T68	0	1	0	0
T115	0	2	0	0
T148	0	1	0	0
T150	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	40	0	0
T7	699	1	0	0
T8	19937	0	0	0
T9	501	0	0	0
T10	23734	0	0	0
T11	1710	0	0	0
T20	3199	0	0	0
T21	19067	0	0	0
T28	0	2	0	0
T30	0	2	0	0
T31	0	3	0	0
T32	0	1	0	0
T43	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T54	502	0	0	0
T68	0	1	0	0
T115	0	2	0	0
T148	0	1	0	0
T150	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	40	0	0
T7	699	1	0	0
T8	19937	0	0	0
T9	501	0	0	0
T10	23734	0	0	0
T11	1710	0	0	0
T20	3199	0	0	0
T21	19067	0	0	0
T28	0	2	0	0
T30	0	2	0	0
T31	0	3	0	0
T32	0	1	0	0
T43	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T54	502	0	0	0
T68	0	1	0	0
T115	0	2	0	0
T148	0	1	0	0
T150	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	40	0	0
T7	699	1	0	0
T8	19937	0	0	0
T9	501	0	0	0
T10	23734	0	0	0
T11	1710	0	0	0
T20	3199	0	0	0
T21	19067	0	0	0
T28	0	2	0	0
T30	0	2	0	0
T31	0	3	0	0
T32	0	1	0	0
T43	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T54	502	0	0	0
T68	0	1	0	0
T115	0	2	0	0
T148	0	1	0	0
T150	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	138044	0	0
T7	699	182	0	0
T8	19937	0	0	0
T9	501	0	0	0
T10	23734	0	0	0
T11	1710	0	0	0
T20	3199	0	0	0
T21	19067	0	0	0
T28	0	56458	0	0
T30	0	67	0	0
T31	0	233	0	0
T32	0	119	0	0
T43	0	7	0	0
T46	785	0	0	0
T50	491	0	0	0
T54	502	0	0	0
T68	0	61	0	0
T115	0	132	0	0
T148	0	78	0	0
T150	0	411	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	6196	0	0
T1	13100	47	0	0
T2	34899	27	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	17	0	0
T6	9368	12	0	0
T7	0	1	0	0
T12	1551	0	0	0
T13	6878	36	0	0
T14	495	10	0	0
T15	498	6	0	0
T19	0	4	0	0
T80	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	14	0	0
T30	15535	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T77	9320	0	0	0
T78	638	0	0	0
T96	492	0	0	0
T97	493	0	0	0
T98	636	0	0	0
T99	451	0	0	0
T100	414	0	0	0
T101	523	0	0	0
T102	5556	0	0	0
T148	0	1	0	0
T181	0	2	0	0
T209	0	1	0	0
T211	0	1	0	0
T212	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T42,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T42,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T28,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T60
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T42,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T30
0	1	Covered	T70,T67,T134
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T30
0	1	Covered	T1,T28,T30
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T28,T30
1	-	Covered	T1,T28,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T42,T28
DetectSt	168	Covered	T1,T28,T30
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T28,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T28,T30
DebounceSt->IdleSt	163	Covered	T1,T42,T70
DetectSt->IdleSt	186	Covered	T70,T67,T134
DetectSt->StableSt	191	Covered	T1,T28,T30
IdleSt->DebounceSt	148	Covered	T1,T42,T28
StableSt->IdleSt	206	Covered	T1,T28,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T42,T28
0	1	Covered	T1,T42,T28
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T28,T30
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T42,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T28,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T70,T69
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T42,T28
DetectSt	-	-	-	-	1	-	-	Covered	T70,T67,T134
DetectSt	-	-	-	-	0	1	-	Covered	T1,T28,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T28,T30
StableSt	-	-	-	-	-	-	0	Covered	T1,T28,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	154	0	0
CntIncr_A	6463474	317513	0	0
CntNoWrap_A	6463474	5797806	0	0
DetectStDropOut_A	6463474	4	0	0
DetectedOut_A	6463474	186768	0	0
DetectedPulseOut_A	6463474	70	0	0
DisabledIdleSt_A	6463474	4774261	0	0
DisabledNoDetection_A	6463474	4776548	0	0
EnterDebounceSt_A	6463474	81	0	0
EnterDetectSt_A	6463474	74	0	0
EnterStableSt_A	6463474	70	0	0
PulseIsPulse_A	6463474	70	0	0
StayInStableSt	6463474	186660	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	154	0	0
T1	13100	3	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	2	0	0
T32	0	8	0	0
T33	0	2	0	0
T42	0	1	0	0
T67	0	2	0	0
T70	0	3	0	0
T148	0	2	0	0
T155	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	317513	0	0
T1	13100	109	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	56286	0	0
T30	0	47	0	0
T32	0	324	0	0
T33	0	69	0	0
T42	0	26	0	0
T67	0	89	0	0
T70	0	124	0	0
T148	0	27	0	0
T155	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797806	0	0
T1	13100	4846	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	4	0	0
T67	635	1	0	0
T70	693	1	0	0
T82	11970	0	0	0
T134	0	1	0	0
T146	1161	0	0	0
T155	617	0	0	0
T171	697	0	0	0
T172	519	0	0	0
T173	895	0	0	0
T215	0	1	0	0
T216	12169	0	0	0
T217	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	186768	0	0
T1	13100	421	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	119681	0	0
T30	0	162	0	0
T32	0	185	0	0
T33	0	39	0	0
T68	0	225	0	0
T144	0	41	0	0
T148	0	188	0	0
T150	0	170	0	0
T155	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	70	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	4	0	0
T33	0	1	0	0
T68	0	3	0	0
T144	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T155	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	4774261	0	0
T1	13100	3902	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	4776548	0	0
T1	13100	3926	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	81	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	4	0	0
T33	0	1	0	0
T42	0	1	0	0
T67	0	1	0	0
T70	0	2	0	0
T148	0	1	0	0
T155	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	74	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	4	0	0
T33	0	1	0	0
T67	0	1	0	0
T70	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T155	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	70	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	4	0	0
T33	0	1	0	0
T68	0	3	0	0
T144	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T155	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	70	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	4	0	0
T33	0	1	0	0
T68	0	3	0	0
T144	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T155	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	186660	0	0
T1	13100	420	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	119680	0	0
T30	0	161	0	0
T32	0	179	0	0
T33	0	37	0	0
T68	0	220	0	0
T144	0	39	0	0
T148	0	186	0	0
T150	0	169	0	0
T155	0	77	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	31	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T115	0	1	0	0
T150	0	1	0	0
T155	0	1	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T7,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T7,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T7,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T7,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T28
0	1	Covered	T68,T218,T219
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T28
0	1	Covered	T165,T70,T155
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T28
1	-	Covered	T165,T70,T155

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T42
DetectSt	168	Covered	T1,T7,T28
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T7,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T28
DebounceSt->IdleSt	163	Covered	T42,T115,T191
DetectSt->IdleSt	186	Covered	T68,T218,T219
DetectSt->StableSt	191	Covered	T1,T7,T28
IdleSt->DebounceSt	148	Covered	T1,T7,T42
StableSt->IdleSt	206	Covered	T1,T28,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T42
0	1	Covered	T1,T7,T42
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T28
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T115,T191,T218
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T42
DetectSt	-	-	-	-	1	-	-	Covered	T68,T218,T219
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T165,T70,T155
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	92	0	0
CntIncr_A	6463474	115246	0	0
CntNoWrap_A	6463474	5797868	0	0
DetectStDropOut_A	6463474	3	0	0
DetectedOut_A	6463474	58892	0	0
DetectedPulseOut_A	6463474	40	0	0
DisabledIdleSt_A	6463474	5265599	0	0
DisabledNoDetection_A	6463474	5267882	0	0
EnterDebounceSt_A	6463474	49	0	0
EnterDetectSt_A	6463474	43	0	0
EnterStableSt_A	6463474	40	0	0
PulseIsPulse_A	6463474	40	0	0
StayInStableSt	6463474	58831	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6463474	6269	0	0
gen_low_level_sva.LowLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	92	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	0	2	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	4	0	0
T30	0	2	0	0
T31	0	2	0	0
T42	0	1	0	0
T61	0	2	0	0
T70	0	4	0	0
T155	0	2	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	115246	0	0
T1	13100	25	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	0	52	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	56316	0	0
T30	0	47	0	0
T31	0	32	0	0
T42	0	25	0	0
T61	0	34	0	0
T70	0	124	0	0
T155	0	32	0	0
T165	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797868	0	0
T1	13100	4847	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	3	0	0
T68	38883	1	0	0
T86	5366	0	0	0
T144	632	0	0	0
T218	0	1	0	0
T219	0	1	0	0
T220	402	0	0	0
T221	797	0	0	0
T222	900	0	0	0
T223	1387	0	0	0
T224	531	0	0	0
T225	465	0	0	0
T226	960	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	58892	0	0
T1	13100	40	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	0	38	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	56462	0	0
T30	0	94	0	0
T31	0	39	0	0
T61	0	43	0	0
T70	0	84	0	0
T146	0	42	0	0
T155	0	9	0	0
T165	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	40	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T61	0	1	0	0
T70	0	2	0	0
T146	0	1	0	0
T155	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5265599	0	0
T1	13100	4642	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	698	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5267882	0	0
T1	13100	4667	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	706	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	49	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T42	0	1	0	0
T61	0	1	0	0
T70	0	2	0	0
T155	0	1	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	43	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T61	0	1	0	0
T70	0	2	0	0
T146	0	1	0	0
T155	0	1	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	40	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T61	0	1	0	0
T70	0	2	0	0
T146	0	1	0	0
T155	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	40	0	0
T1	13100	1	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	0	1	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T61	0	1	0	0
T70	0	2	0	0
T146	0	1	0	0
T155	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	58831	0	0
T1	13100	38	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	0	36	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	56458	0	0
T30	0	92	0	0
T31	0	37	0	0
T61	0	41	0	0
T70	0	81	0	0
T146	0	40	0	0
T155	0	8	0	0
T165	0	84	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	6269	0	0
T1	13100	38	0	0
T2	34899	33	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	22	0	0
T6	9368	6	0	0
T7	0	1	0	0
T12	1551	0	0	0
T13	6878	29	0	0
T14	495	3	0	0
T15	498	5	0	0
T19	0	5	0	0
T80	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	18	0	0
T66	15617	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T115	0	1	0	0
T134	0	1	0	0
T153	0	1	0	0
T155	0	1	0	0
T165	742	1	0	0
T166	40425	0	0	0
T167	17883	0	0	0
T195	0	1	0	0
T207	0	2	0	0
T212	0	1	0	0
T227	775	0	0	0
T228	427	0	0	0
T229	841	0	0	0
T230	880	0	0	0
T231	419	0	0	0
T232	4433	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T29,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T5,T29,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T29,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T29,T60
1	0	Covered	T1,T2,T4
1	1	Covered	T5,T29,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T29,T28
0	1	Covered	T182
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T29,T28
0	1	Covered	T29,T28,T165
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T29,T28
1	-	Covered	T29,T28,T165

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T29,T42
DetectSt	168	Covered	T5,T29,T28
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T5,T29,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T29,T28
DebounceSt->IdleSt	163	Covered	T42,T233
DetectSt->IdleSt	186	Covered	T182
DetectSt->StableSt	191	Covered	T5,T29,T28
IdleSt->DebounceSt	148	Covered	T5,T29,T42
StableSt->IdleSt	206	Covered	T5,T29,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T29,T42
0	1	Covered	T5,T29,T42
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T29,T28
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T29,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T29,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T233
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T29,T42
DetectSt	-	-	-	-	1	-	-	Covered	T182
DetectSt	-	-	-	-	0	1	-	Covered	T5,T29,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T28,T165
StableSt	-	-	-	-	-	-	0	Covered	T5,T29,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	134	0	0
CntIncr_A	6463474	160388	0	0
CntNoWrap_A	6463474	5797826	0	0
DetectStDropOut_A	6463474	1	0	0
DetectedOut_A	6463474	143611	0	0
DetectedPulseOut_A	6463474	65	0	0
DisabledIdleSt_A	6463474	5327834	0	0
DisabledNoDetection_A	6463474	5330128	0	0
EnterDebounceSt_A	6463474	68	0	0
EnterDetectSt_A	6463474	66	0	0
EnterStableSt_A	6463474	65	0	0
PulseIsPulse_A	6463474	65	0	0
StayInStableSt	6463474	143524	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	42	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	134	0	0
T5	5381	2	0	0
T6	9368	0	0	0
T7	699	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	0	0	0
T28	0	4	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T42	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T61	0	2	0	0
T80	447	0	0	0
T155	0	2	0	0
T165	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	160388	0	0
T5	5381	71	0	0
T6	9368	0	0	0
T7	699	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	0	0	0
T28	0	60	0	0
T29	0	46	0	0
T31	0	32	0	0
T32	0	79	0	0
T33	0	69	0	0
T42	0	25	0	0
T46	785	0	0	0
T50	491	0	0	0
T61	0	34	0	0
T80	447	0	0	0
T155	0	32	0	0
T165	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797826	0	0
T1	13100	4849	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1097	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	1	0	0
T182	4097	1	0	0
T183	500	0	0	0
T184	403	0	0	0
T185	686	0	0	0
T186	436	0	0	0
T187	427	0	0	0
T188	62108	0	0	0
T189	703	0	0	0
T190	5271	0	0	0
T234	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	143611	0	0
T5	5381	324	0	0
T6	9368	0	0	0
T7	699	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	0	0	0
T28	0	41	0	0
T29	0	31	0	0
T31	0	145	0	0
T32	0	199	0	0
T33	0	109	0	0
T46	785	0	0	0
T50	491	0	0	0
T61	0	43	0	0
T80	447	0	0	0
T146	0	301	0	0
T155	0	11	0	0
T165	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	65	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T7	699	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T61	0	1	0	0
T80	447	0	0	0
T146	0	2	0	0
T155	0	1	0	0
T165	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5327834	0	0
T1	13100	4849	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	698	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5330128	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	706	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	68	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T7	699	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T42	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T61	0	1	0	0
T80	447	0	0	0
T155	0	1	0	0
T165	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	66	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T7	699	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T61	0	1	0	0
T80	447	0	0	0
T146	0	2	0	0
T155	0	1	0	0
T165	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	65	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T7	699	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T61	0	1	0	0
T80	447	0	0	0
T146	0	2	0	0
T155	0	1	0	0
T165	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	65	0	0
T5	5381	1	0	0
T6	9368	0	0	0
T7	699	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	0	0	0
T28	0	2	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T61	0	1	0	0
T80	447	0	0	0
T146	0	2	0	0
T155	0	1	0	0
T165	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	143524	0	0
T5	5381	322	0	0
T6	9368	0	0	0
T7	699	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	0	0	0
T28	0	39	0	0
T29	0	30	0	0
T31	0	143	0	0
T32	0	198	0	0
T33	0	107	0	0
T46	785	0	0	0
T50	491	0	0	0
T61	0	41	0	0
T80	447	0	0	0
T146	0	299	0	0
T155	0	10	0	0
T165	0	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	42	0	0
T25	13811	0	0	0
T28	0	2	0	0
T29	1391	1	0	0
T32	0	1	0	0
T56	502	0	0	0
T57	505	0	0	0
T58	527	0	0	0
T60	551	0	0	0
T69	0	1	0	0
T115	0	2	0	0
T122	405	0	0	0
T146	0	2	0	0
T147	0	2	0	0
T150	0	2	0	0
T155	0	1	0	0
T165	0	2	0	0
T192	50513	0	0	0
T193	598	0	0	0
T194	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T29,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T29,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T29,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T29
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T29,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T29,T28
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T29,T28
0	1	Covered	T1,T28,T31
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T29,T28
1	-	Covered	T1,T28,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T29,T42
DetectSt	168	Covered	T1,T29,T28
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T29,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T29,T28
DebounceSt->IdleSt	163	Covered	T42,T73,T153
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T29,T28
IdleSt->DebounceSt	148	Covered	T1,T29,T42
StableSt->IdleSt	206	Covered	T1,T29,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T29,T42
0	1	Covered	T1,T29,T42
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T29,T28
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T29,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T29,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T73,T153,T181
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T29,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T29,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T28,T31
StableSt	-	-	-	-	-	-	0	Covered	T1,T29,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	88	0	0
CntIncr_A	6463474	183154	0	0
CntNoWrap_A	6463474	5797872	0	0
DetectStDropOut_A	6463474	0	0	0
DetectedOut_A	6463474	51635	0	0
DetectedPulseOut_A	6463474	42	0	0
DisabledIdleSt_A	6463474	4988858	0	0
DisabledNoDetection_A	6463474	4991148	0	0
EnterDebounceSt_A	6463474	46	0	0
EnterDetectSt_A	6463474	42	0	0
EnterStableSt_A	6463474	42	0	0
PulseIsPulse_A	6463474	42	0	0
StayInStableSt	6463474	51573	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6463474	6941	0	0
gen_low_level_sva.LowLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	88	0	0
T1	13100	4	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	8	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T42	0	1	0	0
T115	0	2	0	0
T144	0	4	0	0
T149	0	2	0	0
T165	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	183154	0	0
T1	13100	168	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	112632	0	0
T29	0	46	0	0
T31	0	80	0	0
T32	0	79	0	0
T42	0	25	0	0
T115	0	13	0	0
T144	0	30	0	0
T149	0	92	0	0
T165	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797872	0	0
T1	13100	4845	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	51635	0	0
T1	13100	81	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	297	0	0
T29	0	43	0	0
T31	0	124	0	0
T32	0	250	0	0
T43	0	10	0	0
T115	0	38	0	0
T144	0	112	0	0
T149	0	42	0	0
T165	0	99	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	42	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	4	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T43	0	1	0	0
T115	0	1	0	0
T144	0	2	0	0
T149	0	1	0	0
T165	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	4988858	0	0
T1	13100	4109	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	698	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	4991148	0	0
T1	13100	4134	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	706	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	46	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	4	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T42	0	1	0	0
T115	0	1	0	0
T144	0	2	0	0
T149	0	1	0	0
T165	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	42	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	4	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T43	0	1	0	0
T115	0	1	0	0
T144	0	2	0	0
T149	0	1	0	0
T165	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	42	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	4	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T43	0	1	0	0
T115	0	1	0	0
T144	0	2	0	0
T149	0	1	0	0
T165	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	42	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	4	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T43	0	1	0	0
T115	0	1	0	0
T144	0	2	0	0
T149	0	1	0	0
T165	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	51573	0	0
T1	13100	79	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	292	0	0
T29	0	41	0	0
T31	0	123	0	0
T32	0	248	0	0
T43	0	9	0	0
T115	0	36	0	0
T144	0	109	0	0
T149	0	40	0	0
T165	0	96	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	6941	0	0
T1	13100	48	0	0
T2	34899	30	0	0
T3	2173	14	0	0
T4	739	3	0	0
T5	5381	17	0	0
T6	9368	13	0	0
T12	1551	2	0	0
T13	6878	25	0	0
T14	495	7	0	0
T15	498	10	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	21	0	0
T1	13100	2	0	0
T2	34899	0	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T28	0	3	0	0
T31	0	1	0	0
T111	0	1	0	0
T144	0	1	0	0
T165	0	1	0	0
T181	0	1	0	0
T205	0	1	0	0
T212	0	1	0	0
T218	0	1	0	0