Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T21
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T13,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T13,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T13,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T21
1	0	Covered	T2,T13,T21
1	1	Covered	T2,T13,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T21
0	1	Covered	T2,T42,T63
1	0	Covered	T2,T25,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T21,T34
0	1	Covered	T13,T21,T34
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T21,T34
1	-	Covered	T13,T21,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T13,T21
DetectSt	168	Covered	T2,T13,T21
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T13,T21,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T13,T21
DebounceSt->IdleSt	163	Covered	T42,T43,T235
DetectSt->IdleSt	186	Covered	T2,T25,T42
DetectSt->StableSt	191	Covered	T13,T21,T34
IdleSt->DebounceSt	148	Covered	T2,T13,T21
StableSt->IdleSt	206	Covered	T13,T21,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T13,T21
0	1	Covered	T2,T13,T21
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T21
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T13,T21
IdleSt	0	-	-	-	-	-	-	Covered	T2,T13,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T43
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T13,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T43,T235
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T13,T21
DetectSt	-	-	-	-	1	-	-	Covered	T2,T25,T42
DetectSt	-	-	-	-	0	1	-	Covered	T13,T21,T34
DetectSt	-	-	-	-	0	0	-	Covered	T2,T13,T21
StableSt	-	-	-	-	-	-	1	Covered	T13,T21,T34
StableSt	-	-	-	-	-	-	0	Covered	T13,T21,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	3075	0	0
CntIncr_A	6463474	100367	0	0
CntNoWrap_A	6463474	5794885	0	0
DetectStDropOut_A	6463474	508	0	0
DetectedOut_A	6463474	66555	0	0
DetectedPulseOut_A	6463474	809	0	0
DisabledIdleSt_A	6463474	5373714	0	0
DisabledNoDetection_A	6463474	5375856	0	0
EnterDebounceSt_A	6463474	1570	0	0
EnterDetectSt_A	6463474	1505	0	0
EnterStableSt_A	6463474	809	0	0
PulseIsPulse_A	6463474	809	0	0
StayInStableSt	6463474	65633	0	0
gen_high_event_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	695	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	3075	0	0
T2	34899	54	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	24	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	28	0	0
T25	0	36	0	0
T34	0	58	0	0
T41	0	52	0	0
T42	0	16	0	0
T62	0	46	0	0
T63	0	38	0	0
T64	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	100367	0	0
T2	34899	3722	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	612	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	840	0	0
T25	0	1433	0	0
T34	0	1682	0	0
T41	0	1690	0	0
T42	0	435	0	0
T62	0	1449	0	0
T63	0	890	0	0
T64	0	737	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5794885	0	0
T1	13100	4849	0	0
T2	34899	34362	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6453	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	508	0	0
T2	34899	2	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T42	0	1	0	0
T63	0	19	0	0
T64	0	14	0	0
T83	0	13	0	0
T85	0	1	0	0
T86	0	6	0	0
T87	0	21	0	0
T236	0	13	0	0
T237	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	66555	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	699	0	0	0
T13	6878	502	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	906	0	0
T34	0	1796	0	0
T41	0	1340	0	0
T42	0	298	0	0
T46	785	0	0	0
T50	491	0	0	0
T62	0	1696	0	0
T80	447	0	0	0
T166	0	5308	0	0
T201	0	2363	0	0
T203	0	2795	0	0
T238	0	779	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	809	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	699	0	0	0
T13	6878	12	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	14	0	0
T34	0	29	0	0
T41	0	26	0	0
T42	0	5	0	0
T46	785	0	0	0
T50	491	0	0	0
T62	0	23	0	0
T80	447	0	0	0
T166	0	15	0	0
T201	0	25	0	0
T203	0	25	0	0
T238	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5373714	0	0
T1	13100	4849	0	0
T2	34899	27309	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	2947	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5375856	0	0
T1	13100	4875	0	0
T2	34899	27320	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	2947	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	1570	0	0
T2	34899	27	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	12	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	14	0	0
T25	0	18	0	0
T34	0	29	0	0
T41	0	26	0	0
T42	0	9	0	0
T62	0	23	0	0
T63	0	19	0	0
T64	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	1505	0	0
T2	34899	27	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	12	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	14	0	0
T25	0	18	0	0
T34	0	29	0	0
T41	0	26	0	0
T42	0	7	0	0
T62	0	23	0	0
T63	0	19	0	0
T64	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	809	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	699	0	0	0
T13	6878	12	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	14	0	0
T34	0	29	0	0
T41	0	26	0	0
T42	0	5	0	0
T46	785	0	0	0
T50	491	0	0	0
T62	0	23	0	0
T80	447	0	0	0
T166	0	15	0	0
T201	0	25	0	0
T203	0	25	0	0
T238	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	809	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	699	0	0	0
T13	6878	12	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	14	0	0
T34	0	29	0	0
T41	0	26	0	0
T42	0	5	0	0
T46	785	0	0	0
T50	491	0	0	0
T62	0	23	0	0
T80	447	0	0	0
T166	0	15	0	0
T201	0	25	0	0
T203	0	25	0	0
T238	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	65633	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	699	0	0	0
T13	6878	490	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	890	0	0
T34	0	1767	0	0
T41	0	1305	0	0
T42	0	293	0	0
T46	785	0	0	0
T50	491	0	0	0
T62	0	1673	0	0
T80	447	0	0	0
T166	0	5292	0	0
T201	0	2334	0	0
T203	0	2769	0	0
T238	0	769	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	695	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	699	0	0	0
T13	6878	12	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	12	0	0
T34	0	29	0	0
T41	0	17	0	0
T42	0	5	0	0
T46	785	0	0	0
T50	491	0	0	0
T62	0	23	0	0
T80	447	0	0	0
T166	0	14	0	0
T201	0	21	0	0
T203	0	24	0	0
T238	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T6
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T21,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T6,T21,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T21,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T6,T21
1	0	Covered	T1,T2,T12
1	1	Covered	T6,T21,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T21,T8
0	1	Covered	T28,T81,T82
1	0	Covered	T42,T43

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T21,T8
0	1	Covered	T6,T21,T8
1	0	Covered	T21

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T21,T8
1	-	Covered	T6,T21,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T21,T8
DetectSt	168	Covered	T6,T21,T8
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T6,T21,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T21,T8
DebounceSt->IdleSt	163	Covered	T8,T38,T42
DetectSt->IdleSt	186	Covered	T42,T28,T81
DetectSt->StableSt	191	Covered	T6,T21,T8
IdleSt->DebounceSt	148	Covered	T6,T21,T8
StableSt->IdleSt	206	Covered	T6,T21,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T21,T8
0	1	Covered	T6,T21,T8
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T21,T8
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T21,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T43
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T21,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T38,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T21,T8
DetectSt	-	-	-	-	1	-	-	Covered	T42,T28,T81
DetectSt	-	-	-	-	0	1	-	Covered	T6,T21,T8
DetectSt	-	-	-	-	0	0	-	Covered	T6,T21,T8
StableSt	-	-	-	-	-	-	1	Covered	T6,T21,T8
StableSt	-	-	-	-	-	-	0	Covered	T6,T21,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	810	0	0
CntIncr_A	6463474	40642	0	0
CntNoWrap_A	6463474	5797150	0	0
DetectStDropOut_A	6463474	45	0	0
DetectedOut_A	6463474	14248	0	0
DetectedPulseOut_A	6463474	322	0	0
DisabledIdleSt_A	6463474	5445471	0	0
DisabledNoDetection_A	6463474	5447155	0	0
EnterDebounceSt_A	6463474	447	0	0
EnterDetectSt_A	6463474	370	0	0
EnterStableSt_A	6463474	322	0	0
PulseIsPulse_A	6463474	322	0	0
StayInStableSt	6463474	13877	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	266	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	810	0	0
T6	9368	8	0	0
T7	699	0	0	0
T8	19937	11	0	0
T9	0	2	0	0
T10	0	6	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	4	0	0
T26	0	4	0	0
T27	0	24	0	0
T38	0	5	0	0
T41	0	14	0	0
T42	0	7	0	0
T46	785	0	0	0
T50	491	0	0	0
T80	447	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	40642	0	0
T6	9368	716	0	0
T7	699	0	0	0
T8	19937	660	0	0
T9	0	25	0	0
T10	0	420	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	162	0	0
T26	0	186	0	0
T27	0	1109	0	0
T38	0	391	0	0
T41	0	308	0	0
T42	0	128	0	0
T46	785	0	0	0
T50	491	0	0	0
T80	447	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797150	0	0
T1	13100	4849	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8952	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	45	0	0
T28	369743	4	0	0
T30	15535	0	0	0
T69	0	3	0	0
T77	9320	0	0	0
T81	0	1	0	0
T82	0	8	0	0
T84	0	3	0	0
T88	0	3	0	0
T89	0	2	0	0
T90	0	5	0	0
T91	0	1	0	0
T94	0	2	0	0
T96	492	0	0	0
T97	493	0	0	0
T98	636	0	0	0
T99	451	0	0	0
T100	414	0	0	0
T101	523	0	0	0
T102	5556	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	14248	0	0
T6	9368	24	0	0
T7	699	0	0	0
T8	19937	75	0	0
T9	0	4	0	0
T10	0	101	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	103	0	0
T26	0	141	0	0
T27	0	948	0	0
T38	0	36	0	0
T41	0	367	0	0
T42	0	103	0	0
T46	785	0	0	0
T50	491	0	0	0
T80	447	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	322	0	0
T6	9368	4	0	0
T7	699	0	0	0
T8	19937	4	0	0
T9	0	1	0	0
T10	0	3	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	2	0	0
T26	0	2	0	0
T27	0	11	0	0
T38	0	2	0	0
T41	0	7	0	0
T42	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T80	447	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5445471	0	0
T1	13100	4849	0	0
T2	34899	34416	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	4029	0	0
T12	1551	349	0	0
T13	6878	5975	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5447155	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	4029	0	0
T12	1551	351	0	0
T13	6878	5976	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	447	0	0
T6	9368	4	0	0
T7	699	0	0	0
T8	19937	7	0	0
T9	0	1	0	0
T10	0	3	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	2	0	0
T26	0	2	0	0
T27	0	13	0	0
T38	0	3	0	0
T41	0	7	0	0
T42	0	5	0	0
T46	785	0	0	0
T50	491	0	0	0
T80	447	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	370	0	0
T6	9368	4	0	0
T7	699	0	0	0
T8	19937	4	0	0
T9	0	1	0	0
T10	0	3	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	2	0	0
T26	0	2	0	0
T27	0	11	0	0
T38	0	2	0	0
T41	0	7	0	0
T42	0	2	0	0
T46	785	0	0	0
T50	491	0	0	0
T80	447	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	322	0	0
T6	9368	4	0	0
T7	699	0	0	0
T8	19937	4	0	0
T9	0	1	0	0
T10	0	3	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	2	0	0
T26	0	2	0	0
T27	0	11	0	0
T38	0	2	0	0
T41	0	7	0	0
T42	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T80	447	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	322	0	0
T6	9368	4	0	0
T7	699	0	0	0
T8	19937	4	0	0
T9	0	1	0	0
T10	0	3	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	2	0	0
T26	0	2	0	0
T27	0	11	0	0
T38	0	2	0	0
T41	0	7	0	0
T42	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T80	447	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	13877	0	0
T6	9368	20	0	0
T7	699	0	0	0
T8	19937	71	0	0
T9	0	3	0	0
T10	0	98	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	101	0	0
T26	0	139	0	0
T27	0	937	0	0
T38	0	34	0	0
T41	0	353	0	0
T42	0	102	0	0
T46	785	0	0	0
T50	491	0	0	0
T80	447	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	266	0	0
T6	9368	4	0	0
T7	699	0	0	0
T8	19937	4	0	0
T9	0	1	0	0
T10	0	3	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	1	0	0
T26	0	2	0	0
T27	0	11	0	0
T28	0	4	0	0
T30	0	2	0	0
T38	0	2	0	0
T46	785	0	0	0
T50	491	0	0	0
T80	447	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T21
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T13,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T13,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T13,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T21
1	0	Covered	T2,T13,T21
1	1	Covered	T2,T13,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T21
0	1	Covered	T42,T62,T63
1	0	Covered	T41,T42,T62

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T21
0	1	Covered	T2,T13,T21
1	0	Covered	T41,T62,T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T13,T21
1	-	Covered	T2,T13,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T13,T21
DetectSt	168	Covered	T2,T13,T21
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T2,T13,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T13,T21
DebounceSt->IdleSt	163	Covered	T42,T43,T235
DetectSt->IdleSt	186	Covered	T41,T42,T62
DetectSt->StableSt	191	Covered	T2,T13,T21
IdleSt->DebounceSt	148	Covered	T2,T13,T21
StableSt->IdleSt	206	Covered	T2,T13,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T13,T21
0	1	Covered	T2,T13,T21
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T21
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T13,T21
IdleSt	0	-	-	-	-	-	-	Covered	T2,T13,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T43
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T13,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T43,T235
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T13,T21
DetectSt	-	-	-	-	1	-	-	Covered	T41,T42,T62
DetectSt	-	-	-	-	0	1	-	Covered	T2,T13,T21
DetectSt	-	-	-	-	0	0	-	Covered	T2,T13,T21
StableSt	-	-	-	-	-	-	1	Covered	T2,T13,T21
StableSt	-	-	-	-	-	-	0	Covered	T2,T13,T21
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	2947	0	0
CntIncr_A	6463474	100200	0	0
CntNoWrap_A	6463474	5795013	0	0
DetectStDropOut_A	6463474	508	0	0
DetectedOut_A	6463474	72066	0	0
DetectedPulseOut_A	6463474	681	0	0
DisabledIdleSt_A	6463474	5373630	0	0
DisabledNoDetection_A	6463474	5375791	0	0
EnterDebounceSt_A	6463474	1493	0	0
EnterDetectSt_A	6463474	1454	0	0
EnterStableSt_A	6463474	681	0	0
PulseIsPulse_A	6463474	681	0	0
StayInStableSt	6463474	71291	0	0
gen_high_event_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	578	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	2947	0	0
T2	34899	46	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	30	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	46	0	0
T25	0	62	0	0
T34	0	18	0	0
T41	0	24	0	0
T42	0	16	0	0
T62	0	28	0	0
T63	0	34	0	0
T64	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	100200	0	0
T2	34899	1932	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	540	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	1265	0	0
T25	0	1767	0	0
T34	0	612	0	0
T41	0	812	0	0
T42	0	490	0	0
T62	0	1025	0	0
T63	0	793	0	0
T64	0	630	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5795013	0	0
T1	13100	4849	0	0
T2	34899	34370	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6447	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	508	0	0
T26	23121	0	0	0
T42	6802	1	0	0
T49	980	0	0	0
T62	7746	5	0	0
T63	0	17	0	0
T64	0	12	0	0
T65	1156	0	0	0
T83	0	4	0	0
T85	0	14	0	0
T86	0	11	0	0
T87	0	23	0	0
T156	412	0	0	0
T157	424	0	0	0
T158	8473	0	0	0
T159	1267	0	0	0
T160	4414	0	0	0
T236	0	11	0	0
T238	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	72066	0	0
T2	34899	2987	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	1647	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	2334	0	0
T25	0	3841	0	0
T34	0	46	0	0
T41	0	3	0	0
T42	0	379	0	0
T62	0	2	0	0
T166	0	4328	0	0
T201	0	434	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	681	0	0
T2	34899	23	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	15	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	23	0	0
T25	0	31	0	0
T34	0	9	0	0
T41	0	3	0	0
T42	0	5	0	0
T62	0	2	0	0
T166	0	13	0	0
T201	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5373630	0	0
T1	13100	4849	0	0
T2	34899	25554	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	2039	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5375791	0	0
T1	13100	4875	0	0
T2	34899	25559	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	2039	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	1493	0	0
T2	34899	23	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	15	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	23	0	0
T25	0	31	0	0
T34	0	9	0	0
T41	0	12	0	0
T42	0	9	0	0
T62	0	14	0	0
T63	0	17	0	0
T64	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	1454	0	0
T2	34899	23	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	15	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	23	0	0
T25	0	31	0	0
T34	0	9	0	0
T41	0	12	0	0
T42	0	7	0	0
T62	0	14	0	0
T63	0	17	0	0
T64	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	681	0	0
T2	34899	23	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	15	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	23	0	0
T25	0	31	0	0
T34	0	9	0	0
T41	0	3	0	0
T42	0	5	0	0
T62	0	2	0	0
T166	0	13	0	0
T201	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	681	0	0
T2	34899	23	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	15	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	23	0	0
T25	0	31	0	0
T34	0	9	0	0
T41	0	3	0	0
T42	0	5	0	0
T62	0	2	0	0
T166	0	13	0	0
T201	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	71291	0	0
T2	34899	2958	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	1632	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	2307	0	0
T25	0	3808	0	0
T34	0	37	0	0
T42	0	374	0	0
T166	0	4315	0	0
T201	0	427	0	0
T203	0	687	0	0
T239	0	2645	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	578	0	0
T2	34899	17	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	15	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	19	0	0
T25	0	29	0	0
T34	0	9	0	0
T42	0	5	0	0
T166	0	13	0	0
T201	0	3	0	0
T203	0	13	0	0
T239	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T6
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T13,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T2,T13,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T13,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T6
1	0	Covered	T1,T2,T12
1	1	Covered	T2,T13,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T6
0	1	Covered	T42,T28,T199
1	0	Covered	T42,T43

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T6
0	1	Covered	T13,T6,T8
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T13,T6
1	-	Covered	T13,T6,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T13,T6
DetectSt	168	Covered	T2,T13,T6
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T2,T13,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T13,T6
DebounceSt->IdleSt	163	Covered	T8,T10,T42
DetectSt->IdleSt	186	Covered	T42,T28,T199
DetectSt->StableSt	191	Covered	T2,T13,T6
IdleSt->DebounceSt	148	Covered	T2,T13,T6
StableSt->IdleSt	206	Covered	T2,T13,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T13,T6
0	1	Covered	T2,T13,T6
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T6
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T13,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T43
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T13,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T10,T27
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T13,T6
DetectSt	-	-	-	-	1	-	-	Covered	T42,T28,T199
DetectSt	-	-	-	-	0	1	-	Covered	T2,T13,T6
DetectSt	-	-	-	-	0	0	-	Covered	T2,T13,T6
StableSt	-	-	-	-	-	-	1	Covered	T13,T6,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T13,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	802	0	0
CntIncr_A	6463474	42638	0	0
CntNoWrap_A	6463474	5797158	0	0
DetectStDropOut_A	6463474	39	0	0
DetectedOut_A	6463474	14760	0	0
DetectedPulseOut_A	6463474	334	0	0
DisabledIdleSt_A	6463474	5438579	0	0
DisabledNoDetection_A	6463474	5440329	0	0
EnterDebounceSt_A	6463474	426	0	0
EnterDetectSt_A	6463474	377	0	0
EnterStableSt_A	6463474	334	0	0
PulseIsPulse_A	6463474	334	0	0
StayInStableSt	6463474	14412	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	318	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	802	0	0
T2	34899	6	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	4	0	0
T8	0	18	0	0
T10	0	17	0	0
T12	1551	0	0	0
T13	6878	4	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	8	0	0
T25	0	4	0	0
T26	0	8	0	0
T38	0	14	0	0
T42	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	42638	0	0
T2	34899	189	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	312	0	0
T8	0	1060	0	0
T10	0	1418	0	0
T12	1551	0	0	0
T13	6878	140	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	316	0	0
T25	0	178	0	0
T26	0	604	0	0
T38	0	812	0	0
T42	0	207	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797158	0	0
T1	13100	4849	0	0
T2	34899	34410	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8956	0	0
T12	1551	349	0	0
T13	6878	6473	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	39	0	0
T26	23121	0	0	0
T28	0	4	0	0
T42	6802	1	0	0
T49	980	0	0	0
T62	7746	0	0	0
T65	1156	0	0	0
T69	0	2	0	0
T84	0	2	0	0
T89	0	4	0	0
T124	0	1	0	0
T156	412	0	0	0
T157	424	0	0	0
T158	8473	0	0	0
T159	1267	0	0	0
T160	4414	0	0	0
T199	0	5	0	0
T240	0	5	0	0
T241	0	4	0	0
T242	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	14760	0	0
T2	34899	220	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	58	0	0
T8	0	134	0	0
T10	0	45	0	0
T12	1551	0	0	0
T13	6878	110	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	205	0	0
T25	0	322	0	0
T26	0	50	0	0
T38	0	424	0	0
T42	0	101	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	334	0	0
T2	34899	3	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	2	0	0
T8	0	7	0	0
T10	0	8	0	0
T12	1551	0	0	0
T13	6878	2	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	4	0	0
T25	0	2	0	0
T26	0	4	0	0
T38	0	7	0	0
T42	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5438579	0	0
T1	13100	4849	0	0
T2	34899	31435	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	4029	0	0
T12	1551	349	0	0
T13	6878	4830	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5440329	0	0
T1	13100	4875	0	0
T2	34899	31441	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	4029	0	0
T12	1551	351	0	0
T13	6878	4831	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	426	0	0
T2	34899	3	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	2	0	0
T8	0	11	0	0
T10	0	9	0	0
T12	1551	0	0	0
T13	6878	2	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	4	0	0
T25	0	2	0	0
T26	0	4	0	0
T38	0	7	0	0
T42	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	377	0	0
T2	34899	3	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	2	0	0
T8	0	7	0	0
T10	0	8	0	0
T12	1551	0	0	0
T13	6878	2	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	4	0	0
T25	0	2	0	0
T26	0	4	0	0
T38	0	7	0	0
T42	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	334	0	0
T2	34899	3	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	2	0	0
T8	0	7	0	0
T10	0	8	0	0
T12	1551	0	0	0
T13	6878	2	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	4	0	0
T25	0	2	0	0
T26	0	4	0	0
T38	0	7	0	0
T42	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	334	0	0
T2	34899	3	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	2	0	0
T8	0	7	0	0
T10	0	8	0	0
T12	1551	0	0	0
T13	6878	2	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	4	0	0
T25	0	2	0	0
T26	0	4	0	0
T38	0	7	0	0
T42	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	14412	0	0
T2	34899	214	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	56	0	0
T8	0	127	0	0
T10	0	37	0	0
T12	1551	0	0	0
T13	6878	108	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	197	0	0
T25	0	320	0	0
T26	0	46	0	0
T38	0	417	0	0
T42	0	100	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	318	0	0
T5	5381	0	0	0
T6	9368	2	0	0
T7	699	0	0	0
T8	0	7	0	0
T10	0	8	0	0
T13	6878	2	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T25	0	2	0	0
T26	0	4	0	0
T27	0	5	0	0
T30	0	3	0	0
T38	0	7	0	0
T46	785	0	0	0
T50	491	0	0	0
T80	447	0	0	0
T167	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T21
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T13,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T13,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T13,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T21
1	0	Covered	T2,T13,T21
1	1	Covered	T2,T13,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T21
0	1	Covered	T13,T25,T42
1	0	Covered	T13,T25,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T34
0	1	Covered	T2,T21,T34
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T21,T34
1	-	Covered	T2,T21,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T13,T21
DetectSt	168	Covered	T2,T13,T21
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T2,T21,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T13,T21
DebounceSt->IdleSt	163	Covered	T42,T43,T235
DetectSt->IdleSt	186	Covered	T13,T25,T42
DetectSt->StableSt	191	Covered	T2,T21,T34
IdleSt->DebounceSt	148	Covered	T2,T13,T21
StableSt->IdleSt	206	Covered	T2,T21,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T13,T21
0	1	Covered	T2,T13,T21
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T21
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T13,T21
IdleSt	0	-	-	-	-	-	-	Covered	T2,T13,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T43
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T13,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T43,T235
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T13,T21
DetectSt	-	-	-	-	1	-	-	Covered	T13,T25,T42
DetectSt	-	-	-	-	0	1	-	Covered	T2,T21,T34
DetectSt	-	-	-	-	0	0	-	Covered	T2,T13,T21
StableSt	-	-	-	-	-	-	1	Covered	T2,T21,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T21,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	2819	0	0
CntIncr_A	6463474	92801	0	0
CntNoWrap_A	6463474	5795141	0	0
DetectStDropOut_A	6463474	494	0	0
DetectedOut_A	6463474	58196	0	0
DetectedPulseOut_A	6463474	725	0	0
DisabledIdleSt_A	6463474	5387926	0	0
DisabledNoDetection_A	6463474	5390090	0	0
EnterDebounceSt_A	6463474	1440	0	0
EnterDetectSt_A	6463474	1380	0	0
EnterStableSt_A	6463474	725	0	0
PulseIsPulse_A	6463474	725	0	0
StayInStableSt	6463474	57380	0	0
gen_high_event_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	633	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	2819	0	0
T2	34899	50	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	44	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	40	0	0
T25	0	18	0	0
T34	0	18	0	0
T41	0	32	0	0
T42	0	17	0	0
T62	0	18	0	0
T63	0	14	0	0
T64	0	56	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	92801	0	0
T2	34899	2150	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	1283	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	1220	0	0
T25	0	713	0	0
T34	0	513	0	0
T41	0	544	0	0
T42	0	387	0	0
T62	0	585	0	0
T63	0	324	0	0
T64	0	1484	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5795141	0	0
T1	13100	4849	0	0
T2	34899	34366	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6433	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	494	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T7	699	0	0	0
T13	6878	14	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T25	0	2	0	0
T42	0	1	0	0
T46	785	0	0	0
T50	491	0	0	0
T63	0	7	0	0
T64	0	28	0	0
T80	447	0	0	0
T83	0	10	0	0
T85	0	7	0	0
T86	0	19	0	0
T87	0	7	0	0
T203	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	58196	0	0
T2	34899	2225	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	1188	0	0
T34	0	147	0	0
T41	0	1214	0	0
T42	0	353	0	0
T62	0	96	0	0
T166	0	7322	0	0
T201	0	716	0	0
T238	0	4216	0	0
T239	0	1231	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	725	0	0
T2	34899	25	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	20	0	0
T34	0	9	0	0
T41	0	16	0	0
T42	0	5	0	0
T62	0	9	0	0
T166	0	28	0	0
T201	0	12	0	0
T238	0	29	0	0
T239	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5387926	0	0
T1	13100	4849	0	0
T2	34899	26360	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	3377	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5390090	0	0
T1	13100	4875	0	0
T2	34899	26367	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	3377	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	1440	0	0
T2	34899	25	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	22	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	20	0	0
T25	0	9	0	0
T34	0	9	0	0
T41	0	16	0	0
T42	0	10	0	0
T62	0	9	0	0
T63	0	7	0	0
T64	0	28	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	1380	0	0
T2	34899	25	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	22	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	20	0	0
T25	0	9	0	0
T34	0	9	0	0
T41	0	16	0	0
T42	0	7	0	0
T62	0	9	0	0
T63	0	7	0	0
T64	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	725	0	0
T2	34899	25	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	20	0	0
T34	0	9	0	0
T41	0	16	0	0
T42	0	5	0	0
T62	0	9	0	0
T166	0	28	0	0
T201	0	12	0	0
T238	0	29	0	0
T239	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	725	0	0
T2	34899	25	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	20	0	0
T34	0	9	0	0
T41	0	16	0	0
T42	0	5	0	0
T62	0	9	0	0
T166	0	28	0	0
T201	0	12	0	0
T238	0	29	0	0
T239	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	57380	0	0
T2	34899	2196	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	1165	0	0
T34	0	138	0	0
T41	0	1193	0	0
T42	0	348	0	0
T62	0	87	0	0
T166	0	7292	0	0
T201	0	701	0	0
T238	0	4181	0	0
T239	0	1214	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	633	0	0
T2	34899	21	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	17	0	0
T34	0	9	0	0
T41	0	11	0	0
T42	0	4	0	0
T62	0	9	0	0
T166	0	26	0	0
T201	0	9	0	0
T238	0	23	0	0
T239	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T6
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T6,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T2,T6,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T6,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T21
1	0	Covered	T1,T2,T12
1	1	Covered	T2,T6,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T21
0	1	Covered	T42,T66,T82
1	0	Covered	T42,T43

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T21
0	1	Covered	T2,T6,T8
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T21
1	-	Covered	T2,T6,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T21
DetectSt	168	Covered	T2,T6,T21
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T2,T6,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T21
DebounceSt->IdleSt	163	Covered	T8,T10,T42
DetectSt->IdleSt	186	Covered	T42,T66,T82
DetectSt->StableSt	191	Covered	T2,T6,T21
IdleSt->DebounceSt	148	Covered	T2,T6,T21
StableSt->IdleSt	206	Covered	T2,T6,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T21
0	1	Covered	T2,T6,T21
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T21
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T43
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T10,T28
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T21
DetectSt	-	-	-	-	1	-	-	Covered	T42,T66,T82
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T21
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T21
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	755	0	0
CntIncr_A	6463474	41090	0	0
CntNoWrap_A	6463474	5797205	0	0
DetectStDropOut_A	6463474	44	0	0
DetectedOut_A	6463474	12965	0	0
DetectedPulseOut_A	6463474	307	0	0
DisabledIdleSt_A	6463474	5460638	0	0
DisabledNoDetection_A	6463474	5462405	0	0
EnterDebounceSt_A	6463474	401	0	0
EnterDetectSt_A	6463474	356	0	0
EnterStableSt_A	6463474	307	0	0
PulseIsPulse_A	6463474	307	0	0
StayInStableSt	6463474	12642	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	287	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	755	0	0
T2	34899	8	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	2	0	0
T8	0	11	0	0
T10	0	13	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	6	0	0
T26	0	4	0	0
T27	0	10	0	0
T38	0	16	0	0
T41	0	10	0	0
T42	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	41090	0	0
T2	34899	352	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	174	0	0
T8	0	644	0	0
T10	0	632	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	144	0	0
T26	0	258	0	0
T27	0	850	0	0
T38	0	824	0	0
T41	0	245	0	0
T42	0	179	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797205	0	0
T1	13100	4849	0	0
T2	34899	34408	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8958	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	44	0	0
T26	23121	0	0	0
T42	6802	1	0	0
T49	980	0	0	0
T62	7746	0	0	0
T65	1156	0	0	0
T66	0	2	0	0
T82	0	4	0	0
T89	0	2	0	0
T106	0	7	0	0
T156	412	0	0	0
T157	424	0	0	0
T158	8473	0	0	0
T159	1267	0	0	0
T160	4414	0	0	0
T241	0	1	0	0
T243	0	6	0	0
T244	0	2	0	0
T245	0	1	0	0
T246	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	12965	0	0
T2	34899	200	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	12	0	0
T8	0	90	0	0
T10	0	483	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	246	0	0
T26	0	69	0	0
T27	0	25	0	0
T38	0	590	0	0
T41	0	243	0	0
T42	0	101	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	307	0	0
T2	34899	4	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	1	0	0
T8	0	4	0	0
T10	0	6	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	3	0	0
T26	0	2	0	0
T27	0	5	0	0
T38	0	8	0	0
T41	0	5	0	0
T42	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5460638	0	0
T1	13100	4849	0	0
T2	34899	32195	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	4029	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5462405	0	0
T1	13100	4875	0	0
T2	34899	32203	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	4029	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	401	0	0
T2	34899	4	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	1	0	0
T8	0	7	0	0
T10	0	7	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	3	0	0
T26	0	2	0	0
T27	0	5	0	0
T38	0	8	0	0
T41	0	5	0	0
T42	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	356	0	0
T2	34899	4	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	1	0	0
T8	0	4	0	0
T10	0	6	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	3	0	0
T26	0	2	0	0
T27	0	5	0	0
T38	0	8	0	0
T41	0	5	0	0
T42	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	307	0	0
T2	34899	4	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	1	0	0
T8	0	4	0	0
T10	0	6	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	3	0	0
T26	0	2	0	0
T27	0	5	0	0
T38	0	8	0	0
T41	0	5	0	0
T42	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	307	0	0
T2	34899	4	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	1	0	0
T8	0	4	0	0
T10	0	6	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	3	0	0
T26	0	2	0	0
T27	0	5	0	0
T38	0	8	0	0
T41	0	5	0	0
T42	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	12642	0	0
T2	34899	196	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	11	0	0
T8	0	86	0	0
T10	0	477	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	240	0	0
T26	0	67	0	0
T27	0	20	0	0
T38	0	582	0	0
T41	0	238	0	0
T42	0	100	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	287	0	0
T2	34899	4	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	1	0	0
T8	0	4	0	0
T10	0	6	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T26	0	2	0	0
T27	0	5	0	0
T28	0	6	0	0
T38	0	8	0	0
T41	0	5	0	0
T42	0	1	0	0