Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T21
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T13,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T13,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T13,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T21
1	0	Covered	T2,T13,T21
1	1	Covered	T2,T13,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T21
0	1	Covered	T25,T42,T63
1	0	Covered	T13,T25,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T34
0	1	Covered	T2,T21,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T21,T34
1	-	Covered	T2,T21,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T13,T21
DetectSt	168	Covered	T2,T13,T21
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T2,T21,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T13,T21
DebounceSt->IdleSt	163	Covered	T42,T43,T235
DetectSt->IdleSt	186	Covered	T13,T25,T42
DetectSt->StableSt	191	Covered	T2,T21,T34
IdleSt->DebounceSt	148	Covered	T2,T13,T21
StableSt->IdleSt	206	Covered	T2,T21,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T13,T21
0	1	Covered	T2,T13,T21
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T21
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T13,T21
IdleSt	0	-	-	-	-	-	-	Covered	T2,T13,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T43
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T13,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T43,T235
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T13,T21
DetectSt	-	-	-	-	1	-	-	Covered	T13,T25,T42
DetectSt	-	-	-	-	0	1	-	Covered	T2,T21,T34
DetectSt	-	-	-	-	0	0	-	Covered	T2,T13,T21
StableSt	-	-	-	-	-	-	1	Covered	T2,T21,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T21,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	2939	0	0
CntIncr_A	6463474	101822	0	0
CntNoWrap_A	6463474	5795021	0	0
DetectStDropOut_A	6463474	510	0	0
DetectedOut_A	6463474	62756	0	0
DetectedPulseOut_A	6463474	692	0	0
DisabledIdleSt_A	6463474	5381343	0	0
DisabledNoDetection_A	6463474	5383496	0	0
EnterDebounceSt_A	6463474	1498	0	0
EnterDetectSt_A	6463474	1441	0	0
EnterStableSt_A	6463474	692	0	0
PulseIsPulse_A	6463474	692	0	0
StayInStableSt	6463474	61962	0	0
gen_high_event_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	590	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	2939	0	0
T2	34899	54	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	10	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	16	0	0
T25	0	60	0	0
T34	0	12	0	0
T41	0	50	0	0
T42	0	16	0	0
T62	0	8	0	0
T63	0	58	0	0
T64	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	101822	0	0
T2	34899	2538	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	295	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	512	0	0
T25	0	2384	0	0
T34	0	384	0	0
T41	0	1250	0	0
T42	0	433	0	0
T62	0	148	0	0
T63	0	1363	0	0
T64	0	632	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5795021	0	0
T1	13100	4849	0	0
T2	34899	34362	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	6467	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	510	0	0
T25	13811	12	0	0
T34	7608	0	0	0
T35	676	0	0	0
T36	1657	0	0	0
T42	0	1	0	0
T59	524	0	0	0
T63	0	29	0	0
T64	0	12	0	0
T83	0	12	0	0
T86	0	17	0	0
T87	0	12	0	0
T201	0	5	0	0
T236	0	12	0	0
T237	0	10	0	0
T247	450	0	0	0
T248	454	0	0	0
T249	422	0	0	0
T250	422	0	0	0
T251	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	62756	0	0
T2	34899	2683	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	311	0	0
T34	0	54	0	0
T41	0	2516	0	0
T42	0	296	0	0
T62	0	153	0	0
T85	0	1503	0	0
T166	0	1512	0	0
T203	0	778	0	0
T238	0	1151	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	692	0	0
T2	34899	27	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	8	0	0
T34	0	6	0	0
T41	0	25	0	0
T42	0	5	0	0
T62	0	4	0	0
T85	0	8	0	0
T166	0	19	0	0
T203	0	13	0	0
T238	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5381343	0	0
T1	13100	4849	0	0
T2	34899	25793	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8960	0	0
T12	1551	349	0	0
T13	6878	3377	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5383496	0	0
T1	13100	4875	0	0
T2	34899	25799	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	3377	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	1498	0	0
T2	34899	27	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	5	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	8	0	0
T25	0	30	0	0
T34	0	6	0	0
T41	0	25	0	0
T42	0	9	0	0
T62	0	4	0	0
T63	0	29	0	0
T64	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	1441	0	0
T2	34899	27	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	5	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	8	0	0
T25	0	30	0	0
T34	0	6	0	0
T41	0	25	0	0
T42	0	7	0	0
T62	0	4	0	0
T63	0	29	0	0
T64	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	692	0	0
T2	34899	27	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	8	0	0
T34	0	6	0	0
T41	0	25	0	0
T42	0	5	0	0
T62	0	4	0	0
T85	0	8	0	0
T166	0	19	0	0
T203	0	13	0	0
T238	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	692	0	0
T2	34899	27	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	8	0	0
T34	0	6	0	0
T41	0	25	0	0
T42	0	5	0	0
T62	0	4	0	0
T85	0	8	0	0
T166	0	19	0	0
T203	0	13	0	0
T238	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	61962	0	0
T2	34899	2651	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	302	0	0
T34	0	48	0	0
T41	0	2480	0	0
T42	0	291	0	0
T62	0	149	0	0
T85	0	1494	0	0
T166	0	1492	0	0
T203	0	765	0	0
T238	0	1135	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	590	0	0
T2	34899	22	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	7	0	0
T34	0	6	0	0
T41	0	14	0	0
T42	0	5	0	0
T62	0	4	0	0
T85	0	7	0	0
T166	0	18	0	0
T203	0	13	0	0
T238	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T6
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T6,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T2,T6,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T6,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T21
1	0	Covered	T1,T2,T12
1	1	Covered	T2,T6,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T21
0	1	Covered	T6,T8,T82
1	0	Covered	T42,T43

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T10
0	1	Covered	T2,T10,T38
1	0	Covered	T43

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T21,T10
1	-	Covered	T2,T10,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T21
DetectSt	168	Covered	T2,T6,T21
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T2,T21,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T21
DebounceSt->IdleSt	163	Covered	T2,T8,T41
DetectSt->IdleSt	186	Covered	T6,T8,T42
DetectSt->StableSt	191	Covered	T2,T21,T10
IdleSt->DebounceSt	148	Covered	T2,T6,T21
StableSt->IdleSt	206	Covered	T2,T21,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T21
0	1	Covered	T2,T6,T21
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T21
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T43
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T8,T41
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T21
DetectSt	-	-	-	-	1	-	-	Covered	T6,T8,T42
DetectSt	-	-	-	-	0	1	-	Covered	T2,T21,T10
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T21
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T38
StableSt	-	-	-	-	-	-	0	Covered	T2,T21,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6463474	729	0	0
CntIncr_A	6463474	39090	0	0
CntNoWrap_A	6463474	5797231	0	0
DetectStDropOut_A	6463474	54	0	0
DetectedOut_A	6463474	13286	0	0
DetectedPulseOut_A	6463474	285	0	0
DisabledIdleSt_A	6463474	5448659	0	0
DisabledNoDetection_A	6463474	5450402	0	0
EnterDebounceSt_A	6463474	388	0	0
EnterDetectSt_A	6463474	343	0	0
EnterStableSt_A	6463474	285	0	0
PulseIsPulse_A	6463474	285	0	0
StayInStableSt	6463474	12964	0	0
gen_high_level_sva.HighLevelEvent_A	6463474	5800306	0	0
gen_not_sticky_sva.StableStDropOut_A	6463474	245	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	729	0	0
T2	34899	9	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	2	0	0
T8	0	7	0	0
T10	0	6	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	2	0	0
T26	0	12	0	0
T27	0	17	0	0
T38	0	14	0	0
T41	0	21	0	0
T42	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	39090	0	0
T2	34899	425	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	186	0	0
T8	0	456	0	0
T10	0	417	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	59	0	0
T26	0	834	0	0
T27	0	1193	0	0
T38	0	1022	0	0
T41	0	539	0	0
T42	0	124	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5797231	0	0
T1	13100	4849	0	0
T2	34899	34407	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	8958	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	54	0	0
T6	9368	1	0	0
T7	699	0	0	0
T8	19937	3	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	19067	0	0	0
T46	785	0	0	0
T50	491	0	0	0
T80	447	0	0	0
T82	0	3	0	0
T84	0	1	0	0
T88	0	3	0	0
T124	0	1	0	0
T207	0	12	0	0
T240	0	5	0	0
T252	0	1	0	0
T253	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	13286	0	0
T2	34899	173	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T10	0	103	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	71	0	0
T26	0	147	0	0
T27	0	268	0	0
T28	0	99	0	0
T30	0	19	0	0
T38	0	214	0	0
T41	0	447	0	0
T42	0	102	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	285	0	0
T2	34899	4	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T10	0	3	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	1	0	0
T26	0	6	0	0
T27	0	8	0	0
T28	0	3	0	0
T30	0	1	0	0
T38	0	7	0	0
T41	0	10	0	0
T42	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5448659	0	0
T1	13100	4849	0	0
T2	34899	31738	0	0
T3	2173	1772	0	0
T4	739	338	0	0
T5	5381	1099	0	0
T6	9368	4029	0	0
T12	1551	349	0	0
T13	6878	6477	0	0
T14	495	94	0	0
T15	498	97	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5450402	0	0
T1	13100	4875	0	0
T2	34899	31745	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	4029	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	388	0	0
T2	34899	5	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	1	0	0
T8	0	4	0	0
T10	0	3	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	1	0	0
T26	0	6	0	0
T27	0	9	0	0
T38	0	7	0	0
T41	0	11	0	0
T42	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	343	0	0
T2	34899	4	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	1	0	0
T8	0	3	0	0
T10	0	3	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	1	0	0
T26	0	6	0	0
T27	0	8	0	0
T38	0	7	0	0
T41	0	10	0	0
T42	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	285	0	0
T2	34899	4	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T10	0	3	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	1	0	0
T26	0	6	0	0
T27	0	8	0	0
T28	0	3	0	0
T30	0	1	0	0
T38	0	7	0	0
T41	0	10	0	0
T42	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	285	0	0
T2	34899	4	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T10	0	3	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	1	0	0
T26	0	6	0	0
T27	0	8	0	0
T28	0	3	0	0
T30	0	1	0	0
T38	0	7	0	0
T41	0	10	0	0
T42	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	12964	0	0
T2	34899	169	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T10	0	100	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T21	0	69	0	0
T26	0	141	0	0
T27	0	260	0	0
T28	0	96	0	0
T30	0	18	0	0
T38	0	207	0	0
T41	0	430	0	0
T42	0	101	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	5800306	0	0
T1	13100	4875	0	0
T2	34899	34428	0	0
T3	2173	1773	0	0
T4	739	339	0	0
T5	5381	1108	0	0
T6	9368	8962	0	0
T12	1551	351	0	0
T13	6878	6478	0	0
T14	495	95	0	0
T15	498	98	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6463474	245	0	0
T2	34899	4	0	0
T3	2173	0	0	0
T4	739	0	0	0
T5	5381	0	0	0
T6	9368	0	0	0
T10	0	3	0	0
T12	1551	0	0	0
T13	6878	0	0	0
T14	495	0	0	0
T15	498	0	0	0
T19	524	0	0	0
T26	0	6	0	0
T27	0	8	0	0
T28	0	3	0	0
T30	0	1	0	0
T38	0	7	0	0
T41	0	3	0	0
T66	0	1	0	0
T167	0	5	0	0