Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T30,T32
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T17,T30,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T17,T30,T31

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T17,T30,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T30,T32
1	0	Covered	T30,T32,T37
1	1	Covered	T17,T30,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T30,T31
0	1	Covered	T17,T30,T37
1	0	Covered	T30,T37,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T36
0	1	Covered	T32,T36,T42
1	0	Covered	T108

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T32,T36
1	-	Covered	T32,T36,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T30,T31
DetectSt	168	Covered	T17,T30,T31
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T31,T32,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T30,T31
DebounceSt->IdleSt	163	Covered	T116,T254,T255
DetectSt->IdleSt	186	Covered	T17,T30,T37
DetectSt->StableSt	191	Covered	T31,T32,T36
IdleSt->DebounceSt	148	Covered	T17,T30,T31
StableSt->IdleSt	206	Covered	T32,T36,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T30,T31
0	1	Covered	T17,T30,T31
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T30,T31
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T17,T30,T31
IdleSt	0	-	-	-	-	-	-	Covered	T17,T30,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T108,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T30,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T116,T254,T255
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T30,T31
DetectSt	-	-	-	-	1	-	-	Covered	T17,T30,T37
DetectSt	-	-	-	-	0	1	-	Covered	T31,T32,T36
DetectSt	-	-	-	-	0	0	-	Covered	T17,T30,T31
StableSt	-	-	-	-	-	-	1	Covered	T32,T36,T42
StableSt	-	-	-	-	-	-	0	Covered	T31,T32,T36
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	2914	0	0
CntIncr_A	7903577	121812	0	0
CntNoWrap_A	7903577	7248173	0	0
DetectStDropOut_A	7903577	435	0	0
DetectedOut_A	7903577	76827	0	0
DetectedPulseOut_A	7903577	783	0	0
DisabledIdleSt_A	7903577	6741466	0	0
DisabledNoDetection_A	7903577	6743569	0	0
EnterDebounceSt_A	7903577	1483	0	0
EnterDetectSt_A	7903577	1433	0	0
EnterStableSt_A	7903577	783	0	0
PulseIsPulse_A	7903577	783	0	0
StayInStableSt	7903577	75956	0	0
gen_high_event_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	694	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	2914	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	30	0	0
T18	502	0	0	0
T30	0	54	0	0
T31	0	2	0	0
T32	0	6	0	0
T36	0	14	0	0
T37	0	56	0	0
T42	0	54	0	0
T48	504	0	0	0
T54	0	22	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	46	0	0
T75	0	36	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	121812	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	815	0	0
T18	502	0	0	0
T30	0	1964	0	0
T31	0	21	0	0
T32	0	159	0	0
T36	0	364	0	0
T37	0	2652	0	0
T42	0	1917	0	0
T48	504	0	0	0
T54	0	756	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	1309	0	0
T75	0	800	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7248173	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4936	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	435	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	15	0	0
T18	502	0	0	0
T30	0	10	0	0
T37	0	7	0	0
T48	504	0	0	0
T54	0	9	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	23	0	0
T75	0	18	0	0
T119	0	7	0	0
T200	0	14	0	0
T256	0	13	0	0
T257	0	35	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	76827	0	0
T28	12055	0	0	0
T29	775	0	0	0
T31	470	44	0	0
T32	13036	41	0	0
T36	0	303	0	0
T37	15555	0	0	0
T42	0	1971	0	0
T52	422	0	0	0
T76	0	74	0	0
T96	418	0	0	0
T116	0	45	0	0
T130	407	0	0	0
T131	504	0	0	0
T132	410	0	0	0
T138	0	451	0	0
T190	0	285	0	0
T254	0	55	0	0
T258	0	27	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	783	0	0
T28	12055	0	0	0
T29	775	0	0	0
T31	470	1	0	0
T32	13036	3	0	0
T36	0	7	0	0
T37	15555	0	0	0
T42	0	27	0	0
T52	422	0	0	0
T76	0	7	0	0
T96	418	0	0	0
T116	0	8	0	0
T130	407	0	0	0
T131	504	0	0	0
T132	410	0	0	0
T138	0	12	0	0
T190	0	4	0	0
T254	0	6	0	0
T258	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6741466	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	2014	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6743569	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	2014	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	1483	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	15	0	0
T18	502	0	0	0
T30	0	27	0	0
T31	0	1	0	0
T32	0	3	0	0
T36	0	7	0	0
T37	0	28	0	0
T42	0	27	0	0
T48	504	0	0	0
T54	0	11	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	23	0	0
T75	0	18	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	1433	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	15	0	0
T18	502	0	0	0
T30	0	27	0	0
T31	0	1	0	0
T32	0	3	0	0
T36	0	7	0	0
T37	0	28	0	0
T42	0	27	0	0
T48	504	0	0	0
T54	0	11	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	23	0	0
T75	0	18	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	783	0	0
T28	12055	0	0	0
T29	775	0	0	0
T31	470	1	0	0
T32	13036	3	0	0
T36	0	7	0	0
T37	15555	0	0	0
T42	0	27	0	0
T52	422	0	0	0
T76	0	7	0	0
T96	418	0	0	0
T116	0	8	0	0
T130	407	0	0	0
T131	504	0	0	0
T132	410	0	0	0
T138	0	12	0	0
T190	0	4	0	0
T254	0	6	0	0
T258	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	783	0	0
T28	12055	0	0	0
T29	775	0	0	0
T31	470	1	0	0
T32	13036	3	0	0
T36	0	7	0	0
T37	15555	0	0	0
T42	0	27	0	0
T52	422	0	0	0
T76	0	7	0	0
T96	418	0	0	0
T116	0	8	0	0
T130	407	0	0	0
T131	504	0	0	0
T132	410	0	0	0
T138	0	12	0	0
T190	0	4	0	0
T254	0	6	0	0
T258	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	75956	0	0
T28	12055	0	0	0
T29	775	0	0	0
T31	470	42	0	0
T32	13036	38	0	0
T36	0	296	0	0
T37	15555	0	0	0
T42	0	1941	0	0
T52	422	0	0	0
T76	0	67	0	0
T96	418	0	0	0
T116	0	37	0	0
T130	407	0	0	0
T131	504	0	0	0
T132	410	0	0	0
T138	0	437	0	0
T190	0	281	0	0
T254	0	49	0	0
T258	0	25	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	694	0	0
T29	775	0	0	0
T32	13036	3	0	0
T36	0	7	0	0
T37	15555	0	0	0
T42	0	24	0	0
T76	0	7	0	0
T96	418	0	0	0
T116	0	8	0	0
T130	407	0	0	0
T131	504	0	0	0
T132	410	0	0	0
T133	503	0	0	0
T138	0	10	0	0
T190	0	4	0	0
T254	0	6	0	0
T259	0	3	0	0
T260	0	18	0	0
T261	218173	0	0	0
T262	502	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T13,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T13,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T5,T17
1	1	Covered	T1,T13,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T12
0	1	Covered	T107,T120,T121
1	0	Covered	T108,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T12
0	1	Covered	T1,T11,T12
1	0	Covered	T108,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T12
1	-	Covered	T1,T11,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T13,T11
DetectSt	168	Covered	T1,T11,T12
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T12
DebounceSt->IdleSt	163	Covered	T13,T12,T31
DetectSt->IdleSt	186	Covered	T107,T120,T121
DetectSt->StableSt	191	Covered	T1,T11,T12
IdleSt->DebounceSt	148	Covered	T1,T13,T11
StableSt->IdleSt	206	Covered	T1,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T13,T11
0	1	Covered	T1,T13,T11
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T12
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T13,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T12,T31
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T13,T11
DetectSt	-	-	-	-	1	-	-	Covered	T107,T120,T121
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T11,T12
StableSt	-	-	-	-	-	-	1	Covered	T1,T11,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	915	0	0
CntIncr_A	7903577	47948	0	0
CntNoWrap_A	7903577	7250172	0	0
DetectStDropOut_A	7903577	81	0	0
DetectedOut_A	7903577	16546	0	0
DetectedPulseOut_A	7903577	339	0	0
DisabledIdleSt_A	7903577	6887210	0	0
DisabledNoDetection_A	7903577	6888824	0	0
EnterDebounceSt_A	7903577	492	0	0
EnterDetectSt_A	7903577	424	0	0
EnterStableSt_A	7903577	339	0	0
PulseIsPulse_A	7903577	339	0	0
StayInStableSt	7903577	16171	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	299	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	915	0	0
T1	25831	6	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	4	0	0
T12	0	25	0	0
T13	5067	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	3	0	0
T25	0	2	0	0
T28	0	3	0	0
T31	0	1	0	0
T39	0	1	0	0
T43	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	47948	0	0
T1	25831	345	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	314	0	0
T12	0	930	0	0
T13	5067	35	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	45	0	0
T25	0	40	0	0
T28	0	45	0	0
T31	0	20	0	0
T39	0	20	0	0
T43	0	107	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7250172	0	0
T1	25831	25357	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4665	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	81	0	0
T46	6960	0	0	0
T62	492	0	0	0
T75	4865	0	0	0
T76	23777	0	0	0
T107	32359	14	0	0
T116	4916	0	0	0
T120	0	3	0	0
T121	0	10	0	0
T122	0	11	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	6	0	0
T127	0	4	0	0
T128	0	4	0	0
T129	0	1	0	0
T134	529	0	0	0
T135	507	0	0	0
T136	406	0	0	0
T137	588	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	16546	0	0
T1	25831	282	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	32	0	0
T12	0	673	0	0
T13	5067	0	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	5	0	0
T28	0	3	0	0
T41	0	4	0	0
T42	0	74	0	0
T43	0	38	0	0
T138	0	127	0	0
T139	0	64	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	339	0	0
T1	25831	3	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	2	0	0
T12	0	11	0	0
T13	5067	0	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	1	0	0
T28	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T138	0	2	0	0
T139	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6887210	0	0
T1	25831	20144	0	0
T2	1099	698	0	0
T5	4417	620	0	0
T6	651	250	0	0
T13	5067	2014	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6888824	0	0
T1	25831	20144	0	0
T2	1099	699	0	0
T5	4417	630	0	0
T6	651	251	0	0
T13	5067	2014	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	492	0	0
T1	25831	3	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	2	0	0
T12	0	14	0	0
T13	5067	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	2	0	0
T25	0	2	0	0
T28	0	2	0	0
T31	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	424	0	0
T1	25831	3	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	2	0	0
T12	0	11	0	0
T13	5067	0	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	1	0	0
T28	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T107	0	14	0	0
T138	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	339	0	0
T1	25831	3	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	2	0	0
T12	0	11	0	0
T13	5067	0	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	1	0	0
T28	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T138	0	2	0	0
T139	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	339	0	0
T1	25831	3	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	2	0	0
T12	0	11	0	0
T13	5067	0	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	1	0	0
T28	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T138	0	2	0	0
T139	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	16171	0	0
T1	25831	279	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	30	0	0
T12	0	662	0	0
T13	5067	0	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	4	0	0
T28	0	2	0	0
T41	0	3	0	0
T42	0	68	0	0
T43	0	37	0	0
T138	0	125	0	0
T139	0	61	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	299	0	0
T1	25831	3	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	2	0	0
T12	0	11	0	0
T13	5067	0	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T22	0	1	0	0
T28	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T138	0	2	0	0
T139	0	3	0	0
T141	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T30,T32
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T17,T30,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T17,T30,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T17,T30,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T30,T32
1	0	Covered	T30,T32,T37
1	1	Covered	T17,T30,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T30,T32
0	1	Covered	T17,T54,T74
1	0	Covered	T54,T252,T108

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T32,T37
0	1	Covered	T30,T32,T37
1	0	Covered	T108,T53,T263

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T32,T37
1	-	Covered	T30,T32,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T30,T32
DetectSt	168	Covered	T17,T30,T32
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T30,T32,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T30,T32
DebounceSt->IdleSt	163	Covered	T116,T254,T255
DetectSt->IdleSt	186	Covered	T17,T54,T74
DetectSt->StableSt	191	Covered	T30,T32,T37
IdleSt->DebounceSt	148	Covered	T17,T30,T32
StableSt->IdleSt	206	Covered	T30,T32,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T30,T32
0	1	Covered	T17,T30,T32
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T30,T32
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T17,T30,T32
IdleSt	0	-	-	-	-	-	-	Covered	T17,T30,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T108,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T30,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T116,T254,T255
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T30,T32
DetectSt	-	-	-	-	1	-	-	Covered	T17,T54,T74
DetectSt	-	-	-	-	0	1	-	Covered	T30,T32,T37
DetectSt	-	-	-	-	0	0	-	Covered	T17,T30,T32
StableSt	-	-	-	-	-	-	1	Covered	T30,T32,T37
StableSt	-	-	-	-	-	-	0	Covered	T30,T32,T37
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	2878	0	0
CntIncr_A	7903577	102748	0	0
CntNoWrap_A	7903577	7248209	0	0
DetectStDropOut_A	7903577	386	0	0
DetectedOut_A	7903577	70272	0	0
DetectedPulseOut_A	7903577	869	0	0
DisabledIdleSt_A	7903577	6745357	0	0
DisabledNoDetection_A	7903577	6747452	0	0
EnterDebounceSt_A	7903577	1465	0	0
EnterDetectSt_A	7903577	1415	0	0
EnterStableSt_A	7903577	869	0	0
PulseIsPulse_A	7903577	869	0	0
StayInStableSt	7903577	69306	0	0
gen_high_event_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	769	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	2878	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	6	0	0
T18	502	0	0	0
T30	0	28	0	0
T32	0	14	0	0
T36	0	64	0	0
T37	0	52	0	0
T42	0	18	0	0
T48	504	0	0	0
T54	0	18	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	30	0	0
T75	0	22	0	0
T76	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	102748	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	162	0	0
T18	502	0	0	0
T30	0	966	0	0
T32	0	371	0	0
T36	0	2080	0	0
T37	0	1820	0	0
T42	0	540	0	0
T48	504	0	0	0
T54	0	621	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	845	0	0
T75	0	492	0	0
T76	0	288	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7248209	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4960	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	386	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	3	0	0
T18	502	0	0	0
T48	504	0	0	0
T54	0	7	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	15	0	0
T75	0	11	0	0
T200	0	23	0	0
T252	0	8	0	0
T256	0	29	0	0
T257	0	23	0	0
T264	0	3	0	0
T265	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	70272	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	978	0	0
T31	470	0	0	0
T32	0	172	0	0
T36	0	2444	0	0
T37	0	2737	0	0
T42	0	733	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	373	0	0
T116	0	131	0	0
T119	0	2688	0	0
T138	0	1600	0	0
T189	0	292	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	869	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	14	0	0
T31	470	0	0	0
T32	0	7	0	0
T36	0	32	0	0
T37	0	26	0	0
T42	0	9	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	6	0	0
T116	0	5	0	0
T119	0	14	0	0
T138	0	23	0	0
T189	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6745357	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	2014	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6747452	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	2014	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	1465	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	3	0	0
T18	502	0	0	0
T30	0	14	0	0
T32	0	7	0	0
T36	0	32	0	0
T37	0	26	0	0
T42	0	9	0	0
T48	504	0	0	0
T54	0	9	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	15	0	0
T75	0	11	0	0
T76	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	1415	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	3	0	0
T18	502	0	0	0
T30	0	14	0	0
T32	0	7	0	0
T36	0	32	0	0
T37	0	26	0	0
T42	0	9	0	0
T48	504	0	0	0
T54	0	9	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	15	0	0
T75	0	11	0	0
T76	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	869	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	14	0	0
T31	470	0	0	0
T32	0	7	0	0
T36	0	32	0	0
T37	0	26	0	0
T42	0	9	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	6	0	0
T116	0	5	0	0
T119	0	14	0	0
T138	0	23	0	0
T189	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	869	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	14	0	0
T31	470	0	0	0
T32	0	7	0	0
T36	0	32	0	0
T37	0	26	0	0
T42	0	9	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	6	0	0
T116	0	5	0	0
T119	0	14	0	0
T138	0	23	0	0
T189	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	69306	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	962	0	0
T31	470	0	0	0
T32	0	165	0	0
T36	0	2408	0	0
T37	0	2708	0	0
T42	0	724	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	366	0	0
T116	0	126	0	0
T119	0	2670	0	0
T138	0	1577	0	0
T189	0	286	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	769	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	12	0	0
T31	470	0	0	0
T32	0	7	0	0
T36	0	28	0	0
T37	0	23	0	0
T42	0	9	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	5	0	0
T116	0	5	0	0
T119	0	10	0	0
T138	0	23	0	0
T189	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T13,T17
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T17
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T13,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T13,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T13,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T11
1	0	Covered	T1,T5,T17
1	1	Covered	T13,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T11,T12
0	1	Covered	T13,T43,T140
1	0	Covered	T108,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T30
0	1	Covered	T11,T12,T30
1	0	Covered	T110,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T30
1	-	Covered	T11,T12,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T11,T12
DetectSt	168	Covered	T13,T11,T12
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T11,T12,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T11,T12
DebounceSt->IdleSt	163	Covered	T13,T12,T43
DetectSt->IdleSt	186	Covered	T13,T43,T140
DetectSt->StableSt	191	Covered	T11,T12,T30
IdleSt->DebounceSt	148	Covered	T13,T11,T12
StableSt->IdleSt	206	Covered	T11,T12,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T11,T12
0	1	Covered	T13,T11,T12
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T11,T12
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T12,T43
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T11,T12
DetectSt	-	-	-	-	1	-	-	Covered	T13,T43,T140
DetectSt	-	-	-	-	0	1	-	Covered	T11,T12,T30
DetectSt	-	-	-	-	0	0	-	Covered	T13,T11,T12
StableSt	-	-	-	-	-	-	1	Covered	T11,T12,T30
StableSt	-	-	-	-	-	-	0	Covered	T11,T12,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	755	0	0
CntIncr_A	7903577	40060	0	0
CntNoWrap_A	7903577	7250332	0	0
DetectStDropOut_A	7903577	53	0	0
DetectedOut_A	7903577	12769	0	0
DetectedPulseOut_A	7903577	305	0	0
DisabledIdleSt_A	7903577	6909859	0	0
DisabledNoDetection_A	7903577	6911542	0	0
EnterDebounceSt_A	7903577	393	0	0
EnterDetectSt_A	7903577	363	0	0
EnterStableSt_A	7903577	305	0	0
PulseIsPulse_A	7903577	305	0	0
StayInStableSt	7903577	12412	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	248	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	755	0	0
T2	1099	0	0	0
T3	596	0	0	0
T11	0	4	0	0
T12	0	9	0	0
T13	5067	13	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	4	0	0
T32	0	1	0	0
T36	0	8	0	0
T37	0	5	0	0
T43	0	13	0	0
T48	504	0	0	0
T70	502	0	0	0
T76	0	2	0	0
T107	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	40060	0	0
T2	1099	0	0	0
T3	596	0	0	0
T11	0	216	0	0
T12	0	425	0	0
T13	5067	575	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	134	0	0
T32	0	16	0	0
T36	0	304	0	0
T37	0	198	0	0
T43	0	935	0	0
T48	504	0	0	0
T70	502	0	0	0
T76	0	70	0	0
T107	0	518	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7250332	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4653	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	53	0	0
T2	1099	0	0	0
T3	596	0	0	0
T13	5067	6	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T43	0	6	0	0
T48	504	0	0	0
T70	502	0	0	0
T91	0	1	0	0
T140	0	3	0	0
T181	0	1	0	0
T196	0	1	0	0
T249	0	5	0	0
T266	0	6	0	0
T267	0	4	0	0
T268	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	12769	0	0
T11	12474	131	0	0
T12	22676	148	0	0
T27	766	0	0	0
T30	20486	113	0	0
T36	0	249	0	0
T37	0	141	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	90	0	0
T107	0	72	0	0
T119	0	111	0	0
T139	0	443	0	0
T189	0	68	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	305	0	0
T11	12474	2	0	0
T12	22676	4	0	0
T27	766	0	0	0
T30	20486	2	0	0
T36	0	4	0	0
T37	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	1	0	0
T107	0	14	0	0
T119	0	2	0	0
T139	0	11	0	0
T189	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6909859	0	0
T1	25831	20144	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	2014	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6911542	0	0
T1	25831	20144	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	2014	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	393	0	0
T2	1099	0	0	0
T3	596	0	0	0
T11	0	2	0	0
T12	0	5	0	0
T13	5067	7	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	2	0	0
T32	0	1	0	0
T36	0	4	0	0
T37	0	3	0	0
T43	0	7	0	0
T48	504	0	0	0
T70	502	0	0	0
T76	0	1	0	0
T107	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	363	0	0
T2	1099	0	0	0
T3	596	0	0	0
T11	0	2	0	0
T12	0	4	0	0
T13	5067	6	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	2	0	0
T36	0	4	0	0
T37	0	2	0	0
T43	0	6	0	0
T48	504	0	0	0
T70	502	0	0	0
T76	0	1	0	0
T107	0	14	0	0
T119	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	305	0	0
T11	12474	2	0	0
T12	22676	4	0	0
T27	766	0	0	0
T30	20486	2	0	0
T36	0	4	0	0
T37	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	1	0	0
T107	0	14	0	0
T119	0	2	0	0
T139	0	11	0	0
T189	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	305	0	0
T11	12474	2	0	0
T12	22676	4	0	0
T27	766	0	0	0
T30	20486	2	0	0
T36	0	4	0	0
T37	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	1	0	0
T107	0	14	0	0
T119	0	2	0	0
T139	0	11	0	0
T189	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	12412	0	0
T11	12474	129	0	0
T12	22676	144	0	0
T27	766	0	0	0
T30	20486	111	0	0
T36	0	245	0	0
T37	0	137	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	88	0	0
T107	0	58	0	0
T119	0	109	0	0
T139	0	432	0	0
T189	0	64	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	248	0	0
T11	12474	2	0	0
T12	22676	4	0	0
T27	766	0	0	0
T30	20486	2	0	0
T36	0	4	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T107	0	14	0	0
T119	0	2	0	0
T139	0	11	0	0
T141	0	2	0	0
T190	0	1	0	0
T199	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T30,T32
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T17,T30,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T17,T30,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T17,T30,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T30,T32
1	0	Covered	T30,T32,T37
1	1	Covered	T17,T30,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T30,T32
0	1	Covered	T17,T74,T75
1	0	Covered	T260,T150,T252

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T32,T37
0	1	Covered	T30,T32,T37
1	0	Covered	T112,T53,T269

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T32,T37
1	-	Covered	T30,T32,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T30,T32
DetectSt	168	Covered	T17,T30,T32
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T30,T32,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T30,T32
DebounceSt->IdleSt	163	Covered	T116,T254,T255
DetectSt->IdleSt	186	Covered	T17,T74,T75
DetectSt->StableSt	191	Covered	T30,T32,T37
IdleSt->DebounceSt	148	Covered	T17,T30,T32
StableSt->IdleSt	206	Covered	T30,T32,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T30,T32
0	1	Covered	T17,T30,T32
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T30,T32
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T17,T30,T32
IdleSt	0	-	-	-	-	-	-	Covered	T17,T30,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T108,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T30,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T116,T254,T255
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T30,T32
DetectSt	-	-	-	-	1	-	-	Covered	T17,T74,T75
DetectSt	-	-	-	-	0	1	-	Covered	T30,T32,T37
DetectSt	-	-	-	-	0	0	-	Covered	T17,T30,T32
StableSt	-	-	-	-	-	-	1	Covered	T30,T32,T37
StableSt	-	-	-	-	-	-	0	Covered	T30,T32,T37
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	3147	0	0
CntIncr_A	7903577	121154	0	0
CntNoWrap_A	7903577	7247940	0	0
DetectStDropOut_A	7903577	344	0	0
DetectedOut_A	7903577	102710	0	0
DetectedPulseOut_A	7903577	992	0	0
DisabledIdleSt_A	7903577	6726153	0	0
DisabledNoDetection_A	7903577	6728224	0	0
EnterDebounceSt_A	7903577	1600	0	0
EnterDetectSt_A	7903577	1550	0	0
EnterStableSt_A	7903577	992	0	0
PulseIsPulse_A	7903577	992	0	0
StayInStableSt	7903577	101599	0	0
gen_high_event_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	847	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	3147	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	22	0	0
T18	502	0	0	0
T30	0	12	0	0
T32	0	64	0	0
T36	0	10	0	0
T37	0	60	0	0
T42	0	32	0	0
T48	504	0	0	0
T54	0	10	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	20	0	0
T75	0	29	0	0
T76	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	121154	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	600	0	0
T18	502	0	0	0
T30	0	228	0	0
T32	0	1056	0	0
T36	0	335	0	0
T37	0	1590	0	0
T42	0	1024	0	0
T48	504	0	0	0
T54	0	300	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	562	0	0
T75	0	669	0	0
T76	0	1566	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7247940	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4944	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	344	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	11	0	0
T18	502	0	0	0
T48	504	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	10	0	0
T75	0	14	0	0
T108	0	1	0	0
T200	0	7	0	0
T252	0	5	0	0
T256	0	13	0	0
T257	0	11	0	0
T260	0	7	0	0
T264	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	102710	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	466	0	0
T31	470	0	0	0
T32	0	1631	0	0
T36	0	37	0	0
T37	0	1795	0	0
T42	0	1346	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T54	0	332	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	3362	0	0
T116	0	151	0	0
T119	0	4548	0	0
T138	0	719	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	992	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	6	0	0
T31	470	0	0	0
T32	0	32	0	0
T36	0	5	0	0
T37	0	30	0	0
T42	0	16	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T54	0	5	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	27	0	0
T116	0	5	0	0
T119	0	11	0	0
T138	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6726153	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	2014	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6728224	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	2014	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	1600	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	11	0	0
T18	502	0	0	0
T30	0	6	0	0
T32	0	32	0	0
T36	0	5	0	0
T37	0	30	0	0
T42	0	16	0	0
T48	504	0	0	0
T54	0	5	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	10	0	0
T75	0	15	0	0
T76	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	1550	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	11	0	0
T18	502	0	0	0
T30	0	6	0	0
T32	0	32	0	0
T36	0	5	0	0
T37	0	30	0	0
T42	0	16	0	0
T48	504	0	0	0
T54	0	5	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	10	0	0
T75	0	15	0	0
T76	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	992	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	6	0	0
T31	470	0	0	0
T32	0	32	0	0
T36	0	5	0	0
T37	0	30	0	0
T42	0	16	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T54	0	5	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	27	0	0
T116	0	5	0	0
T119	0	11	0	0
T138	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	992	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	6	0	0
T31	470	0	0	0
T32	0	32	0	0
T36	0	5	0	0
T37	0	30	0	0
T42	0	16	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T54	0	5	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	27	0	0
T116	0	5	0	0
T119	0	11	0	0
T138	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	101599	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	458	0	0
T31	470	0	0	0
T32	0	1597	0	0
T36	0	32	0	0
T37	0	1763	0	0
T42	0	1329	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T54	0	327	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	3329	0	0
T116	0	146	0	0
T119	0	4535	0	0
T138	0	704	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	847	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	4	0	0
T31	470	0	0	0
T32	0	30	0	0
T36	0	5	0	0
T37	0	28	0	0
T42	0	15	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T54	0	5	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	21	0	0
T116	0	5	0	0
T119	0	9	0	0
T138	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T13,T17
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T17
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T13,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T13,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T11
1	0	Covered	T1,T5,T17
1	1	Covered	T1,T13,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T12
0	1	Covered	T120,T140,T122
1	0	Covered	T108,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T12
0	1	Covered	T1,T11,T12
1	0	Covered	T108,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T12
1	-	Covered	T1,T11,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T13,T11
DetectSt	168	Covered	T1,T11,T12
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T12
DebounceSt->IdleSt	163	Covered	T1,T13,T12
DetectSt->IdleSt	186	Covered	T120,T140,T122
DetectSt->StableSt	191	Covered	T1,T11,T12
IdleSt->DebounceSt	148	Covered	T1,T13,T11
StableSt->IdleSt	206	Covered	T1,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T13,T11
0	1	Covered	T1,T13,T11
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T12
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T13,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T13,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T13,T11
DetectSt	-	-	-	-	1	-	-	Covered	T120,T140,T122
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T11,T12
StableSt	-	-	-	-	-	-	1	Covered	T1,T11,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	781	0	0
CntIncr_A	7903577	44221	0	0
CntNoWrap_A	7903577	7250306	0	0
DetectStDropOut_A	7903577	44	0	0
DetectedOut_A	7903577	16913	0	0
DetectedPulseOut_A	7903577	320	0	0
DisabledIdleSt_A	7903577	6867828	0	0
DisabledNoDetection_A	7903577	6869474	0	0
EnterDebounceSt_A	7903577	413	0	0
EnterDetectSt_A	7903577	368	0	0
EnterStableSt_A	7903577	320	0	0
PulseIsPulse_A	7903577	320	0	0
StayInStableSt	7903577	16557	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	281	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	781	0	0
T1	25831	15	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	4	0	0
T12	0	14	0	0
T13	5067	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	4	0	0
T32	0	4	0	0
T37	0	2	0	0
T42	0	1	0	0
T43	0	29	0	0
T54	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	44221	0	0
T1	25831	1022	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	222	0	0
T12	0	713	0	0
T13	5067	35	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	132	0	0
T32	0	66	0	0
T37	0	65	0	0
T42	0	23	0	0
T43	0	1648	0	0
T54	0	108	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7250306	0	0
T1	25831	25348	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4665	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	44	0	0
T118	725	0	0	0
T120	33002	6	0	0
T122	0	3	0	0
T126	0	12	0	0
T128	0	2	0	0
T140	48660	2	0	0
T270	0	2	0	0
T271	0	3	0	0
T272	0	6	0	0
T273	0	6	0	0
T274	0	2	0	0
T275	490	0	0	0
T276	521	0	0	0
T277	1700	0	0	0
T278	508	0	0	0
T279	422	0	0	0
T280	677	0	0	0
T281	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	16913	0	0
T1	25831	528	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	124	0	0
T12	0	162	0	0
T13	5067	0	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	112	0	0
T32	0	82	0	0
T37	0	88	0	0
T43	0	448	0	0
T54	0	140	0	0
T76	0	316	0	0
T107	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	320	0	0
T1	25831	7	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	2	0	0
T12	0	5	0	0
T13	5067	0	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T37	0	1	0	0
T43	0	14	0	0
T54	0	2	0	0
T76	0	6	0	0
T107	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6867828	0	0
T1	25831	20144	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	2014	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6869474	0	0
T1	25831	20144	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	2014	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	413	0	0
T1	25831	8	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	2	0	0
T12	0	9	0	0
T13	5067	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T37	0	1	0	0
T42	0	1	0	0
T43	0	15	0	0
T54	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	368	0	0
T1	25831	7	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	2	0	0
T12	0	5	0	0
T13	5067	0	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T37	0	1	0	0
T43	0	14	0	0
T54	0	2	0	0
T76	0	6	0	0
T107	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	320	0	0
T1	25831	7	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	2	0	0
T12	0	5	0	0
T13	5067	0	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T37	0	1	0	0
T43	0	14	0	0
T54	0	2	0	0
T76	0	6	0	0
T107	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	320	0	0
T1	25831	7	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	2	0	0
T12	0	5	0	0
T13	5067	0	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T37	0	1	0	0
T43	0	14	0	0
T54	0	2	0	0
T76	0	6	0	0
T107	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	16557	0	0
T1	25831	521	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	122	0	0
T12	0	157	0	0
T13	5067	0	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	108	0	0
T32	0	78	0	0
T37	0	87	0	0
T43	0	434	0	0
T54	0	138	0	0
T76	0	310	0	0
T107	0	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	281	0	0
T1	25831	7	0	0
T2	1099	0	0	0
T5	4417	0	0	0
T6	651	0	0	0
T11	0	2	0	0
T12	0	5	0	0
T13	5067	0	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T43	0	14	0	0
T54	0	2	0	0
T76	0	6	0	0
T107	0	1	0	0
T139	0	2	0	0