Unified Coverage Report :: Module :: sysrst_ctrl_combo

Module : sysrst_ctrl_combo

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	92.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_combo	96.15	100.00	92.31

---

Module Instance : tb.dut.u_sysrst_ctrl_combo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	92.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	97.87		100.00	98.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_combo_trigger[0].u_combo_act	99.19	100.00	97.56			100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
gen_combo_trigger[1].u_combo_act	99.19	100.00	97.56			100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
gen_combo_trigger[2].u_combo_act	99.19	100.00	97.56			100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
gen_combo_trigger[3].u_combo_act	99.19	100.00	97.56			100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl_combo

	Line No.	Total	Covered	Percent
TOTAL		28	28	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	155	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	1	1
54	4	4
66	4	4
70	4	4
92	4	4
106	4	4
111	4	4
151	1	1
154	1	1
155	1	1

---

Cond Coverage for Module : sysrst_ctrl_combo

	Total	Covered	Percent
Conditions	52	48	92.31
Logical	52	48	92.31
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[0].cfg_in_pre) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T17,T30,T32
1	Covered	T1,T5,T6

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[1].cfg_in_pre) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T17,T30,T32
1	Covered	T1,T5,T6

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[2].cfg_in_pre) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T17,T30,T32
1	Covered	T1,T5,T6

 LINE       70
 EXPRESSION ((in & gen_combo_trigger[3].cfg_in_pre) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T17,T30,T32
1	Covered	T1,T5,T6

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[0].cfg_in_sel)) && 
      2  ((gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en) || ((!gen_combo_trigger[0].cfg_combo_pre_en))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T17,T30,T31
1	1	Covered	T1,T5,T13

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en) || ((!gen_combo_trigger[0].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T30,T31
0	1	Covered	T1,T5,T6
1	0	Covered	T31,T32,T36

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T30,T31
1	0	Not Covered
1	1	Covered	T31,T32,T36

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[1].cfg_in_sel)) && 
      2  ((gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en) || ((!gen_combo_trigger[1].cfg_combo_pre_en))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T17,T30,T32
1	1	Covered	T1,T13,T11

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en) || ((!gen_combo_trigger[1].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T30,T32
0	1	Covered	T1,T5,T6
1	0	Covered	T30,T32,T37

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T30,T32
1	0	Not Covered
1	1	Covered	T30,T32,T37

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[2].cfg_in_sel)) && 
      2  ((gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en) || ((!gen_combo_trigger[2].cfg_combo_pre_en))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T17,T30,T32
1	1	Covered	T1,T13,T11

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en) || ((!gen_combo_trigger[2].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T30,T32
0	1	Covered	T1,T5,T6
1	0	Covered	T30,T32,T37

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T30,T32
1	0	Not Covered
1	1	Covered	T30,T32,T37

 LINE       106
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[3].cfg_in_sel)) && 
      2  ((gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en) || ((!gen_combo_trigger[3].cfg_combo_pre_en))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T17,T30,T32
1	1	Covered	T1,T13,T11

 LINE       106
 SUB-EXPRESSION ((gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en) || ((!gen_combo_trigger[3].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T30,T32
0	1	Covered	T1,T5,T6
1	0	Covered	T30,T32,T42

 LINE       106
 SUB-EXPRESSION (gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T30,T32
1	0	Not Covered
1	1	Covered	T30,T32,T42

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[0].cfg_in_sel) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T5,T6

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[1].cfg_in_sel) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T13,T17
1	Covered	T1,T5,T6

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[2].cfg_in_sel) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T13,T17
1	Covered	T1,T5,T6

 LINE       111
 EXPRESSION ((in & gen_combo_trigger[3].cfg_in_sel) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T13,T17
1	Covered	T1,T5,T6