Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T30,T32
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T17,T30,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T17,T30,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T17,T30,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T30,T32
1	0	Covered	T30,T32,T37
1	1	Covered	T17,T30,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T30,T32
0	1	Covered	T17,T37,T54
1	0	Covered	T37,T54,T36

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T32,T42
0	1	Covered	T30,T32,T42
1	0	Covered	T282

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T32,T42
1	-	Covered	T30,T32,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T30,T32
DetectSt	168	Covered	T17,T30,T32
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T30,T32,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T30,T32
DebounceSt->IdleSt	163	Covered	T116,T254,T255
DetectSt->IdleSt	186	Covered	T17,T37,T54
DetectSt->StableSt	191	Covered	T30,T32,T42
IdleSt->DebounceSt	148	Covered	T17,T30,T32
StableSt->IdleSt	206	Covered	T30,T32,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T30,T32
0	1	Covered	T17,T30,T32
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T30,T32
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T17,T30,T32
IdleSt	0	-	-	-	-	-	-	Covered	T17,T30,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T108,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T30,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T116,T254,T255
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T30,T32
DetectSt	-	-	-	-	1	-	-	Covered	T17,T37,T54
DetectSt	-	-	-	-	0	1	-	Covered	T30,T32,T42
DetectSt	-	-	-	-	0	0	-	Covered	T17,T30,T32
StableSt	-	-	-	-	-	-	1	Covered	T30,T32,T42
StableSt	-	-	-	-	-	-	0	Covered	T30,T32,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	2978	0	0
CntIncr_A	7903577	113168	0	0
CntNoWrap_A	7903577	7248109	0	0
DetectStDropOut_A	7903577	418	0	0
DetectedOut_A	7903577	63613	0	0
DetectedPulseOut_A	7903577	823	0	0
DisabledIdleSt_A	7903577	6748244	0	0
DisabledNoDetection_A	7903577	6750349	0	0
EnterDebounceSt_A	7903577	1516	0	0
EnterDetectSt_A	7903577	1463	0	0
EnterStableSt_A	7903577	823	0	0
PulseIsPulse_A	7903577	823	0	0
StayInStableSt	7903577	62703	0	0
gen_high_event_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	734	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	2978	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	52	0	0
T18	502	0	0	0
T30	0	16	0	0
T32	0	18	0	0
T36	0	48	0	0
T37	0	34	0	0
T42	0	8	0	0
T48	504	0	0	0
T54	0	34	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	30	0	0
T75	0	54	0	0
T76	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	113168	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	1428	0	0
T18	502	0	0	0
T30	0	400	0	0
T32	0	567	0	0
T36	0	1756	0	0
T37	0	1607	0	0
T42	0	432	0	0
T48	504	0	0	0
T54	0	1170	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	846	0	0
T75	0	1217	0	0
T76	0	1656	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7248109	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4914	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	418	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	26	0	0
T18	502	0	0	0
T36	0	9	0	0
T37	0	5	0	0
T48	504	0	0	0
T54	0	12	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	15	0	0
T75	0	27	0	0
T200	0	27	0	0
T256	0	14	0	0
T257	0	4	0	0
T264	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	63613	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	1096	0	0
T31	470	0	0	0
T32	0	424	0	0
T42	0	41	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	1032	0	0
T116	0	63	0	0
T119	0	855	0	0
T138	0	1406	0	0
T189	0	486	0	0
T190	0	1287	0	0
T254	0	65	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	823	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	8	0	0
T31	470	0	0	0
T32	0	9	0	0
T42	0	4	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	24	0	0
T116	0	2	0	0
T119	0	3	0	0
T138	0	25	0	0
T189	0	8	0	0
T190	0	13	0	0
T254	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6748244	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	2014	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6750349	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	2014	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	1516	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	26	0	0
T18	502	0	0	0
T30	0	8	0	0
T32	0	9	0	0
T36	0	24	0	0
T37	0	17	0	0
T42	0	4	0	0
T48	504	0	0	0
T54	0	17	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	15	0	0
T75	0	27	0	0
T76	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	1463	0	0
T3	596	0	0	0
T4	1937	0	0	0
T7	850	0	0	0
T17	5367	26	0	0
T18	502	0	0	0
T30	0	8	0	0
T32	0	9	0	0
T36	0	24	0	0
T37	0	17	0	0
T42	0	4	0	0
T48	504	0	0	0
T54	0	17	0	0
T59	1557	0	0	0
T70	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T74	0	15	0	0
T75	0	27	0	0
T76	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	823	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	8	0	0
T31	470	0	0	0
T32	0	9	0	0
T42	0	4	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	24	0	0
T116	0	2	0	0
T119	0	3	0	0
T138	0	25	0	0
T189	0	8	0	0
T190	0	13	0	0
T254	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	823	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	8	0	0
T31	470	0	0	0
T32	0	9	0	0
T42	0	4	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	24	0	0
T116	0	2	0	0
T119	0	3	0	0
T138	0	25	0	0
T189	0	8	0	0
T190	0	13	0	0
T254	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	62703	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	1086	0	0
T31	470	0	0	0
T32	0	414	0	0
T42	0	37	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	1006	0	0
T116	0	61	0	0
T119	0	850	0	0
T138	0	1378	0	0
T189	0	477	0	0
T190	0	1272	0	0
T254	0	58	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	734	0	0
T27	766	0	0	0
T28	12055	0	0	0
T30	20486	6	0	0
T31	470	0	0	0
T32	0	8	0	0
T42	0	4	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	22	0	0
T116	0	2	0	0
T119	0	1	0	0
T138	0	22	0	0
T189	0	7	0	0
T190	0	11	0	0
T254	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T13,T17
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T17
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T13,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T13,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T11,T12,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T11
1	0	Covered	T1,T5,T17
1	1	Covered	T13,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T30
0	1	Covered	T11,T267,T270
1	0	Covered	T108,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T30,T43
0	1	Covered	T12,T30,T43
1	0	Covered	T109

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T30,T43
1	-	Covered	T12,T30,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T11,T12
DetectSt	168	Covered	T11,T12,T30
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T12,T30,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T12,T30
DebounceSt->IdleSt	163	Covered	T13,T11,T12
DetectSt->IdleSt	186	Covered	T11,T108,T267
DetectSt->StableSt	191	Covered	T12,T30,T43
IdleSt->DebounceSt	148	Covered	T13,T11,T12
StableSt->IdleSt	206	Covered	T12,T30,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T11,T12
0	1	Covered	T13,T11,T12
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T30
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T12,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T11,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T11,T12
DetectSt	-	-	-	-	1	-	-	Covered	T11,T108,T267
DetectSt	-	-	-	-	0	1	-	Covered	T12,T30,T43
DetectSt	-	-	-	-	0	0	-	Covered	T11,T12,T30
StableSt	-	-	-	-	-	-	1	Covered	T12,T30,T43
StableSt	-	-	-	-	-	-	0	Covered	T12,T30,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	743	0	0
CntIncr_A	7903577	47840	0	0
CntNoWrap_A	7903577	7250344	0	0
DetectStDropOut_A	7903577	40	0	0
DetectedOut_A	7903577	14075	0	0
DetectedPulseOut_A	7903577	308	0	0
DisabledIdleSt_A	7903577	6911455	0	0
DisabledNoDetection_A	7903577	6913147	0	0
EnterDebounceSt_A	7903577	391	0	0
EnterDetectSt_A	7903577	352	0	0
EnterStableSt_A	7903577	308	0	0
PulseIsPulse_A	7903577	308	0	0
StayInStableSt	7903577	13738	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	275	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	743	0	0
T2	1099	0	0	0
T3	596	0	0	0
T11	0	5	0	0
T12	0	3	0	0
T13	5067	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	4	0	0
T32	0	2	0	0
T43	0	13	0	0
T48	504	0	0	0
T70	502	0	0	0
T76	0	4	0	0
T107	0	8	0	0
T119	0	4	0	0
T138	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	47840	0	0
T2	1099	0	0	0
T3	596	0	0	0
T11	0	436	0	0
T12	0	170	0	0
T13	5067	35	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	152	0	0
T32	0	42	0	0
T43	0	582	0	0
T48	504	0	0	0
T70	502	0	0	0
T76	0	130	0	0
T107	0	148	0	0
T119	0	558	0	0
T138	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7250344	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4665	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	40	0	0
T11	12474	2	0	0
T12	22676	0	0	0
T27	766	0	0	0
T30	20486	0	0	0
T43	20986	0	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T91	0	2	0	0
T125	0	11	0	0
T129	0	2	0	0
T225	0	6	0	0
T267	0	2	0	0
T270	0	7	0	0
T283	0	2	0	0
T284	0	4	0	0
T285	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	14075	0	0
T12	22676	16	0	0
T27	766	0	0	0
T30	20486	96	0	0
T31	470	0	0	0
T32	0	32	0	0
T43	20986	353	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	190	0	0
T107	0	17	0	0
T119	0	182	0	0
T138	0	120	0	0
T139	0	731	0	0
T189	0	20	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	308	0	0
T12	22676	1	0	0
T27	766	0	0	0
T30	20486	2	0	0
T31	470	0	0	0
T32	0	1	0	0
T43	20986	6	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	2	0	0
T107	0	4	0	0
T119	0	2	0	0
T138	0	2	0	0
T139	0	10	0	0
T189	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6911455	0	0
T1	25831	20144	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	2014	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6913147	0	0
T1	25831	20144	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	2014	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	391	0	0
T2	1099	0	0	0
T3	596	0	0	0
T11	0	3	0	0
T12	0	2	0	0
T13	5067	1	0	0
T14	427	0	0	0
T15	508	0	0	0
T16	502	0	0	0
T17	5367	0	0	0
T18	502	0	0	0
T30	0	2	0	0
T32	0	1	0	0
T43	0	7	0	0
T48	504	0	0	0
T70	502	0	0	0
T76	0	2	0	0
T107	0	4	0	0
T119	0	2	0	0
T138	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	352	0	0
T11	12474	2	0	0
T12	22676	1	0	0
T27	766	0	0	0
T30	20486	2	0	0
T32	0	1	0	0
T43	20986	6	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	2	0	0
T107	0	4	0	0
T119	0	2	0	0
T138	0	2	0	0
T139	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	308	0	0
T12	22676	1	0	0
T27	766	0	0	0
T30	20486	2	0	0
T31	470	0	0	0
T32	0	1	0	0
T43	20986	6	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	2	0	0
T107	0	4	0	0
T119	0	2	0	0
T138	0	2	0	0
T139	0	10	0	0
T189	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	308	0	0
T12	22676	1	0	0
T27	766	0	0	0
T30	20486	2	0	0
T31	470	0	0	0
T32	0	1	0	0
T43	20986	6	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	2	0	0
T107	0	4	0	0
T119	0	2	0	0
T138	0	2	0	0
T139	0	10	0	0
T189	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	13738	0	0
T12	22676	15	0	0
T27	766	0	0	0
T30	20486	94	0	0
T31	470	0	0	0
T32	0	31	0	0
T43	20986	347	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	188	0	0
T107	0	13	0	0
T119	0	178	0	0
T138	0	117	0	0
T139	0	721	0	0
T189	0	18	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	275	0	0
T12	22676	1	0	0
T27	766	0	0	0
T30	20486	2	0	0
T31	470	0	0	0
T32	0	1	0	0
T43	20986	6	0	0
T49	624	0	0	0
T50	305356	0	0	0
T51	414670	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T76	0	2	0	0
T107	0	4	0	0
T138	0	1	0	0
T139	0	10	0	0
T141	0	13	0	0
T190	0	1	0	0