Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T19,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T5,T19,T2

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T19,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T2
1	0	Covered	T4,T5,T21
1	1	Covered	T5,T19,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T2,T42
0	1	Covered	T5
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T2,T42
0	1	Covered	T19,T2,T42
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T2,T42
1	-	Covered	T19,T2,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T19,T2
DetectSt	168	Covered	T5,T19,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T19,T2,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T19,T2
DebounceSt->IdleSt	163	Covered	T19,T42,T45
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T19,T2,T42
IdleSt->DebounceSt	148	Covered	T5,T19,T2
StableSt->IdleSt	206	Covered	T19,T2,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T19,T2
0	1	Covered	T5,T19,T2
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T19,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T19,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T101
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T19,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T42,T45
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T19,T2
DetectSt	-	-	-	-	1	-	-	Covered	T5
DetectSt	-	-	-	-	0	1	-	Covered	T19,T2,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T2,T42
StableSt	-	-	-	-	-	-	0	Covered	T19,T2,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	268	0	0
CntIncr_A	6698738	167715	0	0
CntNoWrap_A	6698738	6029723	0	0
DetectStDropOut_A	6698738	1	0	0
DetectedOut_A	6698738	882	0	0
DetectedPulseOut_A	6698738	122	0	0
DisabledIdleSt_A	6698738	5855902	0	0
DisabledNoDetection_A	6698738	5858088	0	0
EnterDebounceSt_A	6698738	150	0	0
EnterDetectSt_A	6698738	123	0	0
EnterStableSt_A	6698738	122	0	0
PulseIsPulse_A	6698738	122	0	0
StayInStableSt	6698738	760	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6698738	6915	0	0
gen_low_level_sva.LowLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	121	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	268	0	0
T1	1581	0	0	0
T2	0	2	0	0
T5	3029	2	0	0
T6	405	0	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	0	5	0	0
T21	1360	0	0	0
T22	9912	0	0	0
T35	0	4	0	0
T42	0	3	0	0
T43	0	6	0	0
T44	0	4	0	0
T45	0	5	0	0
T46	0	2	0	0
T116	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	167715	0	0
T1	1581	0	0	0
T2	0	48	0	0
T5	3029	25	0	0
T6	405	0	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	0	228	0	0
T21	1360	0	0	0
T22	9912	0	0	0
T35	0	84	0	0
T42	0	141	0	0
T43	0	182	0	0
T44	0	53	0	0
T45	0	101	0	0
T46	0	75	0	0
T116	0	16	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029723	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	622	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1	0	0
T1	1581	0	0	0
T5	3029	1	0	0
T6	405	0	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T21	1360	0	0	0
T22	9912	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	882	0	0
T2	5129	6	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	0	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T19	738	9	0	0
T20	527	0	0	0
T35	0	12	0	0
T42	0	12	0	0
T43	0	13	0	0
T44	0	7	0	0
T45	0	19	0	0
T46	0	12	0	0
T47	511	0	0	0
T48	522	0	0	0
T86	0	2	0	0
T116	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	122	0	0
T2	5129	1	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	0	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T19	738	2	0	0
T20	527	0	0	0
T35	0	2	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T86	0	1	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5855902	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	568	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5858088	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	573	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	150	0	0
T1	1581	0	0	0
T2	0	1	0	0
T5	3029	1	0	0
T6	405	0	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	0	3	0	0
T21	1360	0	0	0
T22	9912	0	0	0
T35	0	2	0	0
T42	0	2	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	0	3	0	0
T46	0	1	0	0
T116	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	123	0	0
T1	1581	0	0	0
T2	0	1	0	0
T5	3029	1	0	0
T6	405	0	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	0	2	0	0
T21	1360	0	0	0
T22	9912	0	0	0
T35	0	2	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T116	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	122	0	0
T2	5129	1	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	0	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T19	738	2	0	0
T20	527	0	0	0
T35	0	2	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T86	0	1	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	122	0	0
T2	5129	1	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	0	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T19	738	2	0	0
T20	527	0	0	0
T35	0	2	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T86	0	1	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	760	0	0
T2	5129	5	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	0	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T19	738	7	0	0
T20	527	0	0	0
T35	0	10	0	0
T42	0	11	0	0
T43	0	10	0	0
T44	0	5	0	0
T45	0	17	0	0
T46	0	11	0	0
T47	511	0	0	0
T48	522	0	0	0
T86	0	1	0	0
T116	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6915	0	0
T1	1581	8	0	0
T4	510	5	0	0
T5	3029	22	0	0
T6	405	0	0	0
T14	503	5	0	0
T15	416	3	0	0
T16	17916	29	0	0
T17	13266	11	0	0
T18	0	3	0	0
T21	1360	2	0	0
T22	9912	28	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	121	0	0
T2	5129	1	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	0	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T19	738	2	0	0
T20	527	0	0	0
T35	0	2	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T86	0	1	0	0
T116	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T10
1	0	Covered	T4,T5,T21
1	1	Covered	T1,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T10
0	1	Covered	T113,T114,T115
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T10
0	1	Unreachable
1	0	Covered	T1,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T10
DetectSt	168	Covered	T1,T8,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T10
DebounceSt->IdleSt	163	Covered	T35,T68,T69
DetectSt->IdleSt	186	Covered	T113,T114,T115
DetectSt->StableSt	191	Covered	T1,T8,T10
IdleSt->DebounceSt	148	Covered	T1,T8,T10
StableSt->IdleSt	206	Covered	T1,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T10
0	1	Covered	T1,T8,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T101
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T68,T69
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T113,T114,T115
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	167	0	0
CntIncr_A	6698738	152119	0	0
CntNoWrap_A	6698738	6029824	0	0
DetectStDropOut_A	6698738	18	0	0
DetectedOut_A	6698738	121298	0	0
DetectedPulseOut_A	6698738	40	0	0
DisabledIdleSt_A	6698738	4827179	0	0
DisabledNoDetection_A	6698738	4829407	0	0
EnterDebounceSt_A	6698738	111	0	0
EnterDetectSt_A	6698738	58	0	0
EnterStableSt_A	6698738	40	0	0
PulseIsPulse_A	6698738	40	0	0
StayInStableSt	6698738	121258	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6698738	6915	0	0
gen_low_level_sva.LowLevelEvent_A	6698738	6032222	0	0
gen_sticky_sva.StableStDropOut_A	6698738	526375	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	167	0	0
T1	1581	4	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	2	0	0
T10	0	2	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	2	0	0
T52	0	2	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	5	0	0
T69	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	152119	0	0
T1	1581	46	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	72	0	0
T10	0	69	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	32	0	0
T52	0	42	0	0
T65	0	13	0	0
T66	0	88	0	0
T67	0	26	0	0
T68	0	80	0	0
T69	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029824	0	0
T1	1581	1176	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	18	0	0
T102	23489	0	0	0
T113	914	3	0	0
T114	0	2	0	0
T115	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	2	0	0
T149	0	4	0	0
T150	0	3	0	0
T151	488	0	0	0
T152	687	0	0	0
T153	505	0	0	0
T154	613	0	0	0
T155	5768	0	0	0
T156	492	0	0	0
T157	524	0	0	0
T158	750	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	121298	0	0
T1	1581	302	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	3	0	0
T10	0	162	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T52	0	60	0	0
T65	0	85	0	0
T66	0	38	0	0
T67	0	160	0	0
T142	0	133	0	0
T143	0	905	0	0
T144	0	225	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	40	0	0
T1	1581	2	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T52	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	4827179	0	0
T1	1581	53	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	4829407	0	0
T1	1581	54	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	111	0	0
T1	1581	2	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	2	0	0
T52	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	5	0	0
T69	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	58	0	0
T1	1581	2	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T52	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	40	0	0
T1	1581	2	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T52	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	40	0	0
T1	1581	2	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T52	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	121258	0	0
T1	1581	300	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	2	0	0
T10	0	161	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T52	0	59	0	0
T65	0	84	0	0
T66	0	37	0	0
T67	0	159	0	0
T142	0	132	0	0
T143	0	903	0	0
T144	0	224	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6915	0	0
T1	1581	8	0	0
T4	510	5	0	0
T5	3029	22	0	0
T6	405	0	0	0
T14	503	5	0	0
T15	416	3	0	0
T16	17916	29	0	0
T17	13266	11	0	0
T18	0	3	0	0
T21	1360	2	0	0
T22	9912	28	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	526375	0	0
T1	1581	743	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	50	0	0
T10	0	46	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T52	0	108	0	0
T65	0	389	0	0
T66	0	37329	0	0
T67	0	449	0	0
T142	0	477	0	0
T143	0	152	0	0
T144	0	510	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T21
1	1	Covered	T4,T5,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T10
1	0	Covered	T4,T5,T21
1	1	Covered	T1,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T52
0	1	Covered	T10,T111,T112
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T52
0	1	Unreachable
1	0	Covered	T1,T8,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T10
DetectSt	168	Covered	T1,T8,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T8,T52

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T10
DebounceSt->IdleSt	163	Covered	T10,T109,T159
DetectSt->IdleSt	186	Covered	T10,T111,T112
DetectSt->StableSt	191	Covered	T1,T8,T52
IdleSt->DebounceSt	148	Covered	T1,T8,T10
StableSt->IdleSt	206	Covered	T1,T8,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T10
0	1	Covered	T1,T8,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T101
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T109,T159
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T10,T111,T112
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T52
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T52
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	156	0	0
CntIncr_A	6698738	28700	0	0
CntNoWrap_A	6698738	6029835	0	0
DetectStDropOut_A	6698738	12	0	0
DetectedOut_A	6698738	76531	0	0
DetectedPulseOut_A	6698738	54	0	0
DisabledIdleSt_A	6698738	4827179	0	0
DisabledNoDetection_A	6698738	4829407	0	0
EnterDebounceSt_A	6698738	92	0	0
EnterDetectSt_A	6698738	66	0	0
EnterStableSt_A	6698738	54	0	0
PulseIsPulse_A	6698738	54	0	0
StayInStableSt	6698738	76477	0	0
gen_high_level_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_sticky_sva.StableStDropOut_A	6698738	987393	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	156	0	0
T1	1581	4	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	2	0	0
T10	0	3	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	2	0	0
T52	0	2	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	4	0	0
T69	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	28700	0	0
T1	1581	92	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	26	0	0
T10	0	172	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	59	0	0
T52	0	46	0	0
T65	0	46	0	0
T66	0	73	0	0
T67	0	68	0	0
T68	0	112	0	0
T69	0	82	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029835	0	0
T1	1581	1176	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	12	0	0
T10	254367	1	0	0
T11	696	0	0	0
T26	507	0	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T111	0	1	0	0
T112	0	4	0	0
T115	0	1	0	0
T145	507	0	0	0
T160	0	4	0	0
T161	0	1	0	0
T162	436	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	76531	0	0
T1	1581	614	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	14	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	146	0	0
T52	0	127	0	0
T65	0	335	0	0
T66	0	39	0	0
T67	0	277	0	0
T68	0	403	0	0
T69	0	405	0	0
T142	0	464	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	54	0	0
T1	1581	2	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	1	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	1	0	0
T52	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T69	0	1	0	0
T142	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	4827179	0	0
T1	1581	53	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	4829407	0	0
T1	1581	54	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	92	0	0
T1	1581	2	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	1	0	0
T10	0	2	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	1	0	0
T52	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T69	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	66	0	0
T1	1581	2	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	1	0	0
T52	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T69	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	54	0	0
T1	1581	2	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	1	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	1	0	0
T52	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T69	0	1	0	0
T142	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	54	0	0
T1	1581	2	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	1	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	1	0	0
T52	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T69	0	1	0	0
T142	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	76477	0	0
T1	1581	612	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	13	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	145	0	0
T52	0	126	0	0
T65	0	334	0	0
T66	0	38	0	0
T67	0	276	0	0
T68	0	401	0	0
T69	0	404	0	0
T142	0	463	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	987393	0	0
T1	1581	379	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	91	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	54	0	0
T52	0	46	0	0
T65	0	101	0	0
T66	0	37342	0	0
T67	0	300	0	0
T68	0	128	0	0
T69	0	96	0	0
T142	0	95	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T10,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T10
1	0	Covered	T4,T5,T21
1	1	Covered	T1,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T35
0	1	Covered	T68,T109,T103
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T35
0	1	Unreachable
1	0	Covered	T8,T10,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T10
DetectSt	168	Covered	T8,T10,T35
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T10,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T35
DebounceSt->IdleSt	163	Covered	T1,T52,T66
DetectSt->IdleSt	186	Covered	T68,T109,T103
DetectSt->StableSt	191	Covered	T8,T10,T35
IdleSt->DebounceSt	148	Covered	T1,T8,T10
StableSt->IdleSt	206	Covered	T8,T10,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T10
0	1	Covered	T1,T8,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T35
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T101
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T52,T66
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T68,T109,T103
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T10,T35
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	166	0	0
CntIncr_A	6698738	254986	0	0
CntNoWrap_A	6698738	6029825	0	0
DetectStDropOut_A	6698738	13	0	0
DetectedOut_A	6698738	583611	0	0
DetectedPulseOut_A	6698738	43	0	0
DisabledIdleSt_A	6698738	4827179	0	0
DisabledNoDetection_A	6698738	4829407	0	0
EnterDebounceSt_A	6698738	112	0	0
EnterDetectSt_A	6698738	56	0	0
EnterStableSt_A	6698738	43	0	0
PulseIsPulse_A	6698738	43	0	0
StayInStableSt	6698738	583568	0	0
gen_high_event_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_high_level_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_sticky_sva.StableStDropOut_A	6698738	216198	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	166	0	0
T1	1581	8	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	2	0	0
T10	0	2	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	2	0	0
T52	0	2	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	0	5	0	0
T68	0	9	0	0
T69	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	254986	0	0
T1	1581	672	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	82	0	0
T10	0	27	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	77	0	0
T52	0	168	0	0
T65	0	81	0	0
T66	0	37449	0	0
T67	0	450	0	0
T68	0	120	0	0
T69	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029825	0	0
T1	1581	1172	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	13	0	0
T68	1486	4	0	0
T69	1330	0	0	0
T103	0	1	0	0
T109	0	2	0	0
T113	0	3	0	0
T119	6607	0	0	0
T120	6538	0	0	0
T142	2461	0	0	0
T146	0	3	0	0
T163	734	0	0	0
T164	402	0	0	0
T165	496	0	0	0
T166	680	0	0	0
T167	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	583611	0	0
T8	2143	24	0	0
T9	27936	0	0	0
T10	254367	32	0	0
T11	696	0	0	0
T26	507	0	0	0
T35	0	121	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T65	0	330	0	0
T69	0	224	0	0
T87	402	0	0	0
T109	0	66	0	0
T111	0	314	0	0
T142	0	154	0	0
T143	0	289	0	0
T144	0	154	0	0
T145	507	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	43	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	1	0	0
T11	696	0	0	0
T26	507	0	0	0
T35	0	1	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T65	0	1	0	0
T69	0	1	0	0
T87	402	0	0	0
T109	0	1	0	0
T111	0	2	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	507	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	4827179	0	0
T1	1581	53	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	4829407	0	0
T1	1581	54	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	112	0	0
T1	1581	8	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T35	0	1	0	0
T52	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	5	0	0
T68	0	5	0	0
T69	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	56	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	1	0	0
T11	696	0	0	0
T26	507	0	0	0
T35	0	1	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T65	0	1	0	0
T68	0	4	0	0
T69	0	1	0	0
T87	402	0	0	0
T111	0	2	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	507	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	43	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	1	0	0
T11	696	0	0	0
T26	507	0	0	0
T35	0	1	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T65	0	1	0	0
T69	0	1	0	0
T87	402	0	0	0
T109	0	1	0	0
T111	0	2	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	507	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	43	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	1	0	0
T11	696	0	0	0
T26	507	0	0	0
T35	0	1	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T65	0	1	0	0
T69	0	1	0	0
T87	402	0	0	0
T109	0	1	0	0
T111	0	2	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	507	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	583568	0	0
T8	2143	23	0	0
T9	27936	0	0	0
T10	254367	31	0	0
T11	696	0	0	0
T26	507	0	0	0
T35	0	120	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T65	0	329	0	0
T69	0	223	0	0
T87	402	0	0	0
T109	0	65	0	0
T111	0	312	0	0
T142	0	153	0	0
T143	0	287	0	0
T144	0	153	0	0
T145	507	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	216198	0	0
T8	2143	31	0	0
T9	27936	0	0	0
T10	254367	223	0	0
T11	696	0	0	0
T26	507	0	0	0
T35	0	65	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T65	0	80	0	0
T69	0	335	0	0
T87	402	0	0	0
T109	0	57	0	0
T111	0	281	0	0
T142	0	467	0	0
T143	0	909	0	0
T144	0	591	0	0
T145	507	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T13,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T11,T13,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T13,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T13
1	0	Covered	T4,T5,T6
1	1	Covered	T11,T13,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T32
0	1	Not Covered
1	0	Covered	T49

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T32
0	1	Covered	T13,T32,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T13,T32
1	-	Covered	T13,T32,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T13,T32
DetectSt	168	Covered	T11,T13,T32
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T13,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T13,T32
DebounceSt->IdleSt	163	Covered	T13,T168,T101
DetectSt->IdleSt	186	Covered	T49
DetectSt->StableSt	191	Covered	T11,T13,T32
IdleSt->DebounceSt	148	Covered	T11,T13,T32
StableSt->IdleSt	206	Covered	T13,T32,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T13,T32
0	1	Covered	T11,T13,T32
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T13,T32
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T13,T32
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T101
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T13,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T168,T169
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T13,T32
DetectSt	-	-	-	-	1	-	-	Covered	T49
DetectSt	-	-	-	-	0	1	-	Covered	T11,T13,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T32,T33
StableSt	-	-	-	-	-	-	0	Covered	T11,T13,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	76	0	0
CntIncr_A	6698738	1934	0	0
CntNoWrap_A	6698738	6029915	0	0
DetectStDropOut_A	6698738	0	0	0
DetectedOut_A	6698738	2489	0	0
DetectedPulseOut_A	6698738	35	0	0
DisabledIdleSt_A	6698738	6013360	0	0
DisabledNoDetection_A	6698738	6015548	0	0
EnterDebounceSt_A	6698738	40	0	0
EnterDetectSt_A	6698738	36	0	0
EnterStableSt_A	6698738	35	0	0
PulseIsPulse_A	6698738	35	0	0
StayInStableSt	6698738	2435	0	0
gen_high_level_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	76	0	0
T11	696	2	0	0
T13	0	3	0	0
T26	507	0	0	0
T32	0	4	0	0
T33	0	4	0	0
T35	0	4	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	4	0	0
T87	402	0	0	0
T133	0	4	0	0
T145	507	0	0	0
T162	436	0	0	0
T170	0	2	0	0
T171	524	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1934	0	0
T11	696	41	0	0
T13	0	196	0	0
T26	507	0	0	0
T32	0	84	0	0
T33	0	24	0	0
T35	0	40	0	0
T36	0	99	0	0
T38	0	71	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	44	0	0
T87	402	0	0	0
T133	0	98	0	0
T145	507	0	0	0
T162	436	0	0	0
T170	0	51	0	0
T171	524	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029915	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	2489	0	0
T11	696	105	0	0
T13	0	88	0	0
T26	507	0	0	0
T32	0	84	0	0
T33	0	82	0	0
T35	0	79	0	0
T36	0	1	0	0
T38	0	180	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	82	0	0
T87	402	0	0	0
T133	0	55	0	0
T145	507	0	0	0
T162	436	0	0	0
T170	0	144	0	0
T171	524	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	35	0	0
T11	696	1	0	0
T13	0	1	0	0
T26	507	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	2	0	0
T87	402	0	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T170	0	1	0	0
T171	524	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6013360	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6015548	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	40	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	2	0	0
T87	402	0	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T170	0	1	0	0
T171	524	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	36	0	0
T11	696	1	0	0
T13	0	1	0	0
T26	507	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	2	0	0
T87	402	0	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T170	0	1	0	0
T171	524	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	35	0	0
T11	696	1	0	0
T13	0	1	0	0
T26	507	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	2	0	0
T87	402	0	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T170	0	1	0	0
T171	524	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	35	0	0
T11	696	1	0	0
T13	0	1	0	0
T26	507	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	2	0	0
T87	402	0	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T170	0	1	0	0
T171	524	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	2435	0	0
T11	696	103	0	0
T13	0	87	0	0
T26	507	0	0	0
T32	0	81	0	0
T33	0	79	0	0
T35	0	76	0	0
T38	0	178	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	80	0	0
T87	402	0	0	0
T133	0	52	0	0
T145	507	0	0	0
T162	436	0	0	0
T170	0	143	0	0
T171	524	0	0	0
T172	0	66	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	16	0	0
T13	1216	1	0	0
T29	29730	0	0	0
T30	14014	0	0	0
T31	26081	0	0	0
T32	840	1	0	0
T33	554	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T42	760	0	0	0
T52	666	0	0	0
T60	1883	0	0	0
T61	0	2	0	0
T133	0	1	0	0
T141	29230	0	0	0
T170	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T8,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T13
1	0	Covered	T4,T5,T21
1	1	Covered	T2,T8,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T13
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T13
0	1	Covered	T8,T13,T32
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T13
1	-	Covered	T8,T13,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T13
DetectSt	168	Covered	T2,T8,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T8,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T13
DebounceSt->IdleSt	163	Covered	T115,T174,T175
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T8,T13
IdleSt->DebounceSt	148	Covered	T2,T8,T13
StableSt->IdleSt	206	Covered	T8,T13,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T13
0	1	Covered	T2,T8,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T101
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T115,T175
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T13
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T13,T32
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	141	0	0
CntIncr_A	6698738	61658	0	0
CntNoWrap_A	6698738	6029850	0	0
DetectStDropOut_A	6698738	0	0	0
DetectedOut_A	6698738	5092	0	0
DetectedPulseOut_A	6698738	69	0	0
DisabledIdleSt_A	6698738	5895379	0	0
DisabledNoDetection_A	6698738	5897559	0	0
EnterDebounceSt_A	6698738	73	0	0
EnterDetectSt_A	6698738	69	0	0
EnterStableSt_A	6698738	69	0	0
PulseIsPulse_A	6698738	69	0	0
StayInStableSt	6698738	4994	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6698738	2626	0	0
gen_low_level_sva.LowLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	141	0	0
T2	5129	2	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	4	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	6	0	0
T20	527	0	0	0
T32	0	4	0	0
T33	0	4	0	0
T34	0	2	0	0
T37	0	4	0	0
T47	511	0	0	0
T48	522	0	0	0
T133	0	4	0	0
T172	0	4	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	61658	0	0
T2	5129	49	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	80	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	294	0	0
T20	527	0	0	0
T32	0	84	0	0
T33	0	24	0	0
T34	0	56	0	0
T37	0	98	0	0
T47	511	0	0	0
T48	522	0	0	0
T133	0	98	0	0
T172	0	20	0	0
T176	0	36	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029850	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5092	0	0
T2	5129	102	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	123	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	267	0	0
T20	527	0	0	0
T32	0	175	0	0
T33	0	12	0	0
T34	0	109	0	0
T37	0	89	0	0
T47	511	0	0	0
T48	522	0	0	0
T133	0	181	0	0
T172	0	93	0	0
T176	0	125	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	69	0	0
T2	5129	1	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	2	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	3	0	0
T20	527	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	2	0	0
T47	511	0	0	0
T48	522	0	0	0
T133	0	2	0	0
T172	0	2	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5895379	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5897559	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	73	0	0
T2	5129	1	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	2	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	3	0	0
T20	527	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	2	0	0
T47	511	0	0	0
T48	522	0	0	0
T133	0	2	0	0
T172	0	2	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	69	0	0
T2	5129	1	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	2	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	3	0	0
T20	527	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	2	0	0
T47	511	0	0	0
T48	522	0	0	0
T133	0	2	0	0
T172	0	2	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	69	0	0
T2	5129	1	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	2	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	3	0	0
T20	527	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	2	0	0
T47	511	0	0	0
T48	522	0	0	0
T133	0	2	0	0
T172	0	2	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	69	0	0
T2	5129	1	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	2	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	3	0	0
T20	527	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	2	0	0
T47	511	0	0	0
T48	522	0	0	0
T133	0	2	0	0
T172	0	2	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	4994	0	0
T2	5129	100	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	120	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	263	0	0
T20	527	0	0	0
T32	0	173	0	0
T33	0	10	0	0
T34	0	107	0	0
T37	0	86	0	0
T47	511	0	0	0
T48	522	0	0	0
T133	0	179	0	0
T172	0	90	0	0
T176	0	123	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	2626	0	0
T1	1581	0	0	0
T2	0	11	0	0
T4	510	3	0	0
T5	3029	16	0	0
T6	405	0	0	0
T8	0	10	0	0
T14	503	6	0	0
T15	416	2	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T20	0	4	0	0
T21	1360	3	0	0
T22	9912	0	0	0
T47	0	3	0	0
T48	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	39	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	2	0	0
T26	507	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T37	0	1	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T133	0	2	0	0
T145	507	0	0	0
T172	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	1	0	0