Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T21
1	1	Covered	T4,T5,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T32,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T32,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T32,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T32,T33
1	0	Covered	T4,T5,T21
1	1	Covered	T8,T32,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T32,T33
0	1	Covered	T178,T222
1	0	Covered	T49

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T32,T33
0	1	Covered	T32,T37,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T32,T33
1	-	Covered	T32,T37,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T32,T33
DetectSt	168	Covered	T8,T32,T33
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T32,T33
DebounceSt->IdleSt	163	Covered	T60,T135,T115
DetectSt->IdleSt	186	Covered	T178,T49,T222
DetectSt->StableSt	191	Covered	T8,T32,T33
IdleSt->DebounceSt	148	Covered	T8,T32,T33
StableSt->IdleSt	206	Covered	T8,T32,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T32,T33
0	1	Covered	T8,T32,T33
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T32,T33
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T32,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T101
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T32,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T60,T135,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T32,T33
DetectSt	-	-	-	-	1	-	-	Covered	T178,T49,T222
DetectSt	-	-	-	-	0	1	-	Covered	T8,T32,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T37,T36
StableSt	-	-	-	-	-	-	0	Covered	T8,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	130	0	0
CntIncr_A	6698738	61628	0	0
CntNoWrap_A	6698738	6029861	0	0
DetectStDropOut_A	6698738	2	0	0
DetectedOut_A	6698738	4513	0	0
DetectedPulseOut_A	6698738	59	0	0
DisabledIdleSt_A	6698738	5772399	0	0
DisabledNoDetection_A	6698738	5774579	0	0
EnterDebounceSt_A	6698738	68	0	0
EnterDetectSt_A	6698738	62	0	0
EnterStableSt_A	6698738	59	0	0
PulseIsPulse_A	6698738	59	0	0
StayInStableSt	6698738	4426	0	0
gen_high_level_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	130	0	0
T8	2143	2	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T26	507	0	0	0
T32	0	6	0	0
T33	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T60	0	1	0	0
T87	402	0	0	0
T133	0	4	0	0
T135	0	1	0	0
T145	507	0	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	61628	0	0
T8	2143	40	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T26	507	0	0	0
T32	0	126	0	0
T33	0	12	0	0
T35	0	20	0	0
T36	0	99	0	0
T37	0	98	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T60	0	90	0	0
T87	402	0	0	0
T133	0	98	0	0
T135	0	24	0	0
T145	507	0	0	0
T176	0	36	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029861	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	2	0	0
T178	24814	1	0	0
T183	616	0	0	0
T222	0	1	0	0
T223	419	0	0	0
T224	506	0	0	0
T225	509	0	0	0
T226	403	0	0	0
T227	411	0	0	0
T228	515	0	0	0
T229	502	0	0	0
T230	420	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	4513	0	0
T8	2143	41	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T26	507	0	0	0
T32	0	87	0	0
T33	0	114	0	0
T35	0	73	0	0
T36	0	268	0	0
T37	0	170	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	250	0	0
T133	0	82	0	0
T145	507	0	0	0
T176	0	124	0	0
T231	0	164	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	59	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T26	507	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	2	0	0
T133	0	2	0	0
T145	507	0	0	0
T176	0	1	0	0
T231	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5772399	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5774579	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	68	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T26	507	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T60	0	1	0	0
T87	402	0	0	0
T133	0	2	0	0
T135	0	1	0	0
T145	507	0	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	62	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T26	507	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	2	0	0
T133	0	2	0	0
T145	507	0	0	0
T176	0	1	0	0
T231	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	59	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T26	507	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	2	0	0
T133	0	2	0	0
T145	507	0	0	0
T176	0	1	0	0
T231	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	59	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T26	507	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	2	0	0
T133	0	2	0	0
T145	507	0	0	0
T176	0	1	0	0
T231	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	4426	0	0
T8	2143	39	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T26	507	0	0	0
T32	0	83	0	0
T33	0	112	0	0
T35	0	71	0	0
T36	0	267	0	0
T37	0	167	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	247	0	0
T133	0	79	0	0
T145	507	0	0	0
T176	0	122	0	0
T231	0	161	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	31	0	0
T29	29730	0	0	0
T30	14014	0	0	0
T31	26081	0	0	0
T32	840	2	0	0
T33	554	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T52	666	0	0	0
T58	489	0	0	0
T60	1883	0	0	0
T88	402	0	0	0
T110	0	1	0	0
T133	0	1	0	0
T141	29230	0	0	0
T178	0	1	0	0
T183	0	1	0	0
T204	0	1	0	0
T207	0	1	0	0
T231	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T11,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T11,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T11,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T11
1	0	Covered	T4,T5,T21
1	1	Covered	T10,T11,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T32
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T32
0	1	Covered	T10,T32,T172
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T11,T32
1	-	Covered	T10,T32,T172

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T11,T32
DetectSt	168	Covered	T10,T11,T32
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T11,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T11,T32
DebounceSt->IdleSt	163	Covered	T61,T101
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T11,T32
IdleSt->DebounceSt	148	Covered	T10,T11,T32
StableSt->IdleSt	206	Covered	T10,T32,T61

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T11,T32
0	1	Covered	T10,T11,T32
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T32
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T11,T32
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T101
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T11,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T61
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T11,T32
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T32,T172
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	86	0	0
CntIncr_A	6698738	40195	0	0
CntNoWrap_A	6698738	6029905	0	0
DetectStDropOut_A	6698738	0	0	0
DetectedOut_A	6698738	62064	0	0
DetectedPulseOut_A	6698738	42	0	0
DisabledIdleSt_A	6698738	5637390	0	0
DisabledNoDetection_A	6698738	5639571	0	0
EnterDebounceSt_A	6698738	44	0	0
EnterDetectSt_A	6698738	42	0	0
EnterStableSt_A	6698738	42	0	0
PulseIsPulse_A	6698738	42	0	0
StayInStableSt	6698738	62002	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6698738	6173	0	0
gen_low_level_sva.LowLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	86	0	0
T10	254367	2	0	0
T11	696	2	0	0
T26	507	0	0	0
T32	0	4	0	0
T36	0	2	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	3	0	0
T87	402	0	0	0
T135	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	2	0	0
T177	0	2	0	0
T178	0	4	0	0
T231	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	40195	0	0
T10	254367	36652	0	0
T11	696	41	0	0
T26	507	0	0	0
T32	0	84	0	0
T36	0	99	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	44	0	0
T87	402	0	0	0
T135	0	24	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	10	0	0
T177	0	52	0	0
T178	0	184	0	0
T231	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029905	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	62064	0	0
T10	254367	59740	0	0
T11	696	42	0	0
T26	507	0	0	0
T32	0	130	0	0
T36	0	42	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	60	0	0
T87	402	0	0	0
T135	0	44	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	6	0	0
T177	0	97	0	0
T178	0	80	0	0
T231	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	42	0	0
T10	254367	1	0	0
T11	696	1	0	0
T26	507	0	0	0
T32	0	2	0	0
T36	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	1	0	0
T87	402	0	0	0
T135	0	1	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0
T231	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5637390	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5639571	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	44	0	0
T10	254367	1	0	0
T11	696	1	0	0
T26	507	0	0	0
T32	0	2	0	0
T36	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	2	0	0
T87	402	0	0	0
T135	0	1	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0
T231	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	42	0	0
T10	254367	1	0	0
T11	696	1	0	0
T26	507	0	0	0
T32	0	2	0	0
T36	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	1	0	0
T87	402	0	0	0
T135	0	1	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0
T231	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	42	0	0
T10	254367	1	0	0
T11	696	1	0	0
T26	507	0	0	0
T32	0	2	0	0
T36	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	1	0	0
T87	402	0	0	0
T135	0	1	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0
T231	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	42	0	0
T10	254367	1	0	0
T11	696	1	0	0
T26	507	0	0	0
T32	0	2	0	0
T36	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	1	0	0
T87	402	0	0	0
T135	0	1	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0
T231	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	62002	0	0
T10	254367	59739	0	0
T11	696	40	0	0
T26	507	0	0	0
T32	0	128	0	0
T36	0	40	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T61	0	58	0	0
T87	402	0	0	0
T135	0	42	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	5	0	0
T177	0	96	0	0
T178	0	77	0	0
T231	0	2	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6173	0	0
T1	1581	0	0	0
T2	0	13	0	0
T3	0	32	0	0
T4	510	5	0	0
T5	3029	24	0	0
T6	405	0	0	0
T14	503	5	0	0
T15	416	2	0	0
T16	17916	22	0	0
T17	13266	15	0	0
T21	1360	2	0	0
T22	9912	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	21	0	0
T10	254367	1	0	0
T11	696	0	0	0
T26	507	0	0	0
T32	0	2	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T180	0	1	0	0
T184	0	1	0	0
T186	0	1	0	0
T207	0	1	0	0
T231	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T21
1	1	Covered	T4,T5,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T11,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T11,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T11,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T13
1	0	Covered	T4,T5,T21
1	1	Covered	T10,T11,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T13
0	1	Covered	T110
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T13
0	1	Covered	T10,T11,T13
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T11,T13
1	-	Covered	T10,T11,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T11,T13
DetectSt	168	Covered	T10,T11,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T11,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T11,T13
DebounceSt->IdleSt	163	Covered	T10,T133,T104
DetectSt->IdleSt	186	Covered	T110
DetectSt->StableSt	191	Covered	T10,T11,T13
IdleSt->DebounceSt	148	Covered	T10,T11,T13
StableSt->IdleSt	206	Covered	T10,T11,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T11,T13
0	1	Covered	T10,T11,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T11,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T101
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T11,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T133,T104
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T11,T13
DetectSt	-	-	-	-	1	-	-	Covered	T110
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T11,T13
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	145	0	0
CntIncr_A	6698738	171735	0	0
CntNoWrap_A	6698738	6029846	0	0
DetectStDropOut_A	6698738	1	0	0
DetectedOut_A	6698738	109464	0	0
DetectedPulseOut_A	6698738	68	0	0
DisabledIdleSt_A	6698738	5519620	0	0
DisabledNoDetection_A	6698738	5521801	0	0
EnterDebounceSt_A	6698738	76	0	0
EnterDetectSt_A	6698738	69	0	0
EnterStableSt_A	6698738	68	0	0
PulseIsPulse_A	6698738	68	0	0
StayInStableSt	6698738	109371	0	0
gen_high_level_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	42	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	145	0	0
T10	254367	5	0	0
T11	696	2	0	0
T13	0	4	0	0
T26	507	0	0	0
T32	0	4	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	4	0	0
T133	0	5	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	4	0	0
T177	0	4	0	0
T182	0	2	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	171735	0	0
T10	254367	109956	0	0
T11	696	41	0	0
T13	0	196	0	0
T26	507	0	0	0
T32	0	84	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	122	0	0
T133	0	147	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	20	0	0
T177	0	104	0	0
T182	0	15	0	0
T201	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029846	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1	0	0
T110	946	1	0	0
T122	5321	0	0	0
T232	13837	0	0	0
T233	15290	0	0	0
T234	8965	0	0	0
T235	525	0	0	0
T236	14871	0	0	0
T237	496	0	0	0
T238	525	0	0	0
T239	415	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	109464	0	0
T10	254367	43280	0	0
T11	696	105	0	0
T13	0	133	0	0
T26	507	0	0	0
T32	0	127	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	145	0	0
T133	0	125	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	104	0	0
T177	0	62	0	0
T182	0	43	0	0
T201	0	97	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	68	0	0
T10	254367	2	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T32	0	2	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	1	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	2	0	0
T177	0	2	0	0
T182	0	1	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5519620	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5521801	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	76	0	0
T10	254367	3	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T32	0	2	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	2	0	0
T133	0	3	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	2	0	0
T177	0	2	0	0
T182	0	1	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	69	0	0
T10	254367	2	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T32	0	2	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	2	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	2	0	0
T177	0	2	0	0
T182	0	1	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	68	0	0
T10	254367	2	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T32	0	2	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	1	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	2	0	0
T177	0	2	0	0
T182	0	1	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	68	0	0
T10	254367	2	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T32	0	2	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	1	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	2	0	0
T177	0	2	0	0
T182	0	1	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	109371	0	0
T10	254367	43278	0	0
T11	696	104	0	0
T13	0	131	0	0
T26	507	0	0	0
T32	0	124	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	144	0	0
T133	0	122	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	101	0	0
T177	0	59	0	0
T182	0	42	0	0
T201	0	95	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	42	0	0
T10	254367	2	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T32	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	1	0	0
T133	0	1	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	1	0	0
T177	0	1	0	0
T178	0	3	0	0
T182	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T11,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T11,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T11,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T11
1	0	Covered	T4,T5,T21
1	1	Covered	T10,T11,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T13
0	1	Covered	T104
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T13
0	1	Covered	T10,T13,T34
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T11,T13
1	-	Covered	T10,T13,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T11,T13
DetectSt	168	Covered	T10,T11,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T11,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T11,T13
DebounceSt->IdleSt	163	Covered	T187,T101,T169
DetectSt->IdleSt	186	Covered	T104
DetectSt->StableSt	191	Covered	T10,T11,T13
IdleSt->DebounceSt	148	Covered	T10,T11,T13
StableSt->IdleSt	206	Covered	T10,T13,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T11,T13
0	1	Covered	T10,T11,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T11,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T101
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T11,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T187,T169
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T11,T13
DetectSt	-	-	-	-	1	-	-	Covered	T104
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T13,T34
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	106	0	0
CntIncr_A	6698738	112796	0	0
CntNoWrap_A	6698738	6029885	0	0
DetectStDropOut_A	6698738	1	0	0
DetectedOut_A	6698738	3664	0	0
DetectedPulseOut_A	6698738	50	0	0
DisabledIdleSt_A	6698738	5518576	0	0
DisabledNoDetection_A	6698738	5520753	0	0
EnterDebounceSt_A	6698738	55	0	0
EnterDetectSt_A	6698738	51	0	0
EnterStableSt_A	6698738	50	0	0
PulseIsPulse_A	6698738	50	0	0
StayInStableSt	6698738	3590	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6698738	6169	0	0
gen_low_level_sva.LowLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	106	0	0
T10	254367	6	0	0
T11	696	2	0	0
T13	0	4	0	0
T26	507	0	0	0
T34	0	4	0	0
T35	0	2	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	4	0	0
T133	0	4	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	112796	0	0
T10	254367	109956	0	0
T11	696	41	0	0
T13	0	196	0	0
T26	507	0	0	0
T34	0	112	0	0
T35	0	20	0	0
T36	0	99	0	0
T38	0	71	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	122	0	0
T133	0	98	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029885	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1	0	0
T104	467645	1	0	0
T114	2528	0	0	0
T240	521	0	0	0
T241	684	0	0	0
T242	8049	0	0	0
T243	423	0	0	0
T244	45747	0	0	0
T245	507	0	0	0
T246	8132	0	0	0
T247	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	3664	0	0
T10	254367	120	0	0
T11	696	42	0	0
T13	0	137	0	0
T26	507	0	0	0
T34	0	81	0	0
T35	0	40	0	0
T36	0	142	0	0
T38	0	179	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	144	0	0
T133	0	84	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	56	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	50	0	0
T10	254367	3	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	2	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5518576	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5520753	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	55	0	0
T10	254367	3	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	2	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	51	0	0
T10	254367	3	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	2	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	50	0	0
T10	254367	3	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	2	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	50	0	0
T10	254367	3	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	2	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	3590	0	0
T10	254367	116	0	0
T11	696	40	0	0
T13	0	134	0	0
T26	507	0	0	0
T34	0	78	0	0
T35	0	38	0	0
T36	0	140	0	0
T38	0	178	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	141	0	0
T133	0	82	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	55	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6169	0	0
T1	1581	0	0	0
T2	0	11	0	0
T3	0	24	0	0
T4	510	5	0	0
T5	3029	19	0	0
T6	405	0	0	0
T14	503	6	0	0
T15	416	1	0	0
T16	17916	27	0	0
T17	13266	10	0	0
T21	1360	3	0	0
T22	9912	30	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	25	0	0
T10	254367	2	0	0
T11	696	0	0	0
T13	0	1	0	0
T26	507	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	2354	0	0	0
T50	861	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T110	0	1	0	0
T133	0	2	0	0
T145	507	0	0	0
T162	436	0	0	0
T172	0	1	0	0
T178	0	2	0	0
T187	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T21
1	1	Covered	T4,T5,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T8,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T13
1	0	Covered	T4,T5,T21
1	1	Covered	T2,T8,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T13
0	1	Covered	T8
1	0	Covered	T49

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T13
0	1	Covered	T13,T61,T206
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T13
1	-	Covered	T13,T61,T206

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T13
DetectSt	168	Covered	T2,T8,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T8,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T13
DebounceSt->IdleSt	163	Covered	T60,T34,T133
DetectSt->IdleSt	186	Covered	T8,T49
DetectSt->StableSt	191	Covered	T2,T8,T13
IdleSt->DebounceSt	148	Covered	T2,T8,T13
StableSt->IdleSt	206	Covered	T8,T13,T61

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T13
0	1	Covered	T2,T8,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T101
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T60,T34,T133
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T13
DetectSt	-	-	-	-	1	-	-	Covered	T8,T49
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T61,T206
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	123	0	0
CntIncr_A	6698738	3217	0	0
CntNoWrap_A	6698738	6029868	0	0
DetectStDropOut_A	6698738	1	0	0
DetectedOut_A	6698738	4863	0	0
DetectedPulseOut_A	6698738	56	0	0
DisabledIdleSt_A	6698738	6012843	0	0
DisabledNoDetection_A	6698738	6015021	0	0
EnterDebounceSt_A	6698738	65	0	0
EnterDetectSt_A	6698738	58	0	0
EnterStableSt_A	6698738	56	0	0
PulseIsPulse_A	6698738	56	0	0
StayInStableSt	6698738	4784	0	0
gen_high_level_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	123	0	0
T2	5129	2	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	4	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	4	0	0
T20	527	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T47	511	0	0	0
T48	522	0	0	0
T60	0	1	0	0
T61	0	4	0	0
T170	0	2	0	0
T206	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	3217	0	0
T2	5129	49	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	80	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	196	0	0
T20	527	0	0	0
T34	0	56	0	0
T35	0	20	0	0
T36	0	99	0	0
T47	511	0	0	0
T48	522	0	0	0
T60	0	90	0	0
T61	0	44	0	0
T170	0	51	0	0
T206	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029868	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T26	507	0	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T145	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	4863	0	0
T2	5129	101	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	82	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	131	0	0
T20	527	0	0	0
T35	0	161	0	0
T36	0	285	0	0
T47	511	0	0	0
T48	522	0	0	0
T61	0	94	0	0
T133	0	14	0	0
T170	0	229	0	0
T181	0	40	0	0
T206	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	56	0	0
T2	5129	1	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	2	0	0
T20	527	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T61	0	2	0	0
T133	0	1	0	0
T170	0	1	0	0
T181	0	1	0	0
T206	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6012843	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6015021	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	65	0	0
T2	5129	1	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	2	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	2	0	0
T20	527	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T60	0	1	0	0
T61	0	2	0	0
T170	0	1	0	0
T206	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	58	0	0
T2	5129	1	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	2	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	2	0	0
T20	527	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T61	0	2	0	0
T133	0	1	0	0
T170	0	1	0	0
T181	0	1	0	0
T206	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	56	0	0
T2	5129	1	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	2	0	0
T20	527	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T61	0	2	0	0
T133	0	1	0	0
T170	0	1	0	0
T181	0	1	0	0
T206	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	56	0	0
T2	5129	1	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	2	0	0
T20	527	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T61	0	2	0	0
T133	0	1	0	0
T170	0	1	0	0
T181	0	1	0	0
T206	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	4784	0	0
T2	5129	99	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	80	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T13	0	129	0	0
T20	527	0	0	0
T35	0	159	0	0
T36	0	283	0	0
T47	511	0	0	0
T48	522	0	0	0
T61	0	92	0	0
T133	0	13	0	0
T170	0	228	0	0
T172	0	93	0	0
T181	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	33	0	0
T13	1216	2	0	0
T29	29730	0	0	0
T30	14014	0	0	0
T31	26081	0	0	0
T32	840	0	0	0
T33	554	0	0	0
T42	760	0	0	0
T52	666	0	0	0
T60	1883	0	0	0
T61	0	2	0	0
T133	0	1	0	0
T141	29230	0	0	0
T170	0	1	0	0
T172	0	1	0	0
T178	0	2	0	0
T204	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T231	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T10
1	0	Covered	T4,T5,T21
1	1	Covered	T8,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T11
0	1	Not Covered
1	0	Covered	T49

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T11
0	1	Covered	T8,T10,T13
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T10,T11
1	-	Covered	T8,T10,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T11
DetectSt	168	Covered	T8,T10,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T11
DebounceSt->IdleSt	163	Covered	T172,T220,T101
DetectSt->IdleSt	186	Covered	T49
DetectSt->StableSt	191	Covered	T8,T10,T11
IdleSt->DebounceSt	148	Covered	T8,T10,T11
StableSt->IdleSt	206	Covered	T8,T10,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T10,T11
0	1	Covered	T8,T10,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T101
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T172,T220,T248
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T49
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T10,T13
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	88	0	0
CntIncr_A	6698738	40207	0	0
CntNoWrap_A	6698738	6029903	0	0
DetectStDropOut_A	6698738	0	0	0
DetectedOut_A	6698738	59777	0	0
DetectedPulseOut_A	6698738	41	0	0
DisabledIdleSt_A	6698738	5516396	0	0
DisabledNoDetection_A	6698738	5518570	0	0
EnterDebounceSt_A	6698738	46	0	0
EnterDetectSt_A	6698738	42	0	0
EnterStableSt_A	6698738	41	0	0
PulseIsPulse_A	6698738	41	0	0
StayInStableSt	6698738	59714	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6698738	6915	0	0
gen_low_level_sva.LowLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	88	0	0
T8	2143	2	0	0
T9	27936	0	0	0
T10	254367	2	0	0
T11	696	2	0	0
T13	0	4	0	0
T26	507	0	0	0
T33	0	2	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T145	507	0	0	0
T170	0	2	0	0
T172	0	1	0	0
T178	0	2	0	0
T183	0	6	0	0
T206	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	40207	0	0
T8	2143	40	0	0
T9	27936	0	0	0
T10	254367	36652	0	0
T11	696	41	0	0
T13	0	196	0	0
T26	507	0	0	0
T33	0	12	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T145	507	0	0	0
T170	0	51	0	0
T172	0	10	0	0
T178	0	92	0	0
T183	0	42	0	0
T206	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029903	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	59777	0	0
T8	2143	42	0	0
T9	27936	0	0	0
T10	254367	56926	0	0
T11	696	189	0	0
T13	0	139	0	0
T26	507	0	0	0
T33	0	6	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T145	507	0	0	0
T170	0	38	0	0
T178	0	265	0	0
T183	0	121	0	0
T206	0	45	0	0
T208	0	105	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	41	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	1	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T33	0	1	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T145	507	0	0	0
T170	0	1	0	0
T178	0	1	0	0
T183	0	3	0	0
T206	0	1	0	0
T208	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5516396	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5518570	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	46	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	1	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T33	0	1	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T145	507	0	0	0
T170	0	1	0	0
T172	0	1	0	0
T178	0	1	0	0
T183	0	3	0	0
T206	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	42	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	1	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T33	0	1	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T145	507	0	0	0
T170	0	1	0	0
T178	0	1	0	0
T183	0	3	0	0
T206	0	1	0	0
T208	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	41	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	1	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T33	0	1	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T145	507	0	0	0
T170	0	1	0	0
T178	0	1	0	0
T183	0	3	0	0
T206	0	1	0	0
T208	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	41	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	1	0	0
T11	696	1	0	0
T13	0	2	0	0
T26	507	0	0	0
T33	0	1	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T145	507	0	0	0
T170	0	1	0	0
T178	0	1	0	0
T183	0	3	0	0
T206	0	1	0	0
T208	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	59714	0	0
T8	2143	41	0	0
T9	27936	0	0	0
T10	254367	56925	0	0
T11	696	187	0	0
T13	0	136	0	0
T26	507	0	0	0
T33	0	5	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T145	507	0	0	0
T170	0	36	0	0
T178	0	263	0	0
T183	0	117	0	0
T206	0	43	0	0
T208	0	103	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6915	0	0
T1	1581	8	0	0
T4	510	5	0	0
T5	3029	22	0	0
T6	405	0	0	0
T14	503	5	0	0
T15	416	3	0	0
T16	17916	29	0	0
T17	13266	11	0	0
T18	0	3	0	0
T21	1360	2	0	0
T22	9912	28	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	19	0	0
T8	2143	1	0	0
T9	27936	0	0	0
T10	254367	1	0	0
T11	696	0	0	0
T13	0	1	0	0
T26	507	0	0	0
T33	0	1	0	0
T39	2354	0	0	0
T51	2114	0	0	0
T55	494	0	0	0
T87	402	0	0	0
T145	507	0	0	0
T183	0	2	0	0
T185	0	1	0	0
T186	0	2	0	0
T220	0	1	0	0
T249	0	1	0	0
T250	0	1	0	0