Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T22,T16,T3
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T16,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T16,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T16,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T16,T3
1	0	Covered	T22,T3,T9
1	1	Covered	T22,T16,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T16,T3
0	1	Covered	T16,T62,T63
1	0	Covered	T63,T120,T232

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T3,T9
0	1	Covered	T22,T3,T9
1	0	Covered	T251,T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T3,T9
1	-	Covered	T22,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T16,T3
DetectSt	168	Covered	T22,T16,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T22,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T16,T3
DebounceSt->IdleSt	163	Covered	T252,T253,T49
DetectSt->IdleSt	186	Covered	T16,T62,T63
DetectSt->StableSt	191	Covered	T22,T3,T9
IdleSt->DebounceSt	148	Covered	T22,T16,T3
StableSt->IdleSt	206	Covered	T22,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T22,T16,T3
0	1	Covered	T22,T16,T3
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T16,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T22,T16,T3
IdleSt	0	-	-	-	-	-	-	Covered	T22,T16,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T101
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T16,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T252,T253,T49
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T16,T3
DetectSt	-	-	-	-	1	-	-	Covered	T16,T62,T63
DetectSt	-	-	-	-	0	1	-	Covered	T22,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T22,T16,T3
StableSt	-	-	-	-	-	-	1	Covered	T22,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T22,T3,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	3091	0	0
CntIncr_A	6698738	111274	0	0
CntNoWrap_A	6698738	6026900	0	0
DetectStDropOut_A	6698738	328	0	0
DetectedOut_A	6698738	83103	0	0
DetectedPulseOut_A	6698738	1053	0	0
DisabledIdleSt_A	6698738	5543582	0	0
DisabledNoDetection_A	6698738	5545613	0	0
EnterDebounceSt_A	6698738	1562	0	0
EnterDetectSt_A	6698738	1529	0	0
EnterStableSt_A	6698738	1053	0	0
PulseIsPulse_A	6698738	1053	0	0
StayInStableSt	6698738	81942	0	0
gen_high_event_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_high_level_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	934	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	3091	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	24	0	0
T9	0	60	0	0
T12	0	44	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	24	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	48	0	0
T40	0	24	0	0
T41	0	24	0	0
T62	0	26	0	0
T63	0	48	0	0
T64	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	111274	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	576	0	0
T9	0	1890	0	0
T12	0	1342	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	3666	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	2112	0	0
T40	0	816	0	0
T41	0	684	0	0
T62	0	776	0	0
T63	0	1286	0	0
T64	0	793	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6026900	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17491	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9463	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	328	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T16	17916	12	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T47	511	0	0	0
T48	522	0	0	0
T62	0	13	0	0
T63	0	8	0	0
T108	0	7	0	0
T117	0	18	0	0
T120	0	14	0	0
T122	0	16	0	0
T123	0	9	0	0
T125	0	18	0	0
T126	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	83103	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	1262	0	0
T9	0	3381	0	0
T12	0	1831	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	2081	0	0
T40	0	761	0	0
T41	0	1632	0	0
T64	0	239	0	0
T105	0	1776	0	0
T254	0	861	0	0
T255	0	1427	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1053	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	12	0	0
T9	0	30	0	0
T12	0	22	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	24	0	0
T40	0	12	0	0
T41	0	12	0	0
T64	0	13	0	0
T105	0	36	0	0
T254	0	10	0	0
T255	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5543582	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	2014	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	2059	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5545613	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	2014	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	2059	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1562	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	12	0	0
T9	0	30	0	0
T12	0	22	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	12	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	24	0	0
T40	0	12	0	0
T41	0	12	0	0
T62	0	13	0	0
T63	0	24	0	0
T64	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1529	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	12	0	0
T9	0	30	0	0
T12	0	22	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	12	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	24	0	0
T40	0	12	0	0
T41	0	12	0	0
T62	0	13	0	0
T63	0	24	0	0
T64	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1053	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	12	0	0
T9	0	30	0	0
T12	0	22	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	24	0	0
T40	0	12	0	0
T41	0	12	0	0
T64	0	13	0	0
T105	0	36	0	0
T254	0	10	0	0
T255	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1053	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	12	0	0
T9	0	30	0	0
T12	0	22	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	24	0	0
T40	0	12	0	0
T41	0	12	0	0
T64	0	13	0	0
T105	0	36	0	0
T254	0	10	0	0
T255	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	81942	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	1242	0	0
T9	0	3342	0	0
T12	0	1805	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	2057	0	0
T40	0	749	0	0
T41	0	1620	0	0
T64	0	226	0	0
T105	0	1739	0	0
T254	0	849	0	0
T255	0	1400	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	934	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	4	0	0
T9	0	21	0	0
T12	0	18	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	24	0	0
T40	0	12	0	0
T41	0	12	0	0
T64	0	13	0	0
T105	0	35	0	0
T254	0	8	0	0
T255	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T22,T16,T17
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T16,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T17,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T22,T17,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T17,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T17,T3
1	0	Covered	T5,T21,T22
1	1	Covered	T22,T17,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T17,T3
0	1	Covered	T118,T119,T121
1	0	Covered	T49,T101

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T17,T3
0	1	Covered	T22,T17,T3
1	0	Covered	T102,T49,T101

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T17,T3
1	-	Covered	T22,T17,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T17,T3
DetectSt	168	Covered	T22,T17,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T22,T17,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T17,T3
DebounceSt->IdleSt	163	Covered	T39,T99,T199
DetectSt->IdleSt	186	Covered	T118,T119,T121
DetectSt->StableSt	191	Covered	T22,T17,T3
IdleSt->DebounceSt	148	Covered	T22,T17,T3
StableSt->IdleSt	206	Covered	T22,T17,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T17,T3
0	1	Covered	T22,T17,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T17,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T17,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T101
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T17,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T99,T199
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T17,T3
DetectSt	-	-	-	-	1	-	-	Covered	T118,T119,T121
DetectSt	-	-	-	-	0	1	-	Covered	T22,T17,T3
DetectSt	-	-	-	-	0	0	-	Covered	T22,T17,T3
StableSt	-	-	-	-	-	-	1	Covered	T22,T17,T3
StableSt	-	-	-	-	-	-	0	Covered	T22,T17,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	838	0	0
CntIncr_A	6698738	39302	0	0
CntNoWrap_A	6698738	6029153	0	0
DetectStDropOut_A	6698738	38	0	0
DetectedOut_A	6698738	12628	0	0
DetectedPulseOut_A	6698738	337	0	0
DisabledIdleSt_A	6698738	5649514	0	0
DisabledNoDetection_A	6698738	5651081	0	0
EnterDebounceSt_A	6698738	459	0	0
EnterDetectSt_A	6698738	381	0	0
EnterStableSt_A	6698738	337	0	0
PulseIsPulse_A	6698738	337	0	0
StayInStableSt	6698738	12263	0	0
gen_high_level_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	302	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	838	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	10	0	0
T7	0	8	0	0
T9	0	10	0	0
T12	0	8	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	14	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	2	0	0
T29	0	8	0	0
T30	0	8	0	0
T31	0	4	0	0
T39	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	39302	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	340	0	0
T7	0	504	0	0
T9	0	350	0	0
T12	0	228	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	1197	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	56	0	0
T29	0	684	0	0
T30	0	392	0	0
T31	0	340	0	0
T39	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029153	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12827	0	0
T21	1360	158	0	0
T22	9912	9509	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	38	0	0
T115	0	2	0	0
T118	12313	1	0	0
T119	0	2	0	0
T121	0	2	0	0
T124	0	7	0	0
T127	0	4	0	0
T128	0	4	0	0
T129	0	1	0	0
T130	0	3	0	0
T131	0	1	0	0
T132	564	0	0	0
T133	845	0	0	0
T134	6811	0	0	0
T135	2615	0	0	0
T136	426	0	0	0
T137	420	0	0	0
T138	531	0	0	0
T139	667	0	0	0
T140	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	12628	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	170	0	0
T7	0	153	0	0
T9	0	271	0	0
T12	0	235	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	31	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	74	0	0
T29	0	98	0	0
T30	0	111	0	0
T31	0	22	0	0
T141	0	292	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	337	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	5	0	0
T7	0	4	0	0
T9	0	5	0	0
T12	0	4	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	7	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	1	0	0
T29	0	4	0	0
T30	0	4	0	0
T31	0	2	0	0
T141	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5649514	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	8057	0	0
T21	1360	158	0	0
T22	9912	7430	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5651081	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	8057	0	0
T21	1360	160	0	0
T22	9912	7431	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	459	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	5	0	0
T7	0	4	0	0
T9	0	5	0	0
T12	0	4	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	7	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	1	0	0
T29	0	4	0	0
T30	0	4	0	0
T31	0	2	0	0
T39	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	381	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	5	0	0
T7	0	4	0	0
T9	0	5	0	0
T12	0	4	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	7	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	1	0	0
T29	0	4	0	0
T30	0	4	0	0
T31	0	2	0	0
T141	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	337	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	5	0	0
T7	0	4	0	0
T9	0	5	0	0
T12	0	4	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	7	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	1	0	0
T29	0	4	0	0
T30	0	4	0	0
T31	0	2	0	0
T141	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	337	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	5	0	0
T7	0	4	0	0
T9	0	5	0	0
T12	0	4	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	7	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	1	0	0
T29	0	4	0	0
T30	0	4	0	0
T31	0	2	0	0
T141	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	12263	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	165	0	0
T7	0	149	0	0
T9	0	261	0	0
T12	0	231	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	24	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	73	0	0
T29	0	94	0	0
T30	0	107	0	0
T31	0	20	0	0
T141	0	280	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	302	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	5	0	0
T7	0	4	0	0
T12	0	4	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	7	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	1	0	0
T29	0	4	0	0
T30	0	4	0	0
T31	0	2	0	0
T99	0	9	0	0
T141	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T22,T16,T3
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T16,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T16,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T16,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T16,T3
1	0	Covered	T22,T3,T9
1	1	Covered	T22,T16,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T16,T3
0	1	Covered	T16,T62,T117
1	0	Covered	T63,T255,T106

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T3,T9
0	1	Covered	T22,T3,T9
1	0	Covered	T106,T256

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T3,T9
1	-	Covered	T22,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T16,T3
DetectSt	168	Covered	T22,T16,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T22,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T16,T3
DebounceSt->IdleSt	163	Covered	T252,T253,T49
DetectSt->IdleSt	186	Covered	T16,T62,T63
DetectSt->StableSt	191	Covered	T22,T3,T9
IdleSt->DebounceSt	148	Covered	T22,T16,T3
StableSt->IdleSt	206	Covered	T22,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T22,T16,T3
0	1	Covered	T22,T16,T3
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T16,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T22,T16,T3
IdleSt	0	-	-	-	-	-	-	Covered	T22,T16,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T101
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T16,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T252,T253,T49
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T16,T3
DetectSt	-	-	-	-	1	-	-	Covered	T16,T62,T63
DetectSt	-	-	-	-	0	1	-	Covered	T22,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T22,T16,T3
StableSt	-	-	-	-	-	-	1	Covered	T22,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T22,T3,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	3059	0	0
CntIncr_A	6698738	113277	0	0
CntNoWrap_A	6698738	6026932	0	0
DetectStDropOut_A	6698738	390	0	0
DetectedOut_A	6698738	74739	0	0
DetectedPulseOut_A	6698738	1000	0	0
DisabledIdleSt_A	6698738	5544952	0	0
DisabledNoDetection_A	6698738	5546985	0	0
EnterDebounceSt_A	6698738	1538	0	0
EnterDetectSt_A	6698738	1521	0	0
EnterStableSt_A	6698738	1000	0	0
PulseIsPulse_A	6698738	1000	0	0
StayInStableSt	6698738	73632	0	0
gen_high_event_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_high_level_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	881	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	3059	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	28	0	0
T9	0	24	0	0
T12	0	44	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	50	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	48	0	0
T40	0	16	0	0
T41	0	46	0	0
T62	0	6	0	0
T63	0	24	0	0
T64	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	113277	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	644	0	0
T9	0	828	0	0
T12	0	1540	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	7649	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	2088	0	0
T40	0	568	0	0
T41	0	1311	0	0
T62	0	178	0	0
T63	0	648	0	0
T64	0	686	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6026932	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17465	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9463	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	390	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T16	17916	25	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T47	511	0	0	0
T48	522	0	0	0
T62	0	3	0	0
T106	0	15	0	0
T117	0	20	0	0
T122	0	27	0	0
T123	0	8	0	0
T125	0	14	0	0
T257	0	23	0	0
T258	0	5	0	0
T259	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	74739	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	1625	0	0
T9	0	694	0	0
T12	0	1633	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	794	0	0
T40	0	483	0	0
T41	0	1033	0	0
T64	0	1601	0	0
T105	0	148	0	0
T254	0	2583	0	0
T260	0	2252	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1000	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	14	0	0
T9	0	12	0	0
T12	0	22	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	24	0	0
T40	0	8	0	0
T41	0	23	0	0
T64	0	14	0	0
T105	0	13	0	0
T254	0	29	0	0
T260	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5544952	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	2014	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	3368	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5546985	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	2014	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	3368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1538	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	14	0	0
T9	0	12	0	0
T12	0	22	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	25	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	24	0	0
T40	0	8	0	0
T41	0	23	0	0
T62	0	3	0	0
T63	0	12	0	0
T64	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1521	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	14	0	0
T9	0	12	0	0
T12	0	22	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	25	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	24	0	0
T40	0	8	0	0
T41	0	23	0	0
T62	0	3	0	0
T63	0	12	0	0
T64	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1000	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	14	0	0
T9	0	12	0	0
T12	0	22	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	24	0	0
T40	0	8	0	0
T41	0	23	0	0
T64	0	14	0	0
T105	0	13	0	0
T254	0	29	0	0
T260	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1000	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	14	0	0
T9	0	12	0	0
T12	0	22	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	24	0	0
T40	0	8	0	0
T41	0	23	0	0
T64	0	14	0	0
T105	0	13	0	0
T254	0	29	0	0
T260	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	73632	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	1601	0	0
T9	0	681	0	0
T12	0	1607	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	770	0	0
T40	0	475	0	0
T41	0	1010	0	0
T64	0	1587	0	0
T105	0	135	0	0
T254	0	2551	0	0
T260	0	2228	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	881	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	4	0	0
T9	0	11	0	0
T12	0	18	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	24	0	0
T40	0	8	0	0
T41	0	23	0	0
T64	0	14	0	0
T105	0	13	0	0
T254	0	26	0	0
T260	0	16	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T22,T16,T17
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T16,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T17,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T17,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T17,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T17,T3
1	0	Covered	T5,T21,T22
1	1	Covered	T17,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T3,T7
0	1	Covered	T99,T261,T262
1	0	Covered	T49,T101

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T3,T7
0	1	Covered	T17,T3,T7
1	0	Covered	T49,T101

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T3,T7
1	-	Covered	T17,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T3,T7
DetectSt	168	Covered	T17,T3,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T17,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T3,T7
DebounceSt->IdleSt	163	Covered	T17,T30,T141
DetectSt->IdleSt	186	Covered	T99,T261,T262
DetectSt->StableSt	191	Covered	T17,T3,T7
IdleSt->DebounceSt	148	Covered	T17,T3,T7
StableSt->IdleSt	206	Covered	T17,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T3,T7
0	1	Covered	T17,T3,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T3,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T101
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T30,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T99,T261,T262
DetectSt	-	-	-	-	0	1	-	Covered	T17,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T17,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T17,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T17,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	813	0	0
CntIncr_A	6698738	41973	0	0
CntNoWrap_A	6698738	6029178	0	0
DetectStDropOut_A	6698738	61	0	0
DetectedOut_A	6698738	13267	0	0
DetectedPulseOut_A	6698738	315	0	0
DisabledIdleSt_A	6698738	5667377	0	0
DisabledNoDetection_A	6698738	5669016	0	0
EnterDebounceSt_A	6698738	434	0	0
EnterDetectSt_A	6698738	380	0	0
EnterStableSt_A	6698738	315	0	0
PulseIsPulse_A	6698738	315	0	0
StayInStableSt	6698738	12928	0	0
gen_high_level_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	289	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	813	0	0
T2	5129	0	0	0
T3	35654	20	0	0
T7	35059	16	0	0
T8	2143	0	0	0
T9	0	2	0	0
T12	0	8	0	0
T17	13266	7	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T29	0	10	0	0
T30	0	5	0	0
T31	0	16	0	0
T47	511	0	0	0
T48	522	0	0	0
T99	0	11	0	0
T141	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	41973	0	0
T2	5129	0	0	0
T3	35654	600	0	0
T7	35059	1280	0	0
T8	2143	0	0	0
T9	0	87	0	0
T12	0	216	0	0
T17	13266	383	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T29	0	520	0	0
T30	0	261	0	0
T31	0	1312	0	0
T47	511	0	0	0
T48	522	0	0	0
T99	0	443	0	0
T141	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029178	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12834	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	61	0	0
T34	4316	0	0	0
T43	706	0	0	0
T44	667	0	0	0
T61	2556	0	0	0
T62	5621	0	0	0
T63	6735	0	0	0
T99	31169	5	0	0
T101	0	1	0	0
T104	0	1	0	0
T127	0	3	0	0
T131	0	4	0	0
T199	436	0	0	0
T200	962	0	0	0
T210	426	0	0	0
T261	0	4	0	0
T262	0	4	0	0
T263	0	7	0	0
T264	0	3	0	0
T265	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	13267	0	0
T2	5129	0	0	0
T3	35654	410	0	0
T7	35059	37	0	0
T8	2143	0	0	0
T9	0	39	0	0
T12	0	247	0	0
T17	13266	226	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T29	0	459	0	0
T30	0	43	0	0
T31	0	141	0	0
T47	511	0	0	0
T48	522	0	0	0
T64	0	53	0	0
T254	0	168	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	315	0	0
T2	5129	0	0	0
T3	35654	10	0	0
T7	35059	8	0	0
T8	2143	0	0	0
T9	0	1	0	0
T12	0	4	0	0
T17	13266	3	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T29	0	5	0	0
T30	0	2	0	0
T31	0	8	0	0
T47	511	0	0	0
T48	522	0	0	0
T64	0	1	0	0
T254	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5667377	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	8057	0	0
T21	1360	158	0	0
T22	9912	8717	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5669016	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	8057	0	0
T21	1360	160	0	0
T22	9912	8718	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	434	0	0
T2	5129	0	0	0
T3	35654	10	0	0
T7	35059	8	0	0
T8	2143	0	0	0
T9	0	1	0	0
T12	0	4	0	0
T17	13266	4	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T29	0	5	0	0
T30	0	3	0	0
T31	0	8	0	0
T47	511	0	0	0
T48	522	0	0	0
T99	0	6	0	0
T141	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	380	0	0
T2	5129	0	0	0
T3	35654	10	0	0
T7	35059	8	0	0
T8	2143	0	0	0
T9	0	1	0	0
T12	0	4	0	0
T17	13266	3	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T29	0	5	0	0
T30	0	2	0	0
T31	0	8	0	0
T47	511	0	0	0
T48	522	0	0	0
T64	0	1	0	0
T99	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	315	0	0
T2	5129	0	0	0
T3	35654	10	0	0
T7	35059	8	0	0
T8	2143	0	0	0
T9	0	1	0	0
T12	0	4	0	0
T17	13266	3	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T29	0	5	0	0
T30	0	2	0	0
T31	0	8	0	0
T47	511	0	0	0
T48	522	0	0	0
T64	0	1	0	0
T254	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	315	0	0
T2	5129	0	0	0
T3	35654	10	0	0
T7	35059	8	0	0
T8	2143	0	0	0
T9	0	1	0	0
T12	0	4	0	0
T17	13266	3	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T29	0	5	0	0
T30	0	2	0	0
T31	0	8	0	0
T47	511	0	0	0
T48	522	0	0	0
T64	0	1	0	0
T254	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	12928	0	0
T2	5129	0	0	0
T3	35654	396	0	0
T7	35059	29	0	0
T8	2143	0	0	0
T9	0	38	0	0
T12	0	243	0	0
T17	13266	223	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T29	0	454	0	0
T30	0	41	0	0
T31	0	133	0	0
T47	511	0	0	0
T48	522	0	0	0
T64	0	52	0	0
T254	0	166	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	289	0	0
T2	5129	0	0	0
T3	35654	6	0	0
T7	35059	8	0	0
T8	2143	0	0	0
T9	0	1	0	0
T12	0	4	0	0
T17	13266	3	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T29	0	5	0	0
T30	0	2	0	0
T31	0	8	0	0
T47	511	0	0	0
T48	522	0	0	0
T64	0	1	0	0
T254	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T22,T16,T3
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T16,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T16,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T16,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T16,T3
1	0	Covered	T22,T3,T9
1	1	Covered	T22,T16,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T16,T3
0	1	Covered	T16,T62,T117
1	0	Covered	T12,T105,T120

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T3,T9
0	1	Covered	T22,T3,T9
1	0	Covered	T215,T101

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T3,T9
1	-	Covered	T22,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T16,T3
DetectSt	168	Covered	T22,T16,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T22,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T16,T3
DebounceSt->IdleSt	163	Covered	T252,T253,T49
DetectSt->IdleSt	186	Covered	T16,T12,T62
DetectSt->StableSt	191	Covered	T22,T3,T9
IdleSt->DebounceSt	148	Covered	T22,T16,T3
StableSt->IdleSt	206	Covered	T22,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T22,T16,T3
0	1	Covered	T22,T16,T3
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T16,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T22,T16,T3
IdleSt	0	-	-	-	-	-	-	Covered	T22,T16,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T101
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T16,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T252,T253,T49
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T16,T3
DetectSt	-	-	-	-	1	-	-	Covered	T16,T12,T62
DetectSt	-	-	-	-	0	1	-	Covered	T22,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T22,T16,T3
StableSt	-	-	-	-	-	-	1	Covered	T22,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T22,T3,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	3060	0	0
CntIncr_A	6698738	115763	0	0
CntNoWrap_A	6698738	6026931	0	0
DetectStDropOut_A	6698738	400	0	0
DetectedOut_A	6698738	68999	0	0
DetectedPulseOut_A	6698738	873	0	0
DisabledIdleSt_A	6698738	5555106	0	0
DisabledNoDetection_A	6698738	5557165	0	0
EnterDebounceSt_A	6698738	1546	0	0
EnterDetectSt_A	6698738	1514	0	0
EnterStableSt_A	6698738	873	0	0
PulseIsPulse_A	6698738	873	0	0
StayInStableSt	6698738	68044	0	0
gen_high_event_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_high_level_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	788	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	3060	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	22	0	0
T9	0	20	0	0
T12	0	54	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	8	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	20	0	0
T40	0	52	0	0
T41	0	46	0	0
T62	0	8	0	0
T63	0	44	0	0
T64	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	115763	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	506	0	0
T9	0	720	0	0
T12	0	1914	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	1220	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	590	0	0
T40	0	2210	0	0
T41	0	1817	0	0
T62	0	238	0	0
T63	0	1166	0	0
T64	0	1768	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6026931	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17507	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	9491	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	400	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T16	17916	4	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T47	511	0	0	0
T48	522	0	0	0
T62	0	4	0	0
T117	0	24	0	0
T120	0	2	0	0
T122	0	15	0	0
T123	0	26	0	0
T125	0	12	0	0
T236	0	2	0	0
T257	0	8	0	0
T258	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	68999	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	654	0	0
T9	0	738	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	870	0	0
T40	0	1220	0	0
T41	0	527	0	0
T63	0	69	0	0
T64	0	308	0	0
T254	0	509	0	0
T255	0	1330	0	0
T260	0	2312	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	873	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	11	0	0
T9	0	10	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	10	0	0
T40	0	26	0	0
T41	0	23	0	0
T63	0	22	0	0
T64	0	26	0	0
T254	0	8	0	0
T255	0	23	0	0
T260	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5555106	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	2014	0	0
T17	13266	12841	0	0
T21	1360	158	0	0
T22	9912	3159	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5557165	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	2014	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	3159	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1546	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	11	0	0
T9	0	10	0	0
T12	0	27	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	4	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	10	0	0
T40	0	26	0	0
T41	0	23	0	0
T62	0	4	0	0
T63	0	22	0	0
T64	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	1514	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	11	0	0
T9	0	10	0	0
T12	0	27	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	4	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	10	0	0
T40	0	26	0	0
T41	0	23	0	0
T62	0	4	0	0
T63	0	22	0	0
T64	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	873	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	11	0	0
T9	0	10	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	10	0	0
T40	0	26	0	0
T41	0	23	0	0
T63	0	22	0	0
T64	0	26	0	0
T254	0	8	0	0
T255	0	23	0	0
T260	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	873	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	11	0	0
T9	0	10	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	10	0	0
T40	0	26	0	0
T41	0	23	0	0
T63	0	22	0	0
T64	0	26	0	0
T254	0	8	0	0
T255	0	23	0	0
T260	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	68044	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	639	0	0
T9	0	725	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	860	0	0
T40	0	1194	0	0
T41	0	504	0	0
T63	0	47	0	0
T64	0	282	0	0
T254	0	500	0	0
T255	0	1305	0	0
T260	0	2288	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	788	0	0
T1	1581	0	0	0
T2	5129	0	0	0
T3	35654	7	0	0
T9	0	7	0	0
T14	503	0	0	0
T15	416	0	0	0
T16	17916	0	0	0
T17	13266	0	0	0
T18	720	0	0	0
T19	738	0	0	0
T22	9912	10	0	0
T40	0	26	0	0
T41	0	23	0	0
T63	0	22	0	0
T64	0	26	0	0
T254	0	7	0	0
T255	0	21	0	0
T260	0	16	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T22,T16,T17
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T16,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T17,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T17,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T17,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T17,T3
1	0	Covered	T5,T21,T22
1	1	Covered	T17,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T3,T7
0	1	Covered	T17,T100,T261
1	0	Covered	T49,T101

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T9
0	1	Covered	T3,T7,T30
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T9
1	-	Covered	T3,T7,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T3,T7
DetectSt	168	Covered	T17,T3,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T3,T7
DebounceSt->IdleSt	163	Covered	T141,T45,T255
DetectSt->IdleSt	186	Covered	T17,T100,T261
DetectSt->StableSt	191	Covered	T3,T7,T9
IdleSt->DebounceSt	148	Covered	T17,T3,T7
StableSt->IdleSt	206	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T3,T7
0	1	Covered	T17,T3,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T3,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T101
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T141,T45,T255
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T17,T100,T261
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T9
DetectSt	-	-	-	-	0	0	-	Covered	T17,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T30
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6698738	780	0	0
CntIncr_A	6698738	42430	0	0
CntNoWrap_A	6698738	6029211	0	0
DetectStDropOut_A	6698738	84	0	0
DetectedOut_A	6698738	11812	0	0
DetectedPulseOut_A	6698738	278	0	0
DisabledIdleSt_A	6698738	5672984	0	0
DisabledNoDetection_A	6698738	5674644	0	0
EnterDebounceSt_A	6698738	414	0	0
EnterDetectSt_A	6698738	367	0	0
EnterStableSt_A	6698738	278	0	0
PulseIsPulse_A	6698738	278	0	0
StayInStableSt	6698738	11515	0	0
gen_high_level_sva.HighLevelEvent_A	6698738	6032222	0	0
gen_not_sticky_sva.StableStDropOut_A	6698738	258	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	780	0	0
T2	5129	0	0	0
T3	35654	8	0	0
T7	35059	6	0	0
T8	2143	0	0	0
T9	0	2	0	0
T17	13266	12	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T29	0	16	0	0
T30	0	8	0	0
T31	0	2	0	0
T35	0	2	0	0
T47	511	0	0	0
T48	522	0	0	0
T99	0	20	0	0
T141	0	11	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	42430	0	0
T2	5129	0	0	0
T3	35654	200	0	0
T7	35059	270	0	0
T8	2143	0	0	0
T9	0	74	0	0
T17	13266	1052	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T29	0	1520	0	0
T30	0	464	0	0
T31	0	166	0	0
T35	0	92	0	0
T47	511	0	0	0
T48	522	0	0	0
T99	0	620	0	0
T141	0	470	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6029211	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	12829	0	0
T21	1360	158	0	0
T22	9912	9511	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	84	0	0
T2	5129	0	0	0
T3	35654	0	0	0
T7	35059	0	0	0
T8	2143	0	0	0
T17	13266	6	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T47	511	0	0	0
T48	522	0	0	0
T100	0	2	0	0
T128	0	8	0	0
T186	0	4	0	0
T233	0	7	0	0
T261	0	6	0	0
T266	0	2	0	0
T267	0	4	0	0
T268	0	2	0	0
T269	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	11812	0	0
T3	35654	205	0	0
T7	35059	223	0	0
T8	2143	0	0	0
T9	27936	51	0	0
T10	254367	0	0	0
T11	696	0	0	0
T20	527	0	0	0
T26	507	0	0	0
T29	0	43	0	0
T30	0	39	0	0
T31	0	15	0	0
T35	0	21	0	0
T47	511	0	0	0
T48	522	0	0	0
T99	0	230	0	0
T141	0	25	0	0
T270	0	136	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	278	0	0
T3	35654	4	0	0
T7	35059	3	0	0
T8	2143	0	0	0
T9	27936	1	0	0
T10	254367	0	0	0
T11	696	0	0	0
T20	527	0	0	0
T26	507	0	0	0
T29	0	8	0	0
T30	0	4	0	0
T31	0	1	0	0
T35	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T99	0	10	0	0
T141	0	5	0	0
T270	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5672984	0	0
T1	1581	1180	0	0
T4	510	109	0	0
T5	3029	624	0	0
T6	405	4	0	0
T14	503	102	0	0
T15	416	15	0	0
T16	17916	17515	0	0
T17	13266	8057	0	0
T21	1360	158	0	0
T22	9912	8641	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	5674644	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	8057	0	0
T21	1360	160	0	0
T22	9912	8642	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	414	0	0
T2	5129	0	0	0
T3	35654	4	0	0
T7	35059	3	0	0
T8	2143	0	0	0
T9	0	1	0	0
T17	13266	6	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T29	0	8	0	0
T30	0	4	0	0
T31	0	1	0	0
T35	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T99	0	10	0	0
T141	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	367	0	0
T2	5129	0	0	0
T3	35654	4	0	0
T7	35059	3	0	0
T8	2143	0	0	0
T9	0	1	0	0
T17	13266	6	0	0
T18	720	0	0	0
T19	738	0	0	0
T20	527	0	0	0
T29	0	8	0	0
T30	0	4	0	0
T31	0	1	0	0
T35	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T99	0	10	0	0
T141	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	278	0	0
T3	35654	4	0	0
T7	35059	3	0	0
T8	2143	0	0	0
T9	27936	1	0	0
T10	254367	0	0	0
T11	696	0	0	0
T20	527	0	0	0
T26	507	0	0	0
T29	0	8	0	0
T30	0	4	0	0
T31	0	1	0	0
T35	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T99	0	10	0	0
T141	0	5	0	0
T270	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	278	0	0
T3	35654	4	0	0
T7	35059	3	0	0
T8	2143	0	0	0
T9	27936	1	0	0
T10	254367	0	0	0
T11	696	0	0	0
T20	527	0	0	0
T26	507	0	0	0
T29	0	8	0	0
T30	0	4	0	0
T31	0	1	0	0
T35	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T99	0	10	0	0
T141	0	5	0	0
T270	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	11515	0	0
T3	35654	201	0	0
T7	35059	220	0	0
T8	2143	0	0	0
T9	27936	49	0	0
T10	254367	0	0	0
T11	696	0	0	0
T20	527	0	0	0
T26	507	0	0	0
T29	0	35	0	0
T30	0	35	0	0
T31	0	14	0	0
T35	0	20	0	0
T47	511	0	0	0
T48	522	0	0	0
T99	0	220	0	0
T141	0	20	0	0
T270	0	133	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	6032222	0	0
T1	1581	1181	0	0
T4	510	110	0	0
T5	3029	629	0	0
T6	405	5	0	0
T14	503	103	0	0
T15	416	16	0	0
T16	17916	17516	0	0
T17	13266	12845	0	0
T21	1360	160	0	0
T22	9912	9512	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6698738	258	0	0
T3	35654	4	0	0
T7	35059	3	0	0
T8	2143	0	0	0
T9	27936	0	0	0
T10	254367	0	0	0
T11	696	0	0	0
T20	527	0	0	0
T26	507	0	0	0
T29	0	8	0	0
T30	0	4	0	0
T31	0	1	0	0
T35	0	1	0	0
T47	511	0	0	0
T48	522	0	0	0
T99	0	10	0	0
T141	0	5	0	0
T255	0	1	0	0
T270	0	3	0	0