Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T3,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T8,T22,T23
1	-	Covered	T1,T3,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	98976420	0	0
DstReqKnown_A	264091056	234357138	0	0
SrcAckBusyChk_A	2147483647	115006	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	98976420	0	0
T1	1639140	2296	0	0
T2	2065482	385	0	0
T3	5882650	72663	0	0
T4	28806976	15101	0	0
T5	4860285	0	0	0
T6	862455	0	0	0
T7	3207633	0	0	0
T8	738708	0	0	0
T9	681486	0	0	0
T10	808247	19072	0	0
T11	145405	2495	0	0
T12	0	1933	0	0
T13	2359170	0	0	0
T14	13521794	6712	0	0
T15	3177117	0	0	0
T16	7341698	3198	0	0
T25	359318	2857	0	0
T40	1409240	1972	0	0
T41	2579444	13943	0	0
T42	93497	2393	0	0
T43	0	5938	0	0
T44	0	9935	0	0
T45	0	2005	0	0
T46	0	12564	0	0
T47	0	1763	0	0
T48	0	3469	0	0
T49	0	4659	0	0
T50	0	11511	0	0
T51	2816240	0	0	0
T52	446160	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264091056	234357138	0	0
T1	675512	660722	0	0
T2	303042	93602	0	0
T3	1436874	1352248	0	0
T4	75718	21318	0	0
T5	23188	9588	0	0
T6	14484	884	0	0
T13	17816	4216	0	0
T14	357204	343298	0	0
T15	16660	3060	0	0
T16	68850	14450	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	115006	0	0
T1	1639140	14	0	0
T2	2065482	1	0	0
T3	5882650	41	0	0
T4	28806976	9	0	0
T5	4860285	0	0	0
T6	862455	0	0	0
T7	3207633	0	0	0
T8	738708	0	0	0
T9	681486	0	0	0
T10	808247	12	0	0
T11	145405	18	0	0
T12	0	1	0	0
T13	2359170	0	0	0
T14	13521794	4	0	0
T15	3177117	0	0	0
T16	7341698	7	0	0
T25	359318	2	0	0
T40	1409240	1	0	0
T41	2579444	8	0	0
T42	93497	6	0	0
T43	0	8	0	0
T44	0	6	0	0
T45	0	7	0	0
T46	0	7	0	0
T47	0	4	0	0
T48	0	2	0	0
T49	0	6	0	0
T50	0	7	0	0
T51	2816240	0	0	0
T52	446160	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3715384	3708550	0	0
T2	3901466	3872430	0	0
T3	6896900	6882246	0	0
T4	33773696	33764278	0	0
T5	11016646	11014198	0	0
T6	1954898	1952246	0	0
T13	4456210	4454340	0	0
T14	17682346	17666876	0	0
T15	4000814	3998842	0	0
T16	8607508	8596764	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T3,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T26,T27,T28
1	-	Covered	T1,T3,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	837817	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1134	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	837817	0	0
T1	109276	1618	0	0
T2	114749	0	0	0
T3	202850	9104	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T8	0	342	0	0
T10	0	3353	0	0
T11	0	1087	0	0
T13	131065	0	0	0
T14	520069	0	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T22	0	659	0	0
T23	0	1401	0	0
T45	0	1215	0	0
T46	0	1429	0	0
T53	0	945	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1134	0	0
T1	109276	9	0	0
T2	114749	0	0	0
T3	202850	5	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T8	0	1	0	0
T10	0	2	0	0
T11	0	8	0	0
T13	131065	0	0	0
T14	520069	0	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T45	0	4	0	0
T46	0	1	0	0
T53	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	1479349	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	2063	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1479349	0	0
T1	109276	1043	0	0
T2	114749	381	0	0
T3	202850	29843	0	0
T4	993344	1408	0	0
T5	324019	1401	0	0
T6	57497	0	0	0
T10	0	9362	0	0
T13	131065	0	0	0
T14	520069	3061	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1291	0	0
T40	0	3430	0	0
T52	0	252	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	2063	0	0
T1	109276	7	0	0
T2	114749	1	0	0
T3	202850	17	0	0
T4	993344	1	0	0
T5	324019	1	0	0
T6	57497	0	0	0
T10	0	6	0	0
T13	131065	0	0	0
T14	520069	2	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1	0	0
T40	0	2	0	0
T52	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T12,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T12,T22
1	1	Covered	T8,T12,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T12,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T12,T22
1	1	Covered	T8,T12,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T12,T22
0	0	1	Covered	T8,T12,T22
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T12,T22
0	0	1	Covered	T8,T12,T22
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	719388	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1064	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	719388	0	0
T8	61559	369	0	0
T9	227162	0	0	0
T10	808247	0	0	0
T11	145405	0	0	0
T12	0	1960	0	0
T22	0	679	0	0
T23	0	1441	0	0
T25	359318	0	0	0
T42	93497	0	0	0
T43	770762	0	0	0
T46	0	1435	0	0
T52	111540	0	0	0
T53	0	954	0	0
T54	0	1496	0	0
T55	0	952	0	0
T56	0	341	0	0
T57	0	951	0	0
T58	88844	0	0	0
T59	19697	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1064	0	0
T8	61559	1	0	0
T9	227162	0	0	0
T10	808247	0	0	0
T11	145405	0	0	0
T12	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	359318	0	0	0
T42	93497	0	0	0
T43	770762	0	0	0
T46	0	1	0	0
T52	111540	0	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	88844	0	0	0
T59	19697	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T12,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T12,T22
1	1	Covered	T8,T12,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T12,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T12,T22
1	1	Covered	T8,T12,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T12,T22
0	0	1	Covered	T8,T12,T22
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T12,T22
0	0	1	Covered	T8,T12,T22
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	696159	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1054	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	696159	0	0
T8	61559	364	0	0
T9	227162	0	0	0
T10	808247	0	0	0
T11	145405	0	0	0
T12	0	1954	0	0
T22	0	667	0	0
T23	0	1433	0	0
T25	359318	0	0	0
T42	93497	0	0	0
T43	770762	0	0	0
T46	0	1426	0	0
T52	111540	0	0	0
T53	0	950	0	0
T54	0	1494	0	0
T55	0	946	0	0
T56	0	330	0	0
T57	0	938	0	0
T58	88844	0	0	0
T59	19697	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1054	0	0
T8	61559	1	0	0
T9	227162	0	0	0
T10	808247	0	0	0
T11	145405	0	0	0
T12	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	359318	0	0	0
T42	93497	0	0	0
T43	770762	0	0	0
T46	0	1	0	0
T52	111540	0	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	88844	0	0	0
T59	19697	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T12,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T12,T22
1	1	Covered	T8,T12,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T12,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T12,T22
1	1	Covered	T8,T12,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T12,T22
0	0	1	Covered	T8,T12,T22
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T12,T22
0	0	1	Covered	T8,T12,T22
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	740062	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1079	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	740062	0	0
T8	61559	355	0	0
T9	227162	0	0	0
T10	808247	0	0	0
T11	145405	0	0	0
T12	0	1947	0	0
T22	0	663	0	0
T23	0	1426	0	0
T25	359318	0	0	0
T42	93497	0	0	0
T43	770762	0	0	0
T46	0	1416	0	0
T52	111540	0	0	0
T53	0	946	0	0
T54	0	1492	0	0
T55	0	933	0	0
T56	0	316	0	0
T57	0	927	0	0
T58	88844	0	0	0
T59	19697	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1079	0	0
T8	61559	1	0	0
T9	227162	0	0	0
T10	808247	0	0	0
T11	145405	0	0	0
T12	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	359318	0	0	0
T42	93497	0	0	0
T43	770762	0	0	0
T46	0	1	0	0
T52	111540	0	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	88844	0	0	0
T59	19697	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T15,T3,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T15,T3,T24
1	1	Covered	T15,T3,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T15,T3,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T3,T24
1	1	Covered	T15,T3,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T15,T3,T24
0	0	1	Covered	T15,T3,T24
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T15,T3,T24
0	0	1	Covered	T15,T3,T24
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	2416131	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	3237	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	2416131	0	0
T3	202850	35527	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T15	117671	15971	0	0
T16	253162	0	0	0
T23	0	32363	0	0
T24	0	18703	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T51	201160	0	0	0
T52	111540	0	0	0
T55	0	16673	0	0
T56	0	23865	0	0
T60	0	34174	0	0
T61	0	34365	0	0
T62	0	1700	0	0
T63	0	34794	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	3237	0	0
T3	202850	20	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T15	117671	20	0	0
T16	253162	0	0	0
T23	0	20	0	0
T24	0	20	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T51	201160	0	0	0
T52	111540	0	0	0
T55	0	20	0	0
T56	0	60	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T13,T15

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T13,T15
1	1	Covered	T2,T13,T15

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T13,T15

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T13,T15
1	1	Covered	T2,T13,T15

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T13,T15
0	0	1	Covered	T2,T13,T15
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T13,T15
0	0	1	Covered	T2,T13,T15
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	5304151	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	6564	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	5304151	0	0
T2	114749	60203	0	0
T3	202850	37369	0	0
T4	993344	0	0	0
T12	0	32470	0	0
T13	131065	17699	0	0
T14	520069	0	0	0
T15	117671	955	0	0
T16	253162	8331	0	0
T23	0	33878	0	0
T24	0	92693	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T51	201160	0	0	0
T60	0	35326	0	0
T64	0	1462	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	6564	0	0
T2	114749	136	0	0
T3	202850	21	0	0
T4	993344	0	0	0
T12	0	20	0	0
T13	131065	20	0	0
T14	520069	0	0	0
T15	117671	1	0	0
T16	253162	20	0	0
T23	0	21	0	0
T24	0	96	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T51	201160	0	0	0
T60	0	21	0	0
T64	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	6367329	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	7765	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	6367329	0	0
T1	109276	1189	0	0
T2	114749	61526	0	0
T3	202850	66654	0	0
T4	993344	1458	0	0
T5	324019	1413	0	0
T6	57497	0	0	0
T13	131065	18147	0	0
T14	520069	3407	0	0
T15	117671	959	0	0
T16	253162	8773	0	0
T40	0	3475	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	7765	0	0
T1	109276	7	0	0
T2	114749	138	0	0
T3	202850	38	0	0
T4	993344	1	0	0
T5	324019	1	0	0
T6	57497	0	0	0
T13	131065	20	0	0
T14	520069	2	0	0
T15	117671	1	0	0
T16	253162	20	0	0
T40	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T13,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T13,T16
1	1	Covered	T2,T13,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T13,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T13,T16
1	1	Covered	T2,T13,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T13,T16
0	0	1	Covered	T2,T13,T16
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T13,T16
0	0	1	Covered	T2,T13,T16
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	5251400	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	6445	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	5251400	0	0
T2	114749	60477	0	0
T3	202850	35491	0	0
T4	993344	0	0	0
T12	0	32602	0	0
T13	131065	17905	0	0
T14	520069	0	0	0
T15	117671	0	0	0
T16	253162	8556	0	0
T23	0	32154	0	0
T24	0	91787	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T51	201160	0	0	0
T60	0	34006	0	0
T64	0	1454	0	0
T65	0	8173	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	6445	0	0
T2	114749	136	0	0
T3	202850	20	0	0
T4	993344	0	0	0
T12	0	20	0	0
T13	131065	20	0	0
T14	520069	0	0	0
T15	117671	0	0	0
T16	253162	20	0	0
T23	0	20	0	0
T24	0	95	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T51	201160	0	0	0
T60	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T4,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T4,T7
1	1	Covered	T2,T4,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T4,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T7
1	1	Covered	T2,T4,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T4,T7
0	0	1	Covered	T2,T4,T7
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T4,T7
0	0	1	Covered	T2,T4,T7
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	684711	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1065	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	684711	0	0
T2	114749	386	0	0
T3	202850	0	0	0
T4	993344	1467	0	0
T7	0	1660	0	0
T9	0	1429	0	0
T12	0	3419	0	0
T13	131065	0	0	0
T14	520069	0	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T24	0	1097	0	0
T34	0	1449	0	0
T37	0	977	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T51	201160	0	0	0
T66	0	1883	0	0
T67	0	802	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1065	0	0
T2	114749	1	0	0
T3	202850	0	0	0
T4	993344	1	0	0
T7	0	1	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	131065	0	0	0
T14	520069	0	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T24	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T51	201160	0	0	0
T66	0	1	0	0
T67	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T14
0	0	1	Covered	T1,T2,T14
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T14
0	0	1	Covered	T1,T2,T14
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	1500218	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	2062	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1500218	0	0
T1	109276	1029	0	0
T2	114749	894	0	0
T3	202850	29809	0	0
T4	993344	3346	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T7	0	1658	0	0
T9	0	1426	0	0
T10	0	9350	0	0
T13	131065	0	0	0
T14	520069	3032	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1284	0	0
T40	0	1942	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	2062	0	0
T1	109276	7	0	0
T2	114749	2	0	0
T3	202850	17	0	0
T4	993344	2	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T10	0	6	0	0
T13	131065	0	0	0
T14	520069	2	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T16,T3,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T16,T3,T4
1	1	Covered	T16,T3,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T16,T3,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T3,T4
1	1	Covered	T16,T3,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T16,T3,T4
0	0	1	Covered	T16,T3,T4
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T16,T3,T4
0	0	1	Covered	T16,T3,T4
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	1004787	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1377	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1004787	0	0
T3	202850	9115	0	0
T4	993344	8304	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T9	227162	0	0	0
T16	253162	1868	0	0
T40	100660	0	0	0
T41	184246	8979	0	0
T42	0	1558	0	0
T43	0	3770	0	0
T44	0	6635	0	0
T46	0	7259	0	0
T49	0	2343	0	0
T50	0	6719	0	0
T51	201160	0	0	0
T52	111540	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1377	0	0
T3	202850	5	0	0
T4	993344	5	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T9	227162	0	0	0
T16	253162	4	0	0
T40	100660	0	0	0
T41	184246	5	0	0
T42	0	4	0	0
T43	0	5	0	0
T44	0	4	0	0
T46	0	4	0	0
T49	0	3	0	0
T50	0	4	0	0
T51	201160	0	0	0
T52	111540	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T16,T3,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T16,T3,T4
1	1	Covered	T16,T3,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T16,T3,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T3,T4
1	1	Covered	T16,T3,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T16,T3,T4
0	0	1	Covered	T16,T3,T4
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T16,T3,T4
0	0	1	Covered	T16,T3,T4
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	858511	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1213	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	858511	0	0
T3	202850	3352	0	0
T4	993344	5357	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T9	227162	0	0	0
T16	253162	1330	0	0
T40	100660	0	0	0
T41	184246	4964	0	0
T42	0	835	0	0
T43	0	2168	0	0
T44	0	3300	0	0
T46	0	5305	0	0
T49	0	2316	0	0
T50	0	4792	0	0
T51	201160	0	0	0
T52	111540	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1213	0	0
T3	202850	2	0	0
T4	993344	3	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T9	227162	0	0	0
T16	253162	3	0	0
T40	100660	0	0	0
T41	184246	3	0	0
T42	0	2	0	0
T43	0	3	0	0
T44	0	2	0	0
T46	0	3	0	0
T49	0	3	0	0
T50	0	3	0	0
T51	201160	0	0	0
T52	111540	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	6764249	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	6936	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	6764249	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	104429	0	0
T11	0	12269	0	0
T14	520069	106894	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	102090	0	0
T39	0	71019	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	109325	0	0
T51	201160	0	0	0
T68	0	68619	0	0
T69	0	18286	0	0
T70	0	124759	0	0
T71	0	88512	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	6936	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	64	0	0
T11	0	84	0	0
T14	520069	62	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	59	0	0
T39	0	84	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	64	0	0
T51	201160	0	0	0
T68	0	84	0	0
T69	0	51	0	0
T70	0	72	0	0
T71	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	6735369	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	6783	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	6735369	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	136757	0	0
T11	0	11734	0	0
T14	520069	124806	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	111916	0	0
T39	0	57493	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	143539	0	0
T51	201160	0	0	0
T68	0	44337	0	0
T69	0	17539	0	0
T70	0	108792	0	0
T71	0	87797	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	6783	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	84	0	0
T11	0	85	0	0
T14	520069	73	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	65	0	0
T39	0	69	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	84	0	0
T51	201160	0	0	0
T68	0	56	0	0
T69	0	51	0	0
T70	0	63	0	0
T71	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	6680275	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	6815	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	6680275	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	141699	0	0
T11	0	11678	0	0
T14	520069	117417	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	125062	0	0
T39	0	58295	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	155727	0	0
T51	201160	0	0	0
T68	0	66385	0	0
T69	0	16789	0	0
T70	0	131460	0	0
T71	0	87077	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	6815	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	87	0	0
T11	0	82	0	0
T14	520069	69	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	73	0	0
T39	0	71	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	91	0	0
T51	201160	0	0	0
T68	0	84	0	0
T69	0	51	0	0
T70	0	76	0	0
T71	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	6780166	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	7032	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	6780166	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	118456	0	0
T11	0	9362	0	0
T14	520069	134866	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	99290	0	0
T39	0	60272	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	102179	0	0
T51	201160	0	0	0
T68	0	65035	0	0
T69	0	16159	0	0
T70	0	131096	0	0
T71	0	86352	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	7032	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	73	0	0
T11	0	68	0	0
T14	520069	80	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	59	0	0
T39	0	74	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	60	0	0
T51	201160	0	0	0
T68	0	84	0	0
T69	0	51	0	0
T70	0	76	0	0
T71	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	891898	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1234	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	891898	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	9590	0	0
T11	0	1345	0	0
T14	520069	3453	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1469	0	0
T39	0	721	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	3497	0	0
T51	201160	0	0	0
T68	0	4735	0	0
T69	0	408	0	0
T70	0	16644	0	0
T71	0	1478	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1234	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	6	0	0
T11	0	9	0	0
T14	520069	2	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1	0	0
T39	0	1	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	2	0	0
T51	201160	0	0	0
T68	0	6	0	0
T69	0	1	0	0
T70	0	10	0	0
T71	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	869987	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1224	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	869987	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	9530	0	0
T11	0	1320	0	0
T14	520069	3348	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1428	0	0
T39	0	677	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	3477	0	0
T51	201160	0	0	0
T68	0	4482	0	0
T69	0	360	0	0
T70	0	16544	0	0
T71	0	1455	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1224	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	6	0	0
T11	0	9	0	0
T14	520069	2	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1	0	0
T39	0	1	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	2	0	0
T51	201160	0	0	0
T68	0	6	0	0
T69	0	1	0	0
T70	0	10	0	0
T71	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	857988	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1237	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	857988	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	9470	0	0
T11	0	1302	0	0
T14	520069	3254	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1378	0	0
T39	0	638	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	3457	0	0
T51	201160	0	0	0
T68	0	4271	0	0
T69	0	322	0	0
T70	0	16444	0	0
T71	0	1424	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1237	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	6	0	0
T11	0	9	0	0
T14	520069	2	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1	0	0
T39	0	1	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	2	0	0
T51	201160	0	0	0
T68	0	6	0	0
T69	0	1	0	0
T70	0	10	0	0
T71	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T14,T25,T10
0	0	1	Covered	T14,T25,T10
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	850682	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1225	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	850682	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	9410	0	0
T11	0	1287	0	0
T14	520069	3152	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1331	0	0
T39	0	601	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	3437	0	0
T51	201160	0	0	0
T68	0	4080	0	0
T69	0	399	0	0
T70	0	16344	0	0
T71	0	1389	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1225	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T10	0	6	0	0
T11	0	9	0	0
T14	520069	2	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1	0	0
T39	0	1	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T48	0	2	0	0
T51	201160	0	0	0
T68	0	6	0	0
T69	0	1	0	0
T70	0	10	0	0
T71	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T14
0	0	1	Covered	T1,T2,T14
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T14
0	0	1	Covered	T1,T2,T14
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	7321204	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	7638	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	7321204	0	0
T1	109276	1211	0	0
T2	114749	387	0	0
T3	202850	30251	0	0
T4	993344	1449	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	104521	0	0
T11	0	12748	0	0
T12	0	1939	0	0
T13	131065	0	0	0
T14	520069	107523	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	102634	0	0
T40	0	1980	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	7638	0	0
T1	109276	7	0	0
T2	114749	1	0	0
T3	202850	17	0	0
T4	993344	1	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	64	0	0
T11	0	84	0	0
T12	0	1	0	0
T13	131065	0	0	0
T14	520069	62	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	59	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	7259817	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	7439	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	7259817	0	0
T1	109276	1197	0	0
T2	114749	0	0	0
T3	202850	30217	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	136889	0	0
T11	0	11754	0	0
T13	131065	0	0	0
T14	520069	125480	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	112518	0	0
T45	0	2296	0	0
T47	0	1795	0	0
T48	0	143695	0	0
T72	0	10492	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	7439	0	0
T1	109276	7	0	0
T2	114749	0	0	0
T3	202850	17	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	84	0	0
T11	0	85	0	0
T13	131065	0	0	0
T14	520069	73	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	65	0	0
T45	0	7	0	0
T47	0	4	0	0
T48	0	84	0	0
T72	0	11	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	7206344	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	7467	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	7206344	0	0
T1	109276	1183	0	0
T2	114749	0	0	0
T3	202850	30183	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	141837	0	0
T11	0	11658	0	0
T13	131065	0	0	0
T14	520069	118045	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	125736	0	0
T45	0	2236	0	0
T47	0	1787	0	0
T48	0	155897	0	0
T72	0	10414	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	7467	0	0
T1	109276	7	0	0
T2	114749	0	0	0
T3	202850	17	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	87	0	0
T11	0	82	0	0
T13	131065	0	0	0
T14	520069	69	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	73	0	0
T45	0	7	0	0
T47	0	4	0	0
T48	0	91	0	0
T72	0	11	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	7304547	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	7649	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	7304547	0	0
T1	109276	1169	0	0
T2	114749	0	0	0
T3	202850	30149	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	118566	0	0
T11	0	9598	0	0
T13	131065	0	0	0
T14	520069	135628	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	99786	0	0
T45	0	2165	0	0
T47	0	1779	0	0
T48	0	102287	0	0
T72	0	10338	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	7649	0	0
T1	109276	7	0	0
T2	114749	0	0	0
T3	202850	17	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	73	0	0
T11	0	68	0	0
T13	131065	0	0	0
T14	520069	80	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	59	0	0
T45	0	7	0	0
T47	0	4	0	0
T48	0	60	0	0
T72	0	11	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T14
0	0	1	Covered	T1,T2,T14
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T14
0	0	1	Covered	T1,T2,T14
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	1425821	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1957	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1425821	0	0
T1	109276	1155	0	0
T2	114749	385	0	0
T3	202850	30115	0	0
T4	993344	1440	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	9566	0	0
T11	0	1249	0	0
T12	0	1933	0	0
T13	131065	0	0	0
T14	520069	3410	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1448	0	0
T40	0	1972	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1957	0	0
T1	109276	7	0	0
T2	114749	1	0	0
T3	202850	17	0	0
T4	993344	1	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	6	0	0
T11	0	9	0	0
T12	0	1	0	0
T13	131065	0	0	0
T14	520069	2	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	1355132	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1864	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1355132	0	0
T1	109276	1141	0	0
T2	114749	0	0	0
T3	202850	30081	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	9506	0	0
T11	0	1246	0	0
T13	131065	0	0	0
T14	520069	3302	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1409	0	0
T45	0	2005	0	0
T47	0	1763	0	0
T48	0	3469	0	0
T72	0	10185	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1864	0	0
T1	109276	7	0	0
T2	114749	0	0	0
T3	202850	17	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	6	0	0
T11	0	9	0	0
T13	131065	0	0	0
T14	520069	2	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1	0	0
T45	0	7	0	0
T47	0	4	0	0
T48	0	2	0	0
T72	0	11	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	1344550	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1879	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1344550	0	0
T1	109276	1127	0	0
T2	114749	0	0	0
T3	202850	30047	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	9446	0	0
T11	0	1347	0	0
T13	131065	0	0	0
T14	520069	3220	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1359	0	0
T45	0	1922	0	0
T47	0	1755	0	0
T48	0	3449	0	0
T72	0	10116	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1879	0	0
T1	109276	7	0	0
T2	114749	0	0	0
T3	202850	17	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	6	0	0
T11	0	9	0	0
T13	131065	0	0	0
T14	520069	2	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1	0	0
T45	0	7	0	0
T47	0	4	0	0
T48	0	2	0	0
T72	0	11	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	1331203	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1889	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1331203	0	0
T1	109276	1113	0	0
T2	114749	0	0	0
T3	202850	30013	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	9386	0	0
T11	0	1317	0	0
T13	131065	0	0	0
T14	520069	3116	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1311	0	0
T45	0	1852	0	0
T47	0	1747	0	0
T48	0	3429	0	0
T72	0	10039	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1889	0	0
T1	109276	7	0	0
T2	114749	0	0	0
T3	202850	17	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	6	0	0
T11	0	9	0	0
T13	131065	0	0	0
T14	520069	2	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1	0	0
T45	0	7	0	0
T47	0	4	0	0
T48	0	2	0	0
T72	0	11	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T14
0	0	1	Covered	T1,T2,T14
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T14
0	0	1	Covered	T1,T2,T14
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	1427341	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1952	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1427341	0	0
T1	109276	1099	0	0
T2	114749	383	0	0
T3	202850	29979	0	0
T4	993344	1419	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	9554	0	0
T11	0	1388	0	0
T12	0	1922	0	0
T13	131065	0	0	0
T14	520069	3395	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1439	0	0
T40	0	1964	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1952	0	0
T1	109276	7	0	0
T2	114749	1	0	0
T3	202850	17	0	0
T4	993344	1	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	6	0	0
T11	0	9	0	0
T12	0	1	0	0
T13	131065	0	0	0
T14	520069	2	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	1325606	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1844	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1325606	0	0
T1	109276	1085	0	0
T2	114749	0	0	0
T3	202850	29945	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	9494	0	0
T11	0	1359	0	0
T13	131065	0	0	0
T14	520069	3290	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1395	0	0
T45	0	2096	0	0
T47	0	1731	0	0
T48	0	3465	0	0
T72	0	9872	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1844	0	0
T1	109276	7	0	0
T2	114749	0	0	0
T3	202850	17	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	6	0	0
T11	0	9	0	0
T13	131065	0	0	0
T14	520069	2	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1	0	0
T45	0	7	0	0
T47	0	4	0	0
T48	0	2	0	0
T72	0	11	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	1309898	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1857	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1309898	0	0
T1	109276	1071	0	0
T2	114749	0	0	0
T3	202850	29911	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	9434	0	0
T11	0	1300	0	0
T13	131065	0	0	0
T14	520069	3197	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1347	0	0
T45	0	2225	0	0
T47	0	1723	0	0
T48	0	3445	0	0
T72	0	9800	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1857	0	0
T1	109276	7	0	0
T2	114749	0	0	0
T3	202850	17	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	6	0	0
T11	0	9	0	0
T13	131065	0	0	0
T14	520069	2	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1	0	0
T45	0	7	0	0
T47	0	4	0	0
T48	0	2	0	0
T72	0	11	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T14,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T14,T3
0	0	1	Covered	T1,T14,T3
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	1344838	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1882	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1344838	0	0
T1	109276	1057	0	0
T2	114749	0	0	0
T3	202850	29877	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	9374	0	0
T11	0	1303	0	0
T13	131065	0	0	0
T14	520069	3090	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1303	0	0
T45	0	2271	0	0
T47	0	1715	0	0
T48	0	3425	0	0
T72	0	9709	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1882	0	0
T1	109276	7	0	0
T2	114749	0	0	0
T3	202850	17	0	0
T4	993344	0	0	0
T5	324019	0	0	0
T6	57497	0	0	0
T10	0	6	0	0
T11	0	9	0	0
T13	131065	0	0	0
T14	520069	2	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	1	0	0
T45	0	7	0	0
T47	0	4	0	0
T48	0	2	0	0
T72	0	11	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T22,T23

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T22,T23
1	1	Covered	T8,T22,T23

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T8,T22,T23
1	-	Covered	T8,T22,T23

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T22,T23

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T22,T23
1	1	Covered	T8,T22,T23

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T22,T23
0	0	1	Covered	T8,T22,T23
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T22,T23
0	0	1	Covered	T8,T22,T23
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1492797775	729492	0	0
DstReqKnown_A	7767384	6892857	0	0
SrcAckBusyChk_A	1492797775	1081	0	0
SrcBusyKnown_A	1492797775	1491121295	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	729492	0	0
T8	61559	885	0	0
T9	227162	0	0	0
T10	808247	0	0	0
T11	145405	0	0	0
T22	0	1352	0	0
T23	0	3352	0	0
T25	359318	0	0	0
T33	0	1381	0	0
T35	0	589	0	0
T42	93497	0	0	0
T43	770762	0	0	0
T46	0	3363	0	0
T52	111540	0	0	0
T53	0	1666	0	0
T58	88844	0	0	0
T59	19697	0	0	0
T73	0	1099	0	0
T74	0	226	0	0
T75	0	2672	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7767384	6892857	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1081	0	0
T8	61559	2	0	0
T9	227162	0	0	0
T10	808247	0	0	0
T11	145405	0	0	0
T22	0	2	0	0
T23	0	2	0	0
T25	359318	0	0	0
T33	0	2	0	0
T35	0	2	0	0
T42	93497	0	0	0
T43	770762	0	0	0
T46	0	2	0	0
T52	111540	0	0	0
T53	0	4	0	0
T58	88844	0	0	0
T59	19697	0	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1491121295	0	0
T1	109276	109075	0	0
T2	114749	113895	0	0
T3	202850	202419	0	0
T4	993344	993067	0	0
T5	324019	323947	0	0
T6	57497	57419	0	0
T13	131065	131010	0	0
T14	520069	519614	0	0
T15	117671	117613	0	0
T16	253162	252846	0	0