Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T21
1	-	Covered	T1,T2,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	102457252	0	0
DstReqKnown_A	254065272	224417034	0	0
SrcAckBusyChk_A	2147483647	115195	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	102457252	0	0
T1	1431584	26774	0	0
T2	5470828	6826	0	0
T3	6002150	0	0	0
T4	6195266	2746	0	0
T5	2533872	28866	0	0
T6	0	1462	0	0
T7	0	4012	0	0
T9	0	39696	0	0
T13	2817408	879	0	0
T14	5511594	0	0	0
T15	8215920	12691	0	0
T16	1119525	0	0	0
T17	636750	0	0	0
T22	791340	0	0	0
T23	247353	0	0	0
T25	903567	4403	0	0
T26	0	3423	0	0
T27	2672064	14686	0	0
T48	1567084	16894	0	0
T49	0	319	0	0
T50	0	2696	0	0
T51	0	2300	0	0
T52	0	13924	0	0
T53	0	6437	0	0
T54	0	2243	0	0
T55	0	420	0	0
T56	0	2131	0	0
T57	2273095	0	0	0
T58	153594	0	0	0
T59	358192	0	0	0
T60	3055544	0	0	0
T61	108953	0	0	0
T62	49059	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	254065272	224417034	0	0
T1	731918	716788	0	0
T2	704548	689486	0	0
T3	16320	2720	0	0
T4	199444	185844	0	0
T5	783190	768366	0	0
T13	362848	349248	0	0
T14	17714	4114	0	0
T15	23732	10132	0	0
T16	13838	238	0	0
T17	17306	3706	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	115195	0	0
T1	1431584	16	0	0
T2	5470828	16	0	0
T3	6002150	0	0	0
T4	6195266	2	0	0
T5	2533872	16	0	0
T6	0	1	0	0
T7	0	26	0	0
T9	0	24	0	0
T13	2817408	2	0	0
T14	5511594	0	0	0
T15	8215920	7	0	0
T16	1119525	0	0	0
T17	636750	0	0	0
T22	791340	0	0	0
T23	247353	0	0	0
T25	903567	3	0	0
T26	0	8	0	0
T27	2672064	8	0	0
T48	1567084	10	0	0
T49	0	1	0	0
T50	0	7	0	0
T51	0	6	0	0
T52	0	8	0	0
T53	0	8	0	0
T54	0	8	0	0
T55	0	6	0	0
T56	0	9	0	0
T57	2273095	0	0	0
T58	153594	0	0	0
T59	358192	0	0	0
T60	3055544	0	0	0
T61	108953	0	0	0
T62	49059	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3476704	3469428	0	0
T2	8454916	8437168	0	0
T3	8162924	8159762	0	0
T4	9574502	9574230	0	0
T5	3915984	3909830	0	0
T13	4354176	4353904	0	0
T14	8517918	8515708	0	0
T15	11639220	11637350	0	0
T16	1522554	1519698	0	0
T17	865980	863192	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T63,T28,T18
1	-	Covered	T1,T2,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	961351	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1153	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	961351	0	0
T1	102256	12191	0	0
T2	248674	3099	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T7	0	660	0	0
T9	0	1872	0	0
T11	0	940	0	0
T12	0	5269	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T21	0	816	0	0
T31	0	2395	0	0
T35	0	9821	0	0
T64	0	1492	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1153	0	0
T1	102256	7	0	0
T2	248674	7	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T7	0	4	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	0	3	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T21	0	1	0	0
T31	0	3	0	0
T35	0	12	0	0
T64	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1817333	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	2117	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1817333	0	0
T1	102256	12756	0	0
T2	248674	3293	0	0
T3	240086	0	0	0
T4	281603	1199	0	0
T5	115176	14313	0	0
T13	128064	456	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	6959	0	0
T48	0	8302	0	0
T59	0	474	0	0
T60	0	1908	0	0
T65	0	739	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	2117	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	8	0	0
T13	128064	1	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	4	0	0
T48	0	5	0	0
T59	0	1	0	0
T60	0	1	0	0
T65	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T25,T7,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T25,T7,T9
1	1	Covered	T25,T7,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T25,T7,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T25,T7,T9
1	1	Covered	T25,T7,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T25,T7,T9
0	0	1	Covered	T25,T7,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T25,T7,T9
0	0	1	Covered	T25,T7,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	967524	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1043	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	967524	0	0
T6	153340	0	0	0
T7	149569	131	0	0
T8	303069	0	0	0
T9	339047	3280	0	0
T11	0	955	0	0
T21	0	2557	0	0
T25	903567	1469	0	0
T26	90540	0	0	0
T37	0	274	0	0
T62	49059	0	0	0
T64	0	1494	0	0
T65	136997	0	0	0
T66	0	1907	0	0
T67	0	1419	0	0
T68	0	346	0	0
T69	191277	0	0	0
T70	64818	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1043	0	0
T6	153340	0	0	0
T7	149569	1	0	0
T8	303069	0	0	0
T9	339047	2	0	0
T11	0	1	0	0
T21	0	3	0	0
T25	903567	1	0	0
T26	90540	0	0	0
T37	0	2	0	0
T62	49059	0	0	0
T64	0	1	0	0
T65	136997	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	191277	0	0	0
T70	64818	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T25,T7,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T25,T7,T9
1	1	Covered	T25,T7,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T25,T7,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T25,T7,T9
1	1	Covered	T25,T7,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T25,T7,T9
0	0	1	Covered	T25,T7,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T25,T7,T9
0	0	1	Covered	T25,T7,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	998837	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1077	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	998837	0	0
T6	153340	0	0	0
T7	149569	129	0	0
T8	303069	0	0	0
T9	339047	3269	0	0
T11	0	948	0	0
T21	0	2538	0	0
T25	903567	1467	0	0
T26	90540	0	0	0
T37	0	256	0	0
T62	49059	0	0	0
T64	0	1492	0	0
T65	136997	0	0	0
T66	0	1902	0	0
T67	0	1408	0	0
T68	0	336	0	0
T69	191277	0	0	0
T70	64818	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1077	0	0
T6	153340	0	0	0
T7	149569	1	0	0
T8	303069	0	0	0
T9	339047	2	0	0
T11	0	1	0	0
T21	0	3	0	0
T25	903567	1	0	0
T26	90540	0	0	0
T37	0	2	0	0
T62	49059	0	0	0
T64	0	1	0	0
T65	136997	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	191277	0	0	0
T70	64818	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T25,T7,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T25,T7,T9
1	1	Covered	T25,T7,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T25,T7,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T25,T7,T9
1	1	Covered	T25,T7,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T25,T7,T9
0	0	1	Covered	T25,T7,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T25,T7,T9
0	0	1	Covered	T25,T7,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	989977	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1071	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	989977	0	0
T6	153340	0	0	0
T7	149569	127	0	0
T8	303069	0	0	0
T9	339047	3254	0	0
T11	0	936	0	0
T21	0	2525	0	0
T25	903567	1465	0	0
T26	90540	0	0	0
T37	0	234	0	0
T62	49059	0	0	0
T64	0	1490	0	0
T65	136997	0	0	0
T66	0	1897	0	0
T67	0	1397	0	0
T68	0	327	0	0
T69	191277	0	0	0
T70	64818	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1071	0	0
T6	153340	0	0	0
T7	149569	1	0	0
T8	303069	0	0	0
T9	339047	2	0	0
T11	0	1	0	0
T21	0	3	0	0
T25	903567	1	0	0
T26	90540	0	0	0
T37	0	2	0	0
T62	49059	0	0	0
T64	0	1	0	0
T65	136997	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	191277	0	0	0
T70	64818	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T22,T23,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T22,T23,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T22,T23,T24
0	0	1	Covered	T22,T23,T24
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T22,T23,T24
0	0	1	Covered	T22,T23,T24
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	2598025	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	3115	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	2598025	0	0
T11	0	18016	0	0
T22	197835	26731	0	0
T23	247353	36004	0	0
T24	0	8644	0	0
T25	903567	0	0	0
T26	90540	0	0	0
T27	668016	0	0	0
T34	0	2594	0	0
T38	0	25996	0	0
T48	783542	0	0	0
T59	89548	0	0	0
T60	763886	0	0	0
T61	108953	0	0	0
T62	49059	0	0	0
T71	0	16634	0	0
T72	0	33150	0	0
T73	0	6901	0	0
T74	0	25779	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	3115	0	0
T11	0	20	0	0
T22	197835	20	0	0
T23	247353	20	0	0
T24	0	20	0	0
T25	903567	0	0	0
T26	90540	0	0	0
T27	668016	0	0	0
T34	0	20	0	0
T38	0	60	0	0
T48	783542	0	0	0
T59	89548	0	0	0
T60	763886	0	0	0
T61	108953	0	0	0
T62	49059	0	0	0
T71	0	20	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T14,T17,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T14,T17,T22
1	1	Covered	T14,T17,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T14,T17,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T17,T22
1	1	Covered	T14,T17,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T14,T17,T22
0	0	1	Covered	T14,T17,T22
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T14,T17,T22
0	0	1	Covered	T14,T17,T22
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	5264401	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	6483	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	5264401	0	0
T3	240086	0	0	0
T7	0	6155	0	0
T9	0	79813	0	0
T14	250527	34968	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	3014	0	0
T22	197835	1618	0	0
T23	0	1995	0	0
T25	0	13688	0	0
T27	668016	0	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T75	0	32908	0	0
T76	0	6138	0	0
T77	0	36193	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6483	0	0
T3	240086	0	0	0
T7	0	40	0	0
T9	0	49	0	0
T14	250527	20	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	20	0	0
T22	197835	1	0	0
T23	0	1	0	0
T25	0	8	0	0
T27	668016	0	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T75	0	20	0	0
T76	0	20	0	0
T77	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	6421387	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	7758	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6421387	0	0
T1	102256	13659	0	0
T2	248674	3469	0	0
T3	240086	0	0	0
T4	281603	1418	0	0
T5	115176	14452	0	0
T13	128064	476	0	0
T14	250527	35048	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	3419	0	0
T22	0	1620	0	0
T27	0	7396	0	0
T59	0	486	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	7758	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	8	0	0
T13	128064	1	0	0
T14	250527	20	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	20	0	0
T22	0	1	0	0
T27	0	4	0	0
T59	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T14,T17,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T14,T17,T25
1	1	Covered	T14,T17,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T14,T17,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T17,T25
1	1	Covered	T14,T17,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T14,T17,T25
0	0	1	Covered	T14,T17,T25
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T14,T17,T25
0	0	1	Covered	T14,T17,T25
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	5261456	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	6408	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	5261456	0	0
T3	240086	0	0	0
T7	0	6235	0	0
T9	0	80170	0	0
T14	250527	35008	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	3192	0	0
T22	197835	0	0	0
T25	0	13704	0	0
T27	668016	0	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T75	0	32948	0	0
T76	0	6178	0	0
T77	0	36233	0	0
T78	0	8421	0	0
T79	0	33566	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6408	0	0
T3	240086	0	0	0
T7	0	40	0	0
T9	0	49	0	0
T14	250527	20	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	20	0	0
T22	197835	0	0	0
T25	0	8	0	0
T27	668016	0	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T75	0	20	0	0
T76	0	20	0	0
T77	0	20	0	0
T78	0	20	0	0
T79	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T3,T6,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T3,T6,T8
1	1	Covered	T3,T6,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T3,T6,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T8
1	1	Covered	T3,T6,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T3,T6,T8
0	0	1	Covered	T3,T6,T8
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T3,T6,T8
0	0	1	Covered	T3,T6,T8
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	993645	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1108	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	993645	0	0
T3	240086	1472	0	0
T6	0	3482	0	0
T8	0	1995	0	0
T9	0	1896	0	0
T10	0	1329	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T22	197835	0	0	0
T27	668016	0	0	0
T36	0	748	0	0
T37	0	271	0	0
T41	0	376	0	0
T43	0	950	0	0
T44	0	673	0	0
T48	783542	0	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T60	763886	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1108	0	0
T3	240086	1	0	0
T6	0	2	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	2	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T22	197835	0	0	0
T27	668016	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	783542	0	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T60	763886	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1856554	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	2157	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1856554	0	0
T1	102256	12644	0	0
T2	248674	3277	0	0
T3	240086	1464	0	0
T4	281603	1180	0	0
T5	115176	14297	0	0
T6	0	5384	0	0
T7	0	1785	0	0
T13	128064	454	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	6926	0	0
T48	0	8292	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	2157	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	1	0	0
T4	281603	1	0	0
T5	115176	8	0	0
T6	0	3	0	0
T7	0	13	0	0
T13	128064	1	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	4	0	0
T48	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T15,T25,T26

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T15,T25,T26
1	1	Covered	T15,T25,T26

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T15,T25,T26

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T25,T26
1	1	Covered	T15,T25,T26

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T15,T25,T26
0	0	1	Covered	T15,T25,T26
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T15,T25,T26
0	0	1	Covered	T15,T25,T26
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1293626	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1378	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1293626	0	0
T3	240086	0	0	0
T9	0	22733	0	0
T15	342330	7330	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T22	197835	0	0	0
T25	0	2937	0	0
T26	0	2217	0	0
T27	668016	0	0	0
T50	0	1610	0	0
T51	0	1153	0	0
T53	0	4075	0	0
T54	0	1403	0	0
T55	0	218	0	0
T56	0	1398	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T60	763886	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1378	0	0
T3	240086	0	0	0
T9	0	14	0	0
T15	342330	4	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T22	197835	0	0	0
T25	0	2	0	0
T26	0	5	0	0
T27	668016	0	0	0
T50	0	4	0	0
T51	0	3	0	0
T53	0	5	0	0
T54	0	5	0	0
T55	0	3	0	0
T56	0	6	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T60	763886	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T15,T25,T26

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T15,T25,T26
1	1	Covered	T15,T25,T26

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T15,T25,T26

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T25,T26
1	1	Covered	T15,T25,T26

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T15,T25,T26
0	0	1	Covered	T15,T25,T26
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T15,T25,T26
0	0	1	Covered	T15,T25,T26
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1125504	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1200	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1125504	0	0
T3	240086	0	0	0
T9	0	15089	0	0
T15	342330	5361	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T22	197835	0	0	0
T25	0	1466	0	0
T26	0	1206	0	0
T27	668016	0	0	0
T50	0	1086	0	0
T51	0	1147	0	0
T53	0	2362	0	0
T54	0	840	0	0
T55	0	202	0	0
T56	0	733	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T60	763886	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1200	0	0
T3	240086	0	0	0
T9	0	9	0	0
T15	342330	3	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T22	197835	0	0	0
T25	0	1	0	0
T26	0	3	0	0
T27	668016	0	0	0
T50	0	3	0	0
T51	0	3	0	0
T53	0	3	0	0
T54	0	3	0	0
T55	0	3	0	0
T56	0	3	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T60	763886	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	6325860	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	6861	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6325860	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	84633	0	0
T5	115176	0	0	0
T12	0	168205	0	0
T13	128064	20184	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	128114	0	0
T31	0	59991	0	0
T47	0	11487	0	0
T48	0	114374	0	0
T49	0	37304	0	0
T57	206645	0	0	0
T80	0	11542	0	0
T81	0	44500	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6861	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	51	0	0
T5	115176	0	0	0
T12	0	100	0	0
T13	128064	51	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	71	0	0
T31	0	72	0	0
T47	0	54	0	0
T48	0	66	0	0
T49	0	90	0	0
T57	206645	0	0	0
T80	0	51	0	0
T81	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	6276123	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	6835	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6276123	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	83553	0	0
T5	115176	0	0	0
T12	0	119447	0	0
T13	128064	19437	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	118362	0	0
T31	0	79684	0	0
T47	0	14869	0	0
T48	0	94644	0	0
T49	0	36061	0	0
T57	206645	0	0	0
T80	0	10511	0	0
T81	0	43380	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6835	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	51	0	0
T5	115176	0	0	0
T12	0	71	0	0
T13	128064	51	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	66	0	0
T31	0	97	0	0
T47	0	72	0	0
T48	0	55	0	0
T49	0	90	0	0
T57	206645	0	0	0
T80	0	51	0	0
T81	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	6212496	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	6746	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6212496	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	82358	0	0
T5	115176	0	0	0
T12	0	149329	0	0
T13	128064	18749	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	122931	0	0
T31	0	59061	0	0
T47	0	13535	0	0
T48	0	113834	0	0
T49	0	25459	0	0
T57	206645	0	0	0
T80	0	9848	0	0
T81	0	42166	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6746	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	51	0	0
T5	115176	0	0	0
T12	0	89	0	0
T13	128064	51	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	69	0	0
T31	0	73	0	0
T47	0	70	0	0
T48	0	66	0	0
T49	0	66	0	0
T57	206645	0	0	0
T80	0	51	0	0
T81	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	6228100	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	6822	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6228100	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	81249	0	0
T5	115176	0	0	0
T12	0	121262	0	0
T13	128064	18037	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	143243	0	0
T31	0	58914	0	0
T47	0	11816	0	0
T48	0	113540	0	0
T49	0	26310	0	0
T57	206645	0	0	0
T80	0	11330	0	0
T81	0	41053	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6822	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	51	0	0
T5	115176	0	0	0
T12	0	73	0	0
T13	128064	51	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	81	0	0
T31	0	74	0	0
T47	0	65	0	0
T48	0	66	0	0
T49	0	69	0	0
T57	206645	0	0	0
T80	0	51	0	0
T81	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1198599	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1256	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1198599	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	1419	0	0
T5	115176	0	0	0
T12	0	13909	0	0
T13	128064	470	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	7476	0	0
T31	0	3381	0	0
T47	0	250	0	0
T48	0	8492	0	0
T49	0	362	0	0
T57	206645	0	0	0
T80	0	195	0	0
T81	0	732	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1256	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	0	0	0
T12	0	8	0	0
T13	128064	1	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	4	0	0
T31	0	4	0	0
T47	0	1	0	0
T48	0	5	0	0
T49	0	1	0	0
T57	206645	0	0	0
T80	0	1	0	0
T81	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1158696	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1246	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1158696	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	1368	0	0
T5	115176	0	0	0
T12	0	13829	0	0
T13	128064	438	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	7338	0	0
T31	0	3267	0	0
T47	0	231	0	0
T48	0	8442	0	0
T49	0	334	0	0
T57	206645	0	0	0
T80	0	204	0	0
T81	0	654	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1246	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	0	0	0
T12	0	8	0	0
T13	128064	1	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	4	0	0
T31	0	4	0	0
T47	0	1	0	0
T48	0	5	0	0
T49	0	1	0	0
T57	206645	0	0	0
T80	0	1	0	0
T81	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1194957	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1279	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1194957	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	1311	0	0
T5	115176	0	0	0
T12	0	13749	0	0
T13	128064	407	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	7204	0	0
T31	0	3148	0	0
T47	0	258	0	0
T48	0	8392	0	0
T49	0	289	0	0
T57	206645	0	0	0
T80	0	153	0	0
T81	0	606	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1279	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	0	0	0
T12	0	8	0	0
T13	128064	1	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	4	0	0
T31	0	4	0	0
T47	0	1	0	0
T48	0	5	0	0
T49	0	1	0	0
T57	206645	0	0	0
T80	0	1	0	0
T81	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T13,T27
1	1	Covered	T4,T13,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T13,T27
0	0	1	Covered	T4,T13,T27
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1142728	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1252	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1142728	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	1247	0	0
T5	115176	0	0	0
T12	0	13669	0	0
T13	128064	371	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	7079	0	0
T31	0	3012	0	0
T47	0	218	0	0
T48	0	8342	0	0
T49	0	258	0	0
T57	206645	0	0	0
T80	0	158	0	0
T81	0	557	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1252	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	0	0	0
T12	0	8	0	0
T13	128064	1	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	4	0	0
T31	0	4	0	0
T47	0	1	0	0
T48	0	5	0	0
T49	0	1	0	0
T57	206645	0	0	0
T80	0	1	0	0
T81	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	6997687	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	7633	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6997687	0	0
T1	102256	13741	0	0
T2	248674	3485	0	0
T3	240086	0	0	0
T4	281603	85133	0	0
T5	115176	14505	0	0
T6	0	1475	0	0
T7	0	2123	0	0
T9	0	1885	0	0
T13	128064	20523	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	128536	0	0
T48	0	114476	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	7633	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	0	0	0
T4	281603	51	0	0
T5	115176	8	0	0
T6	0	1	0	0
T7	0	13	0	0
T9	0	1	0	0
T13	128064	51	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	71	0	0
T48	0	66	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	6826411	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	7477	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6826411	0	0
T1	102256	13665	0	0
T2	248674	3469	0	0
T3	240086	0	0	0
T4	281603	84034	0	0
T5	115176	14489	0	0
T7	0	2097	0	0
T13	128064	19766	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	118716	0	0
T48	0	94724	0	0
T49	0	36643	0	0
T52	0	13988	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	7477	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	0	0	0
T4	281603	51	0	0
T5	115176	8	0	0
T7	0	13	0	0
T13	128064	51	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	66	0	0
T48	0	55	0	0
T49	0	90	0	0
T52	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	6788731	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	7430	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6788731	0	0
T1	102256	13578	0	0
T2	248674	3453	0	0
T3	240086	0	0	0
T4	281603	82899	0	0
T5	115176	14473	0	0
T7	0	2071	0	0
T13	128064	19082	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	123332	0	0
T48	0	113936	0	0
T49	0	25905	0	0
T52	0	13972	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	7430	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	0	0	0
T4	281603	51	0	0
T5	115176	8	0	0
T7	0	13	0	0
T13	128064	51	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	69	0	0
T48	0	66	0	0
T49	0	66	0	0
T52	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	6802694	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	7515	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6802694	0	0
T1	102256	13501	0	0
T2	248674	3437	0	0
T3	240086	0	0	0
T4	281603	81744	0	0
T5	115176	14457	0	0
T7	0	2045	0	0
T13	128064	18487	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	143732	0	0
T48	0	113642	0	0
T49	0	26870	0	0
T52	0	13956	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	7515	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	0	0	0
T4	281603	51	0	0
T5	115176	8	0	0
T7	0	13	0	0
T13	128064	51	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	81	0	0
T48	0	66	0	0
T49	0	69	0	0
T52	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1802924	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	2045	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1802924	0	0
T1	102256	13413	0	0
T2	248674	3421	0	0
T3	240086	0	0	0
T4	281603	1398	0	0
T5	115176	14441	0	0
T6	0	1462	0	0
T7	0	2019	0	0
T9	0	1874	0	0
T13	128064	455	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	7408	0	0
T48	0	8472	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	2045	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	8	0	0
T6	0	1	0	0
T7	0	13	0	0
T9	0	1	0	0
T13	128064	1	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	4	0	0
T48	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1722465	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1941	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1722465	0	0
T1	102256	13361	0	0
T2	248674	3405	0	0
T3	240086	0	0	0
T4	281603	1348	0	0
T5	115176	14425	0	0
T7	0	1993	0	0
T13	128064	424	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	7278	0	0
T48	0	8422	0	0
T49	0	319	0	0
T52	0	13924	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1941	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	8	0	0
T7	0	13	0	0
T13	128064	1	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	4	0	0
T48	0	5	0	0
T49	0	1	0	0
T52	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1657477	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1909	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1657477	0	0
T1	102256	13261	0	0
T2	248674	3389	0	0
T3	240086	0	0	0
T4	281603	1283	0	0
T5	115176	14409	0	0
T7	0	1967	0	0
T13	128064	389	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	7160	0	0
T48	0	8372	0	0
T49	0	273	0	0
T52	0	13908	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1909	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	8	0	0
T7	0	13	0	0
T13	128064	1	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	4	0	0
T48	0	5	0	0
T49	0	1	0	0
T52	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1712396	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1941	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1712396	0	0
T1	102256	13166	0	0
T2	248674	3373	0	0
T3	240086	0	0	0
T4	281603	1225	0	0
T5	115176	14393	0	0
T7	0	1941	0	0
T13	128064	474	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	7010	0	0
T48	0	8322	0	0
T49	0	369	0	0
T52	0	13892	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1941	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	8	0	0
T7	0	13	0	0
T13	128064	1	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	4	0	0
T48	0	5	0	0
T49	0	1	0	0
T52	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1791234	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	2030	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1791234	0	0
T1	102256	13091	0	0
T2	248674	3357	0	0
T3	240086	0	0	0
T4	281603	1388	0	0
T5	115176	14377	0	0
T6	0	1445	0	0
T7	0	1915	0	0
T9	0	1865	0	0
T13	128064	447	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	7386	0	0
T48	0	8462	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	2030	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	8	0	0
T6	0	1	0	0
T7	0	13	0	0
T9	0	1	0	0
T13	128064	1	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	4	0	0
T48	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1663286	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1908	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1663286	0	0
T1	102256	13020	0	0
T2	248674	3341	0	0
T3	240086	0	0	0
T4	281603	1332	0	0
T5	115176	14361	0	0
T7	0	1889	0	0
T13	128064	412	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	7252	0	0
T48	0	8412	0	0
T49	0	311	0	0
T52	0	13860	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1908	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	8	0	0
T7	0	13	0	0
T13	128064	1	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	4	0	0
T48	0	5	0	0
T49	0	1	0	0
T52	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1753576	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1999	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1753576	0	0
T1	102256	12936	0	0
T2	248674	3325	0	0
T3	240086	0	0	0
T4	281603	1273	0	0
T5	115176	14345	0	0
T7	0	1863	0	0
T13	128064	387	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	7139	0	0
T48	0	8362	0	0
T49	0	268	0	0
T52	0	13844	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1999	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	8	0	0
T7	0	13	0	0
T13	128064	1	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	4	0	0
T48	0	5	0	0
T49	0	1	0	0
T52	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	1682930	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1942	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1682930	0	0
T1	102256	12836	0	0
T2	248674	3309	0	0
T3	240086	0	0	0
T4	281603	1214	0	0
T5	115176	14329	0	0
T7	0	1837	0	0
T13	128064	465	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	6978	0	0
T48	0	8312	0	0
T49	0	360	0	0
T52	0	13828	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1942	0	0
T1	102256	8	0	0
T2	248674	8	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	8	0	0
T7	0	13	0	0
T13	128064	1	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T27	0	4	0	0
T48	0	5	0	0
T49	0	1	0	0
T52	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T9,T11,T21

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T9,T11,T21
1	1	Covered	T9,T11,T21

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T21
1	-	Covered	T9,T11,T21

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T9,T11,T21

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T9,T11,T21
1	1	Covered	T9,T11,T21

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T9,T11,T21
0	0	1	Covered	T9,T11,T21
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T9,T11,T21
0	0	1	Covered	T9,T11,T21
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1277240674	968262	0	0
DstReqKnown_A	7472508	6600501	0	0
SrcAckBusyChk_A	1277240674	1060	0	0
SrcBusyKnown_A	1277240674	1275432517	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	968262	0	0
T9	339047	3759	0	0
T11	0	1909	0	0
T21	0	1683	0	0
T34	0	828	0	0
T38	0	841	0	0
T49	777818	0	0	0
T50	86236	0	0	0
T51	72799	0	0	0
T64	0	2990	0	0
T68	0	698	0	0
T75	243728	0	0	0
T76	45801	0	0	0
T77	255907	0	0	0
T82	0	7111	0	0
T83	0	1703	0	0
T84	0	981	0	0
T85	172589	0	0	0
T86	50827	0	0	0
T87	51183	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7472508	6600501	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1060	0	0
T9	339047	2	0	0
T11	0	2	0	0
T21	0	2	0	0
T34	0	6	0	0
T38	0	2	0	0
T49	777818	0	0	0
T50	86236	0	0	0
T51	72799	0	0	0
T64	0	2	0	0
T68	0	2	0	0
T75	243728	0	0	0
T76	45801	0	0	0
T77	255907	0	0	0
T82	0	4	0	0
T83	0	2	0	0
T84	0	2	0	0
T85	172589	0	0	0
T86	50827	0	0	0
T87	51183	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1275432517	0	0
T1	102256	102042	0	0
T2	248674	248152	0	0
T3	240086	239993	0	0
T4	281603	281595	0	0
T5	115176	114995	0	0
T13	128064	128056	0	0
T14	250527	250462	0	0
T15	342330	342275	0	0
T16	44781	44697	0	0
T17	25470	25388	0	0