Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T12,T6,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T12,T6,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T12,T6,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T6,T19
1	0	Covered	T1,T2,T5
1	1	Covered	T12,T6,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T19,T45
0	1	Covered	T12,T78,T101
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T45,T48
0	1	Covered	T6,T19,T45
1	0	Covered	T30,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T45,T48
1	-	Covered	T6,T19,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T6,T19
DetectSt	168	Covered	T12,T6,T19
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T6,T19,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T6,T19
DebounceSt->IdleSt	163	Covered	T6,T19,T85
DetectSt->IdleSt	186	Covered	T12,T78,T101
DetectSt->StableSt	191	Covered	T6,T19,T45
IdleSt->DebounceSt	148	Covered	T12,T6,T19
StableSt->IdleSt	206	Covered	T6,T19,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T6,T19
0	1	Covered	T12,T6,T19
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T6,T19
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T6,T19
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T6,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T19,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T6,T19
DetectSt	-	-	-	-	1	-	-	Covered	T12,T78,T101
DetectSt	-	-	-	-	0	1	-	Covered	T6,T19,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T19,T45
StableSt	-	-	-	-	-	-	0	Covered	T6,T45,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	276	0	0
CntIncr_A	6888596	184712	0	0
CntNoWrap_A	6888596	6256632	0	0
DetectStDropOut_A	6888596	3	0	0
DetectedOut_A	6888596	822	0	0
DetectedPulseOut_A	6888596	127	0	0
DisabledIdleSt_A	6888596	6008370	0	0
DisabledNoDetection_A	6888596	6010594	0	0
EnterDebounceSt_A	6888596	151	0	0
EnterDetectSt_A	6888596	130	0	0
EnterStableSt_A	6888596	127	0	0
PulseIsPulse_A	6888596	127	0	0
StayInStableSt	6888596	695	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6888596	6868	0	0
gen_low_level_sva.LowLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	125	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	276	0	0
T3	14242	0	0	0
T4	5536	0	0	0
T6	16040	7	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	2	0	0
T13	522	0	0	0
T19	32178	3	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T45	0	4	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	4	0	0
T88	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	184712	0	0
T3	14242	0	0	0
T4	5536	0	0	0
T6	16040	174	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	94	0	0
T13	522	0	0	0
T19	32178	31599	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T45	0	82	0	0
T48	0	17	0	0
T49	0	113	0	0
T50	0	68	0	0
T51	0	23	0	0
T52	0	141	0	0
T88	0	34	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256632	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11598	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	297	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	3	0	0
T3	14242	0	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	1	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T78	0	1	0	0
T101	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	822	0	0
T6	16040	20	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T19	32178	1	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T45	0	8	0	0
T48	0	10	0	0
T49	0	11	0	0
T50	0	10	0	0
T51	0	6	0	0
T52	0	5	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T88	0	2	0	0
T108	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	127	0	0
T6	16040	3	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T19	32178	1	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T45	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T88	0	1	0	0
T108	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6008370	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11263	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	167	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6010594	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11276	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	168	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	151	0	0
T3	14242	0	0	0
T4	5536	0	0	0
T6	16040	4	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	1	0	0
T13	522	0	0	0
T19	32178	2	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T45	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T88	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	130	0	0
T3	14242	0	0	0
T4	5536	0	0	0
T6	16040	3	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	1	0	0
T13	522	0	0	0
T19	32178	1	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T45	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T88	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	127	0	0
T6	16040	3	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T19	32178	1	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T45	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T88	0	1	0	0
T108	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	127	0	0
T6	16040	3	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T19	32178	1	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T45	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T88	0	1	0	0
T108	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	695	0	0
T6	16040	17	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T45	0	6	0	0
T48	0	9	0	0
T49	0	9	0	0
T50	0	9	0	0
T51	0	5	0	0
T52	0	3	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T78	0	12	0	0
T88	0	1	0	0
T108	0	6	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6868	0	0
T1	14429	13	0	0
T2	4856	29	0	0
T3	14242	35	0	0
T4	5536	28	0	0
T5	4420	0	0	0
T6	16040	30	0	0
T7	15865	11	0	0
T8	25329	15	0	0
T12	700	3	0	0
T13	522	5	0	0
T20	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	125	0	0
T6	16040	3	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T19	32178	1	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T45	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T88	0	1	0	0
T108	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T6,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T2,T5
1	1	Covered	T6,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T11
0	1	Covered	T60,T85,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T11
0	1	Unreachable
1	0	Covered	T6,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T11
DetectSt	168	Covered	T6,T9,T11
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T6,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T11
DebounceSt->IdleSt	163	Covered	T49,T58,T74
DetectSt->IdleSt	186	Covered	T60,T85,T86
DetectSt->StableSt	191	Covered	T6,T9,T11
IdleSt->DebounceSt	148	Covered	T6,T9,T11
StableSt->IdleSt	206	Covered	T6,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T9,T11
0	1	Covered	T6,T9,T11
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T11
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T30,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T58,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T60,T85,T86
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	200	0	0
CntIncr_A	6888596	16507	0	0
CntNoWrap_A	6888596	6256708	0	0
DetectStDropOut_A	6888596	24	0	0
DetectedOut_A	6888596	6616	0	0
DetectedPulseOut_A	6888596	39	0	0
DisabledIdleSt_A	6888596	5577350	0	0
DisabledNoDetection_A	6888596	5579623	0	0
EnterDebounceSt_A	6888596	138	0	0
EnterDetectSt_A	6888596	63	0	0
EnterStableSt_A	6888596	39	0	0
PulseIsPulse_A	6888596	39	0	0
StayInStableSt	6888596	6577	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6888596	6868	0	0
gen_low_level_sva.LowLevelEvent_A	6888596	6259184	0	0
gen_sticky_sva.StableStDropOut_A	6888596	469432	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	200	0	0
T6	16040	2	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	2	0	0
T11	0	2	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T49	0	6	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	4	0	0
T58	0	3	0	0
T59	0	2	0	0
T60	0	2	0	0
T74	0	3	0	0
T112	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	16507	0	0
T6	16040	34	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	62	0	0
T11	0	37	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T49	0	130	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	132	0	0
T58	0	93	0	0
T59	0	70	0	0
T60	0	25	0	0
T74	0	42	0	0
T112	0	140	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256708	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11603	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	24	0	0
T32	1081	0	0	0
T33	781	0	0	0
T34	850	0	0	0
T60	877	1	0	0
T61	592	0	0	0
T62	1852	0	0	0
T63	494	0	0	0
T78	686	0	0	0
T80	0	4	0	0
T85	0	1	0	0
T86	0	1	0	0
T116	0	1	0	0
T117	0	3	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	8	0	0
T121	0	3	0	0
T122	404	0	0	0
T123	587	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6616	0	0
T6	16040	157	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	436	0	0
T11	0	174	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	135	0	0
T44	5025	0	0	0
T49	0	101	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	258	0	0
T59	0	18	0	0
T86	0	150	0	0
T99	0	487	0	0
T114	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	39	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	1	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	1	0	0
T44	5025	0	0	0
T49	0	1	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	2	0	0
T59	0	1	0	0
T86	0	1	0	0
T99	0	2	0	0
T114	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5577350	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11331	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5579623	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11345	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	138	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	1	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T49	0	5	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	2	0	0
T58	0	3	0	0
T59	0	1	0	0
T60	0	1	0	0
T74	0	3	0	0
T112	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	63	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	1	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	1	0	0
T44	5025	0	0	0
T49	0	1	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	39	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	1	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	1	0	0
T44	5025	0	0	0
T49	0	1	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	2	0	0
T59	0	1	0	0
T86	0	1	0	0
T99	0	2	0	0
T114	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	39	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	1	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	1	0	0
T44	5025	0	0	0
T49	0	1	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	2	0	0
T59	0	1	0	0
T86	0	1	0	0
T99	0	2	0	0
T114	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6577	0	0
T6	16040	156	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	435	0	0
T11	0	173	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	134	0	0
T44	5025	0	0	0
T49	0	100	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	256	0	0
T59	0	17	0	0
T86	0	149	0	0
T99	0	485	0	0
T114	0	6	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6868	0	0
T1	14429	13	0	0
T2	4856	29	0	0
T3	14242	35	0	0
T4	5536	28	0	0
T5	4420	0	0	0
T6	16040	30	0	0
T7	15865	11	0	0
T8	25329	15	0	0
T12	700	3	0	0
T13	522	5	0	0
T20	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	469432	0	0
T6	16040	59	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	319	0	0
T11	0	194	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	48	0	0
T44	5025	0	0	0
T49	0	277	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	157	0	0
T59	0	107	0	0
T86	0	203870	0	0
T99	0	338	0	0
T114	0	83	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T13,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T13,T6
1	1	Covered	T4,T13,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T6,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T11,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T11
1	0	Covered	T4,T13,T6
1	1	Covered	T6,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T49
0	1	Covered	T82,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T49
0	1	Unreachable
1	0	Covered	T6,T11,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T11
DetectSt	168	Covered	T6,T11,T49
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T6,T11,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T11,T49
DebounceSt->IdleSt	163	Covered	T9,T57,T59
DetectSt->IdleSt	186	Covered	T82,T83,T84
DetectSt->StableSt	191	Covered	T6,T11,T49
IdleSt->DebounceSt	148	Covered	T6,T9,T11
StableSt->IdleSt	206	Covered	T6,T11,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T9,T11
0	1	Covered	T6,T9,T11
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T11,T49
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T13,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T30,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T11,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T57,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T82,T83,T84
DetectSt	-	-	-	-	0	1	-	Covered	T6,T11,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T11,T49
StableSt	-	-	-	-	-	-	0	Covered	T6,T11,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	157	0	0
CntIncr_A	6888596	106811	0	0
CntNoWrap_A	6888596	6256751	0	0
DetectStDropOut_A	6888596	9	0	0
DetectedOut_A	6888596	485180	0	0
DetectedPulseOut_A	6888596	45	0	0
DisabledIdleSt_A	6888596	5577350	0	0
DisabledNoDetection_A	6888596	5579623	0	0
EnterDebounceSt_A	6888596	104	0	0
EnterDetectSt_A	6888596	54	0	0
EnterStableSt_A	6888596	45	0	0
PulseIsPulse_A	6888596	45	0	0
StayInStableSt	6888596	485135	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_sticky_sva.StableStDropOut_A	6888596	81293	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	157	0	0
T6	16040	2	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	5	0	0
T11	0	2	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T49	0	4	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	3	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	106811	0	0
T6	16040	32	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	425	0	0
T11	0	58	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T49	0	113	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	111	0	0
T58	0	74	0	0
T59	0	86	0	0
T60	0	76	0	0
T61	0	77	0	0
T74	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256751	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11603	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	9	0	0
T80	3661	0	0	0
T82	574	1	0	0
T83	0	1	0	0
T84	0	4	0	0
T120	0	2	0	0
T124	0	1	0	0
T125	693	0	0	0
T126	4724	0	0	0
T127	497	0	0	0
T128	1050	0	0	0
T129	494	0	0	0
T130	954	0	0	0
T131	495	0	0	0
T132	3125	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	485180	0	0
T6	16040	155	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T11	0	119	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	94	0	0
T44	5025	0	0	0
T49	0	547	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T58	0	238	0	0
T61	0	51	0	0
T74	0	233	0	0
T85	0	655	0	0
T112	0	90	0	0
T113	0	598	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	45	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	1	0	0
T44	5025	0	0	0
T49	0	2	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T58	0	1	0	0
T61	0	1	0	0
T74	0	1	0	0
T85	0	1	0	0
T112	0	1	0	0
T113	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5577350	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11331	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5579623	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11345	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	104	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	5	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T49	0	2	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	3	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	54	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	1	0	0
T44	5025	0	0	0
T49	0	2	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T58	0	1	0	0
T61	0	1	0	0
T74	0	1	0	0
T85	0	1	0	0
T112	0	1	0	0
T113	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	45	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	1	0	0
T44	5025	0	0	0
T49	0	2	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T58	0	1	0	0
T61	0	1	0	0
T74	0	1	0	0
T85	0	1	0	0
T112	0	1	0	0
T113	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	45	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	1	0	0
T44	5025	0	0	0
T49	0	2	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T58	0	1	0	0
T61	0	1	0	0
T74	0	1	0	0
T85	0	1	0	0
T112	0	1	0	0
T113	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	485135	0	0
T6	16040	154	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T11	0	118	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	93	0	0
T44	5025	0	0	0
T49	0	545	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T58	0	237	0	0
T61	0	50	0	0
T74	0	232	0	0
T85	0	654	0	0
T112	0	89	0	0
T113	0	596	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	81293	0	0
T6	16040	74	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T11	0	220	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	117	0	0
T44	5025	0	0	0
T49	0	417	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T58	0	107	0	0
T61	0	25	0	0
T74	0	82	0	0
T85	0	117	0	0
T112	0	167	0	0
T113	0	604	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T6,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T11
0	1	Covered	T49,T80,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T11
0	1	Unreachable
1	0	Covered	T6,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T11
DetectSt	168	Covered	T6,T9,T11
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T6,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T11
DebounceSt->IdleSt	163	Covered	T49,T61,T112
DetectSt->IdleSt	186	Covered	T49,T80,T81
DetectSt->StableSt	191	Covered	T6,T9,T11
IdleSt->DebounceSt	148	Covered	T6,T9,T11
StableSt->IdleSt	206	Covered	T6,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T9,T11
0	1	Covered	T6,T9,T11
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T11
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T30,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T61,T112
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T49,T80,T81
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	184	0	0
CntIncr_A	6888596	67134	0	0
CntNoWrap_A	6888596	6256724	0	0
DetectStDropOut_A	6888596	19	0	0
DetectedOut_A	6888596	12270	0	0
DetectedPulseOut_A	6888596	44	0	0
DisabledIdleSt_A	6888596	5577350	0	0
DisabledNoDetection_A	6888596	5579623	0	0
EnterDebounceSt_A	6888596	122	0	0
EnterDetectSt_A	6888596	63	0	0
EnterStableSt_A	6888596	44	0	0
PulseIsPulse_A	6888596	44	0	0
StayInStableSt	6888596	12226	0	0
gen_high_event_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_sticky_sva.StableStDropOut_A	6888596	351550	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	184	0	0
T6	16040	2	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	2	0	0
T11	0	2	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T49	0	11	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	4	0	0
T58	0	2	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	1	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	67134	0	0
T6	16040	47	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	23	0	0
T11	0	73	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T49	0	382	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	62	0	0
T58	0	29	0	0
T59	0	46	0	0
T60	0	18	0	0
T61	0	78	0	0
T74	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256724	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11603	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	19	0	0
T49	8866	4	0	0
T50	661	0	0	0
T57	1546	0	0	0
T68	504	0	0	0
T69	524	0	0	0
T80	0	1	0	0
T81	0	7	0	0
T106	1127	0	0	0
T107	402	0	0	0
T116	0	2	0	0
T124	0	2	0	0
T133	0	2	0	0
T134	0	1	0	0
T135	758	0	0	0
T136	440	0	0	0
T137	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	12270	0	0
T6	16040	117	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	110	0	0
T11	0	303	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	132	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	96	0	0
T58	0	107	0	0
T59	0	32	0	0
T60	0	7	0	0
T74	0	145	0	0
T85	0	700	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	44	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	1	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T74	0	1	0	0
T85	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5577350	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11331	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5579623	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11345	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	122	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	1	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T49	0	7	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	63	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	1	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	1	0	0
T44	5025	0	0	0
T49	0	4	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T74	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	44	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	1	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T74	0	1	0	0
T85	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	44	0	0
T6	16040	1	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	1	0	0
T11	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T74	0	1	0	0
T85	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	12226	0	0
T6	16040	116	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	109	0	0
T11	0	302	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	131	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	94	0	0
T58	0	106	0	0
T59	0	31	0	0
T60	0	6	0	0
T74	0	144	0	0
T85	0	699	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	351550	0	0
T6	16040	104	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	701	0	0
T11	0	39	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T36	0	64	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T57	0	401	0	0
T58	0	288	0	0
T59	0	121	0	0
T60	0	100	0	0
T74	0	207	0	0
T85	0	88	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T35,T34,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T35,T34,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T35,T34,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T38,T35
1	0	Covered	T1,T2,T5
1	1	Covered	T35,T34,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T34,T41
0	1	Covered	T138,T139
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T34,T41
0	1	Covered	T37,T138,T99
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T34,T41
1	-	Covered	T37,T138,T99

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T34,T41
DetectSt	168	Covered	T35,T34,T41
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T35,T34,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T34,T41
DebounceSt->IdleSt	163	Covered	T140,T76,T141
DetectSt->IdleSt	186	Covered	T138,T139
DetectSt->StableSt	191	Covered	T35,T34,T41
IdleSt->DebounceSt	148	Covered	T35,T34,T41
StableSt->IdleSt	206	Covered	T37,T30,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T35,T34,T41
0	1	Covered	T35,T34,T41
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T34,T41
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T34,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T34,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T140,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T34,T41
DetectSt	-	-	-	-	1	-	-	Covered	T138,T139
DetectSt	-	-	-	-	0	1	-	Covered	T35,T34,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T30,T138
StableSt	-	-	-	-	-	-	0	Covered	T35,T34,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	95	0	0
CntIncr_A	6888596	4256	0	0
CntNoWrap_A	6888596	6256813	0	0
DetectStDropOut_A	6888596	2	0	0
DetectedOut_A	6888596	5566	0	0
DetectedPulseOut_A	6888596	44	0	0
DisabledIdleSt_A	6888596	6045049	0	0
DisabledNoDetection_A	6888596	6047264	0	0
EnterDebounceSt_A	6888596	49	0	0
EnterDetectSt_A	6888596	46	0	0
EnterStableSt_A	6888596	44	0	0
PulseIsPulse_A	6888596	44	0	0
StayInStableSt	6888596	5499	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	95	0	0
T30	0	2	0	0
T31	0	2	0	0
T34	0	2	0	0
T35	665	2	0	0
T37	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	2	0	0
T90	427	0	0	0
T104	919	0	0	0
T138	0	6	0	0
T142	0	2	0	0
T143	423	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	4256	0	0
T30	0	41	0	0
T31	0	70	0	0
T34	0	82	0	0
T35	665	21	0	0
T37	0	77	0	0
T40	0	80	0	0
T41	0	56	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	95	0	0
T90	427	0	0	0
T104	919	0	0	0
T138	0	212	0	0
T142	0	12	0	0
T143	423	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256813	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	2	0	0
T113	1841	0	0	0
T138	23403	1	0	0
T139	0	1	0	0
T142	551	0	0	0
T144	553	0	0	0
T145	99362	0	0	0
T146	5297	0	0	0
T147	697	0	0	0
T148	488	0	0	0
T149	510	0	0	0
T150	741	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5566	0	0
T30	0	1	0	0
T31	0	110	0	0
T34	0	80	0	0
T35	665	151	0	0
T37	0	157	0	0
T40	0	40	0	0
T41	0	51	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	43	0	0
T90	427	0	0	0
T104	919	0	0	0
T138	0	67	0	0
T142	0	44	0	0
T143	423	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	44	0	0
T30	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T35	665	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	1	0	0
T90	427	0	0	0
T104	919	0	0	0
T138	0	2	0	0
T142	0	1	0	0
T143	423	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6045049	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6047264	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	49	0	0
T30	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T35	665	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	1	0	0
T90	427	0	0	0
T104	919	0	0	0
T138	0	3	0	0
T142	0	1	0	0
T143	423	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	46	0	0
T30	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T35	665	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	1	0	0
T90	427	0	0	0
T104	919	0	0	0
T138	0	3	0	0
T142	0	1	0	0
T143	423	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	44	0	0
T30	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T35	665	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	1	0	0
T90	427	0	0	0
T104	919	0	0	0
T138	0	2	0	0
T142	0	1	0	0
T143	423	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	44	0	0
T30	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T35	665	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	1	0	0
T90	427	0	0	0
T104	919	0	0	0
T138	0	2	0	0
T142	0	1	0	0
T143	423	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5499	0	0
T31	0	108	0	0
T34	0	78	0	0
T35	665	149	0	0
T37	0	156	0	0
T40	0	38	0	0
T41	0	49	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	41	0	0
T90	427	0	0	0
T104	919	0	0	0
T138	0	64	0	0
T142	0	42	0	0
T143	423	0	0	0
T151	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	20	0	0
T30	8245	0	0	0
T31	9256	0	0	0
T37	10761	1	0	0
T85	9925	0	0	0
T87	845	0	0	0
T99	0	1	0	0
T138	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	721	0	0	0
T160	750	0	0	0
T161	24956	0	0	0
T162	429	0	0	0
T163	25787	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T18,T35,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T18,T35,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T18,T35,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T38,T35
1	0	Covered	T1,T5,T3
1	1	Covered	T18,T35,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T35,T29
0	1	Covered	T155,T164
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T35,T29
0	1	Covered	T35,T29,T41
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T35,T29
1	-	Covered	T35,T29,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T35,T29
DetectSt	168	Covered	T18,T35,T29
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T18,T35,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T35,T29
DebounceSt->IdleSt	163	Covered	T76,T165,T166
DetectSt->IdleSt	186	Covered	T155,T164
DetectSt->StableSt	191	Covered	T18,T35,T29
IdleSt->DebounceSt	148	Covered	T18,T35,T29
StableSt->IdleSt	206	Covered	T18,T35,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T35,T29
0	1	Covered	T18,T35,T29
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T35,T29
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T35,T29
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T35,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T165,T166,T167
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T35,T29
DetectSt	-	-	-	-	1	-	-	Covered	T155,T164
DetectSt	-	-	-	-	0	1	-	Covered	T18,T35,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T29,T41
StableSt	-	-	-	-	-	-	0	Covered	T18,T35,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	139	0	0
CntIncr_A	6888596	61355	0	0
CntNoWrap_A	6888596	6256769	0	0
DetectStDropOut_A	6888596	2	0	0
DetectedOut_A	6888596	112901	0	0
DetectedPulseOut_A	6888596	65	0	0
DisabledIdleSt_A	6888596	6046945	0	0
DisabledNoDetection_A	6888596	6049167	0	0
EnterDebounceSt_A	6888596	72	0	0
EnterDetectSt_A	6888596	67	0	0
EnterStableSt_A	6888596	65	0	0
PulseIsPulse_A	6888596	65	0	0
StayInStableSt	6888596	112801	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6888596	2509	0	0
gen_low_level_sva.LowLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	139	0	0
T18	2067	2	0	0
T29	0	4	0	0
T30	0	2	0	0
T35	665	2	0	0
T37	0	4	0	0
T38	1986	0	0	0
T41	0	2	0	0
T42	8434	0	0	0
T47	780	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T87	0	2	0	0
T89	423	0	0	0
T90	427	0	0	0
T138	0	4	0	0
T143	423	0	0	0
T148	0	2	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	61355	0	0
T18	2067	41	0	0
T29	0	52	0	0
T30	0	41	0	0
T35	665	21	0	0
T37	0	154	0	0
T38	1986	0	0	0
T41	0	56	0	0
T42	8434	0	0	0
T47	780	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T87	0	95	0	0
T89	423	0	0	0
T90	427	0	0	0
T138	0	186	0	0
T143	423	0	0	0
T148	0	25	0	0
T168	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256769	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	2	0	0
T155	72176	1	0	0
T156	584	0	0	0
T164	0	1	0	0
T169	456	0	0	0
T170	772	0	0	0
T171	402	0	0	0
T172	8476	0	0	0
T173	27659	0	0	0
T174	523	0	0	0
T175	426	0	0	0
T176	494	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	112901	0	0
T18	2067	40	0	0
T29	0	84	0	0
T30	0	1	0	0
T35	665	39	0	0
T37	0	106	0	0
T38	1986	0	0	0
T41	0	9	0	0
T42	8434	0	0	0
T47	780	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T87	0	96	0	0
T89	423	0	0	0
T90	427	0	0	0
T138	0	358	0	0
T143	423	0	0	0
T148	0	53	0	0
T168	0	61	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	65	0	0
T18	2067	1	0	0
T29	0	2	0	0
T30	0	1	0	0
T35	665	1	0	0
T37	0	2	0	0
T38	1986	0	0	0
T41	0	1	0	0
T42	8434	0	0	0
T47	780	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T87	0	1	0	0
T89	423	0	0	0
T90	427	0	0	0
T138	0	2	0	0
T143	423	0	0	0
T148	0	1	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6046945	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6049167	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	72	0	0
T18	2067	1	0	0
T29	0	2	0	0
T30	0	1	0	0
T35	665	1	0	0
T37	0	2	0	0
T38	1986	0	0	0
T41	0	1	0	0
T42	8434	0	0	0
T47	780	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T87	0	1	0	0
T89	423	0	0	0
T90	427	0	0	0
T138	0	2	0	0
T143	423	0	0	0
T148	0	1	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	67	0	0
T18	2067	1	0	0
T29	0	2	0	0
T30	0	1	0	0
T35	665	1	0	0
T37	0	2	0	0
T38	1986	0	0	0
T41	0	1	0	0
T42	8434	0	0	0
T47	780	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T87	0	1	0	0
T89	423	0	0	0
T90	427	0	0	0
T138	0	2	0	0
T143	423	0	0	0
T148	0	1	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	65	0	0
T18	2067	1	0	0
T29	0	2	0	0
T30	0	1	0	0
T35	665	1	0	0
T37	0	2	0	0
T38	1986	0	0	0
T41	0	1	0	0
T42	8434	0	0	0
T47	780	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T87	0	1	0	0
T89	423	0	0	0
T90	427	0	0	0
T138	0	2	0	0
T143	423	0	0	0
T148	0	1	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	65	0	0
T18	2067	1	0	0
T29	0	2	0	0
T30	0	1	0	0
T35	665	1	0	0
T37	0	2	0	0
T38	1986	0	0	0
T41	0	1	0	0
T42	8434	0	0	0
T47	780	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T87	0	1	0	0
T89	423	0	0	0
T90	427	0	0	0
T138	0	2	0	0
T143	423	0	0	0
T148	0	1	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	112801	0	0
T18	2067	38	0	0
T29	0	81	0	0
T35	665	38	0	0
T37	0	103	0	0
T38	1986	0	0	0
T41	0	8	0	0
T42	8434	0	0	0
T47	780	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T87	0	95	0	0
T89	423	0	0	0
T90	427	0	0	0
T138	0	355	0	0
T143	423	0	0	0
T148	0	51	0	0
T150	0	149	0	0
T168	0	59	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	2509	0	0
T4	5536	24	0	0
T6	16040	14	0	0
T7	15865	0	0	0
T8	25329	8	0	0
T9	1274	0	0	0
T13	522	5	0	0
T17	0	4	0	0
T18	0	4	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T53	4868	16	0	0
T54	0	1	0	0
T109	0	2	0	0
T110	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	29	0	0
T29	0	1	0	0
T35	665	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	1	0	0
T90	427	0	0	0
T99	0	1	0	0
T104	919	0	0	0
T138	0	1	0	0
T143	423	0	0	0
T150	0	1	0	0
T153	0	2	0	0
T177	0	1	0	0