Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	97.61	97.83	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.61	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
91.56	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T46,T75,T24
1	0	Covered	T30,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T30,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T12,T4,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T12,T4,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T12,T4,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T4,T6
1	0	Covered	T1,T2,T5
1	1	Covered	T12,T4,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T19
0	1	Covered	T12,T8,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T45
0	1	Covered	T4,T6,T19
1	0	Covered	T30,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T6,T45
1	-	Covered	T4,T6,T19

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T2,T3,T20
1	1	Covered	T2,T3,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T20
0	1	Covered	T2,T42,T56
1	0	Covered	T2,T42,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T20
0	1	Covered	T2,T3,T20
1	0	Covered	T76,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T20
1	-	Covered	T2,T3,T20

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T11
0	1	Covered	T49,T80,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T11
0	1	Unreachable
1	0	Covered	T6,T9,T11

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.61	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
91.56	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T8,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T8,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T8,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T18
1	0	Covered	T1,T2,T5
1	1	Covered	T4,T8,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T38
0	1	Covered	T35,T33,T40
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T38,T35
0	1	Covered	T4,T8,T38
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T38,T35
1	-	Covered	T4,T8,T38

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T13,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T13,T6
1	1	Covered	T4,T13,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T11,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T11
1	0	Covered	T4,T13,T6
1	1	Covered	T6,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T49
0	1	Covered	T82,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T49
0	1	Unreachable
1	0	Covered	T6,T11,T49

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T6,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T2,T5
1	1	Covered	T6,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T11
0	1	Covered	T60,T85,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T11
0	1	Unreachable
1	0	Covered	T6,T9,T11

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T4,T6
DetectSt	168	Covered	T12,T4,T6
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T4,T6,T19

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T4,T6
DebounceSt->IdleSt	163	Covered	T6,T19,T36
DetectSt->IdleSt	186	Covered	T12,T8,T60
DetectSt->StableSt	191	Covered	T4,T6,T19
IdleSt->DebounceSt	148	Covered	T12,T4,T6
StableSt->IdleSt	206	Covered	T4,T6,T19

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
91.56	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T4,T6
0	1	Covered	T12,T4,T6
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T4,T6
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T12,T4,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T30,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T4,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T19,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T4,T6
DetectSt	-	-	-	-	1	-	-	Covered	T12,T8,T60
DetectSt	-	-	-	-	0	1	-	Covered	T4,T6,T19
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T4,T6,T19
StableSt	-	-	-	-	-	-	0	Covered	T4,T6,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T30,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T49,T61
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T2,T42,T56
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T20
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T6
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T6
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	179103496	18722	0	0
CntIncr_A	179103496	1859293	0	0
CntNoWrap_A	179103496	162660886	0	0
DetectStDropOut_A	179103496	1848	0	0
DetectedOut_A	179103496	1386187	0	0
DetectedPulseOut_A	179103496	6321	0	0
DisabledIdleSt_A	179103496	154154641	0	0
DisabledNoDetection_A	179103496	154209553	0	0
EnterDebounceSt_A	179103496	9645	0	0
EnterDetectSt_A	179103496	9092	0	0
EnterStableSt_A	179103496	6321	0	0
PulseIsPulse_A	179103496	6321	0	0
StayInStableSt	179103496	1378918	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	61997364	50835	0	0
gen_high_event_sva.HighLevelEvent_A	34442980	31295920	0	0
gen_high_level_sva.HighLevelEvent_A	117106132	106406128	0	0
gen_low_level_sva.LowLevelEvent_A	61997364	56332656	0	0
gen_not_sticky_sva.StableStDropOut_A	158437708	5205	0	0
gen_sticky_sva.StableStDropOut_A	20665788	902275	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179103496	18722	0	0
T1	28858	0	0	0
T2	29136	28	0	0
T3	128178	22	0	0
T4	49824	3	0	0
T5	26520	0	0	0
T6	144360	7	0	0
T7	142785	8	0	0
T8	227961	2	0	0
T10	0	2	0	0
T12	4900	2	0	0
T13	4698	0	0	0
T18	2067	0	0	0
T19	96534	3	0	0
T20	95599	0	0	0
T35	665	0	0	0
T38	1986	0	0	0
T42	8434	58	0	0
T43	0	62	0	0
T44	15075	0	0	0
T45	0	4	0	0
T46	0	22	0	0
T47	780	0	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	4	0	0
T53	9736	0	0	0
T56	0	66	0	0
T75	0	2	0	0
T88	0	2	0	0
T89	423	0	0	0
T90	427	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179103496	1859293	0	0
T1	28858	0	0	0
T2	29136	590	0	0
T3	128178	598	0	0
T4	49824	45	0	0
T5	26520	0	0	0
T6	144360	174	0	0
T7	142785	244	0	0
T8	227961	63	0	0
T10	0	25	0	0
T12	4900	94	0	0
T13	4698	0	0	0
T18	2067	0	0	0
T19	96534	31599	0	0
T20	95599	0	0	0
T35	665	0	0	0
T38	1986	0	0	0
T42	8434	1370	0	0
T43	0	1136	0	0
T44	15075	0	0	0
T45	0	82	0	0
T46	0	1212	0	0
T47	780	0	0	0
T48	0	17	0	0
T49	0	113	0	0
T50	0	68	0	0
T51	0	23	0	0
T52	0	141	0	0
T53	9736	0	0	0
T56	0	1308	0	0
T75	0	115	0	0
T88	0	34	0	0
T89	423	0	0	0
T90	427	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179103496	162660886	0	0
T1	375154	363986	0	0
T2	126256	115708	0	0
T3	370292	359103	0	0
T4	143936	20417	0	0
T5	114920	260	0	0
T6	417040	301717	0	0
T7	412490	400988	0	0
T8	658554	594808	0	0
T12	18200	7772	0	0
T13	13572	3146	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179103496	1848	0	0
T2	4856	8	0	0
T3	28484	0	0	0
T4	11072	0	0	0
T6	32080	0	0	0
T7	31730	0	0	0
T8	50658	0	0	0
T12	1400	1	0	0
T13	1044	0	0	0
T19	32178	0	0	0
T20	27314	0	0	0
T24	0	14	0	0
T27	0	13	0	0
T43	15341	0	0	0
T44	5025	0	0	0
T48	669	0	0	0
T49	8866	0	0	0
T67	521	0	0	0
T68	504	0	0	0
T71	0	13	0	0
T75	10187	1	0	0
T77	0	18	0	0
T78	0	1	0	0
T91	0	11	0	0
T92	0	3	0	0
T93	0	10	0	0
T94	0	30	0	0
T95	0	5	0	0
T96	0	5	0	0
T97	0	20	0	0
T98	0	1	0	0
T99	0	2	0	0
T100	0	3	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	8	0	0
T104	919	0	0	0
T105	826	0	0	0
T106	1127	0	0	0
T107	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179103496	1386187	0	0
T1	28858	0	0	0
T2	14568	0	0	0
T3	113936	437	0	0
T4	44288	3	0	0
T5	13260	0	0	0
T6	144360	20	0	0
T7	142785	182	0	0
T8	227961	57	0	0
T9	1274	0	0	0
T10	0	4	0	0
T12	2100	0	0	0
T13	4176	0	0	0
T18	2067	0	0	0
T19	193068	1	0	0
T20	95599	807	0	0
T38	1986	0	0	0
T42	0	4220	0	0
T43	0	1300	0	0
T44	30150	0	0	0
T45	0	8	0	0
T46	0	46	0	0
T47	780	0	0	0
T48	0	10	0	0
T49	0	11	0	0
T50	0	10	0	0
T51	0	6	0	0
T52	0	5	0	0
T53	29208	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T56	0	2031	0	0
T72	0	7249	0	0
T88	0	2	0	0
T89	423	0	0	0
T108	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179103496	6321	0	0
T1	28858	0	0	0
T2	14568	0	0	0
T3	113936	11	0	0
T4	44288	1	0	0
T5	13260	0	0	0
T6	144360	3	0	0
T7	142785	4	0	0
T8	227961	1	0	0
T9	1274	0	0	0
T10	0	1	0	0
T12	2100	0	0	0
T13	4176	0	0	0
T18	2067	0	0	0
T19	193068	1	0	0
T20	95599	9	0	0
T38	1986	0	0	0
T42	0	29	0	0
T43	0	31	0	0
T44	30150	0	0	0
T45	0	2	0	0
T46	0	10	0	0
T47	780	0	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	29208	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T56	0	33	0	0
T72	0	28	0	0
T88	0	1	0	0
T89	423	0	0	0
T108	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179103496	154154641	0	0
T1	375154	348288	0	0
T2	126256	106350	0	0
T3	370292	337857	0	0
T4	143936	18264	0	0
T5	114920	260	0	0
T6	417040	300566	0	0
T7	412490	387650	0	0
T8	658554	579413	0	0
T12	18200	7642	0	0
T13	13572	3146	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179103496	154209553	0	0
T1	375154	348398	0	0
T2	126256	106372	0	0
T3	370292	337947	0	0
T4	143936	18566	0	0
T5	114920	520	0	0
T6	417040	300929	0	0
T7	412490	387782	0	0
T8	658554	579708	0	0
T12	18200	7668	0	0
T13	13572	3172	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179103496	9645	0	0
T1	28858	0	0	0
T2	29136	14	0	0
T3	128178	11	0	0
T4	49824	2	0	0
T5	26520	0	0	0
T6	144360	4	0	0
T7	142785	4	0	0
T8	227961	1	0	0
T10	0	1	0	0
T12	4900	1	0	0
T13	4698	0	0	0
T18	2067	0	0	0
T19	96534	2	0	0
T20	95599	0	0	0
T35	665	0	0	0
T38	1986	0	0	0
T42	8434	29	0	0
T43	0	31	0	0
T44	15075	0	0	0
T45	0	2	0	0
T46	0	12	0	0
T47	780	0	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	9736	0	0	0
T56	0	33	0	0
T75	0	1	0	0
T88	0	1	0	0
T89	423	0	0	0
T90	427	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179103496	9092	0	0
T1	28858	0	0	0
T2	29136	14	0	0
T3	128178	11	0	0
T4	49824	1	0	0
T5	26520	0	0	0
T6	144360	3	0	0
T7	142785	4	0	0
T8	227961	1	0	0
T10	0	1	0	0
T12	4900	1	0	0
T13	4698	0	0	0
T18	2067	0	0	0
T19	96534	1	0	0
T20	95599	0	0	0
T35	665	0	0	0
T38	1986	0	0	0
T42	8434	29	0	0
T43	0	31	0	0
T44	15075	0	0	0
T45	0	2	0	0
T46	0	10	0	0
T47	780	0	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	9736	0	0	0
T56	0	33	0	0
T75	0	1	0	0
T88	0	1	0	0
T89	423	0	0	0
T90	427	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179103496	6321	0	0
T1	28858	0	0	0
T2	14568	0	0	0
T3	113936	11	0	0
T4	44288	1	0	0
T5	13260	0	0	0
T6	144360	3	0	0
T7	142785	4	0	0
T8	227961	1	0	0
T9	1274	0	0	0
T10	0	1	0	0
T12	2100	0	0	0
T13	4176	0	0	0
T18	2067	0	0	0
T19	193068	1	0	0
T20	95599	9	0	0
T38	1986	0	0	0
T42	0	29	0	0
T43	0	31	0	0
T44	30150	0	0	0
T45	0	2	0	0
T46	0	10	0	0
T47	780	0	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	29208	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T56	0	33	0	0
T72	0	28	0	0
T88	0	1	0	0
T89	423	0	0	0
T108	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179103496	6321	0	0
T1	28858	0	0	0
T2	14568	0	0	0
T3	113936	11	0	0
T4	44288	1	0	0
T5	13260	0	0	0
T6	144360	3	0	0
T7	142785	4	0	0
T8	227961	1	0	0
T9	1274	0	0	0
T10	0	1	0	0
T12	2100	0	0	0
T13	4176	0	0	0
T18	2067	0	0	0
T19	193068	1	0	0
T20	95599	9	0	0
T38	1986	0	0	0
T42	0	29	0	0
T43	0	31	0	0
T44	30150	0	0	0
T45	0	2	0	0
T46	0	10	0	0
T47	780	0	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	29208	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T56	0	33	0	0
T72	0	28	0	0
T88	0	1	0	0
T89	423	0	0	0
T108	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	179103496	1378918	0	0
T1	28858	0	0	0
T2	14568	0	0	0
T3	113936	424	0	0
T4	44288	2	0	0
T5	13260	0	0	0
T6	144360	17	0	0
T7	142785	178	0	0
T8	227961	56	0	0
T9	1274	0	0	0
T10	0	3	0	0
T12	2100	0	0	0
T13	4176	0	0	0
T18	2067	0	0	0
T19	193068	0	0	0
T20	95599	798	0	0
T38	1986	0	0	0
T42	0	4191	0	0
T43	0	1268	0	0
T44	30150	0	0	0
T45	0	6	0	0
T46	0	36	0	0
T47	780	0	0	0
T48	0	9	0	0
T49	0	9	0	0
T50	0	9	0	0
T51	0	5	0	0
T52	0	3	0	0
T53	29208	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T56	0	1994	0	0
T72	0	7217	0	0
T78	0	12	0	0
T88	0	1	0	0
T89	423	0	0	0
T108	0	6	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61997364	50835	0	0
T1	101003	80	0	0
T2	33992	207	0	0
T3	99694	209	0	0
T4	49824	231	0	0
T5	30940	0	0	0
T6	144360	206	0	0
T7	142785	74	0	0
T8	227961	140	0	0
T9	2548	0	0	0
T12	4900	9	0	0
T13	4698	42	0	0
T17	0	8	0	0
T18	0	14	0	0
T19	64356	0	0	0
T20	27314	192	0	0
T44	10050	97	0	0
T53	9736	38	0	0
T54	0	1	0	0
T55	0	2	0	0
T109	0	3	0	0
T110	0	4	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34442980	31295920	0	0
T1	72145	70025	0	0
T2	24280	22280	0	0
T3	71210	69100	0	0
T4	27680	3990	0	0
T5	22100	100	0	0
T6	80200	58095	0	0
T7	79325	77145	0	0
T8	126645	114460	0	0
T12	3500	1500	0	0
T13	2610	610	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117106132	106406128	0	0
T1	245293	238085	0	0
T2	82552	75752	0	0
T3	242114	234940	0	0
T4	94112	13566	0	0
T5	75140	340	0	0
T6	272680	197523	0	0
T7	269705	262293	0	0
T8	430593	389164	0	0
T12	11900	5100	0	0
T13	8874	2074	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61997364	56332656	0	0
T1	129861	126045	0	0
T2	43704	40104	0	0
T3	128178	124380	0	0
T4	49824	7182	0	0
T5	39780	180	0	0
T6	144360	104571	0	0
T7	142785	138861	0	0
T8	227961	206028	0	0
T12	6300	2700	0	0
T13	4698	1098	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158437708	5205	0	0
T1	28858	0	0	0
T2	14568	0	0	0
T3	99694	9	0	0
T4	44288	1	0	0
T5	13260	0	0	0
T6	144360	3	0	0
T7	142785	4	0	0
T8	227961	1	0	0
T9	2548	0	0	0
T10	0	1	0	0
T12	2100	0	0	0
T13	4176	0	0	0
T19	193068	1	0	0
T20	95599	0	0	0
T24	0	1	0	0
T35	665	0	0	0
T42	8434	28	0	0
T43	0	30	0	0
T44	30150	0	0	0
T45	0	2	0	0
T46	0	10	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	29208	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T56	0	29	0	0
T66	543	0	0	0
T88	0	1	0	0
T90	427	0	0	0
T108	0	3	0	0
T111	0	1	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20665788	902275	0	0
T6	48120	237	0	0
T7	47595	0	0	0
T8	75987	0	0	0
T9	3822	1020	0	0
T11	0	453	0	0
T19	96534	0	0	0
T20	40971	0	0	0
T36	0	229	0	0
T44	15075	0	0	0
T49	0	694	0	0
T53	14604	0	0	0
T54	1278	0	0	0
T55	155946	0	0	0
T57	0	558	0	0
T58	0	395	0	0
T59	0	228	0	0
T60	0	100	0	0
T61	0	25	0	0
T74	0	289	0	0
T85	0	205	0	0
T86	0	203870	0	0
T99	0	338	0	0
T112	0	167	0	0
T113	0	604	0	0
T114	0	83	0	0