Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T8,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T4,T8,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T8,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T18
1	0	Covered	T1,T2,T5
1	1	Covered	T4,T8,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T38
0	1	Covered	T130
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T38,T32
0	1	Covered	T4,T8,T40
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T38,T32
1	-	Covered	T4,T8,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T8,T38
DetectSt	168	Covered	T4,T8,T38
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T4,T8,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T8,T38
DebounceSt->IdleSt	163	Covered	T76
DetectSt->IdleSt	186	Covered	T130
DetectSt->StableSt	191	Covered	T4,T8,T38
IdleSt->DebounceSt	148	Covered	T4,T8,T38
StableSt->IdleSt	206	Covered	T4,T8,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T8,T38
0	1	Covered	T4,T8,T38
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T38
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T8,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T8,T38
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T8,T38
DetectSt	-	-	-	-	1	-	-	Covered	T130
DetectSt	-	-	-	-	0	1	-	Covered	T4,T8,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T8,T40
StableSt	-	-	-	-	-	-	0	Covered	T4,T38,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	77	0	0
CntIncr_A	6888596	49382	0	0
CntNoWrap_A	6888596	6256831	0	0
DetectStDropOut_A	6888596	1	0	0
DetectedOut_A	6888596	2358	0	0
DetectedPulseOut_A	6888596	37	0	0
DisabledIdleSt_A	6888596	6053394	0	0
DisabledNoDetection_A	6888596	6055622	0	0
EnterDebounceSt_A	6888596	39	0	0
EnterDetectSt_A	6888596	38	0	0
EnterStableSt_A	6888596	37	0	0
PulseIsPulse_A	6888596	37	0	0
StayInStableSt	6888596	2302	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	77	0	0
T4	5536	2	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	4	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	4	0	0
T142	0	2	0	0
T150	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	49382	0	0
T4	5536	36	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	10	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	41	0	0
T32	0	68	0	0
T37	0	77	0	0
T38	0	67	0	0
T40	0	160	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	142	0	0
T142	0	12	0	0
T150	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256831	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	784	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22877	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1	0	0
T130	954	1	0	0
T131	495	0	0	0
T132	3125	0	0	0
T178	427	0	0	0
T179	423	0	0	0
T180	5016	0	0	0
T181	404	0	0	0
T182	838	0	0	0
T183	2199	0	0	0
T184	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	2358	0	0
T4	5536	18	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	2	0	0
T32	0	467	0	0
T37	0	43	0	0
T38	0	58	0	0
T40	0	79	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	55	0	0
T142	0	109	0	0
T150	0	160	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	37	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	2	0	0
T142	0	1	0	0
T150	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6053394	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	529	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22748	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6055622	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	540	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22760	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	39	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	2	0	0
T142	0	1	0	0
T150	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	38	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	2	0	0
T142	0	1	0	0
T150	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	37	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	2	0	0
T142	0	1	0	0
T150	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	37	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	2	0	0
T142	0	1	0	0
T150	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	2302	0	0
T4	5536	17	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	465	0	0
T37	0	42	0	0
T38	0	56	0	0
T40	0	76	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	52	0	0
T142	0	107	0	0
T150	0	157	0	0
T185	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	17	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T130	0	1	0	0
T138	0	1	0	0
T150	0	1	0	0
T155	0	2	0	0
T186	0	1	0	0
T187	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T8,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T4,T8,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T8,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T18
1	0	Covered	T1,T5,T3
1	1	Covered	T4,T8,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T38
0	1	Covered	T188
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T38
0	1	Covered	T4,T8,T38
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T8,T38
1	-	Covered	T4,T8,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T8,T38
DetectSt	168	Covered	T4,T8,T38
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T4,T8,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T8,T38
DebounceSt->IdleSt	163	Covered	T36,T138,T76
DetectSt->IdleSt	186	Covered	T188
DetectSt->StableSt	191	Covered	T4,T8,T38
IdleSt->DebounceSt	148	Covered	T4,T8,T38
StableSt->IdleSt	206	Covered	T4,T8,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T8,T38
0	1	Covered	T4,T8,T38
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T38
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T8,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T8,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T138,T187,T189
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T8,T38
DetectSt	-	-	-	-	1	-	-	Covered	T188
DetectSt	-	-	-	-	0	1	-	Covered	T4,T8,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T8,T38
StableSt	-	-	-	-	-	-	0	Covered	T4,T8,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	135	0	0
CntIncr_A	6888596	51321	0	0
CntNoWrap_A	6888596	6256773	0	0
DetectStDropOut_A	6888596	1	0	0
DetectedOut_A	6888596	97725	0	0
DetectedPulseOut_A	6888596	63	0	0
DisabledIdleSt_A	6888596	6051789	0	0
DisabledNoDetection_A	6888596	6054013	0	0
EnterDebounceSt_A	6888596	72	0	0
EnterDetectSt_A	6888596	64	0	0
EnterStableSt_A	6888596	63	0	0
PulseIsPulse_A	6888596	63	0	0
StayInStableSt	6888596	97637	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6888596	2861	0	0
gen_low_level_sva.LowLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	135	0	0
T4	5536	4	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	4	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	2	0	0
T33	0	4	0	0
T35	0	2	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	2	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	51321	0	0
T4	5536	72	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	20	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T33	0	128	0	0
T35	0	21	0	0
T36	0	6	0	0
T37	0	154	0	0
T38	0	67	0	0
T41	0	56	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	21	0	0
T168	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256773	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	782	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22875	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1	0	0
T164	33784	0	0	0
T188	845	1	0	0
T190	12190	0	0	0
T191	415	0	0	0
T192	763	0	0	0
T193	858	0	0	0
T194	527	0	0	0
T195	432	0	0	0
T196	193669	0	0	0
T197	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	97725	0	0
T4	5536	79	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	81	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	3	0	0
T33	0	149	0	0
T35	0	212	0	0
T37	0	221	0	0
T38	0	58	0	0
T41	0	52	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	81	0	0
T168	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	63	0	0
T4	5536	2	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	1	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6051789	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	529	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22748	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6054013	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	540	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22760	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	72	0	0
T4	5536	2	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	1	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	64	0	0
T4	5536	2	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	1	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	63	0	0
T4	5536	2	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	1	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	63	0	0
T4	5536	2	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	1	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	97637	0	0
T4	5536	76	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	78	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	2	0	0
T33	0	146	0	0
T35	0	210	0	0
T37	0	218	0	0
T38	0	57	0	0
T41	0	50	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	79	0	0
T168	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	2861	0	0
T4	5536	19	0	0
T6	16040	22	0	0
T7	15865	0	0	0
T8	25329	17	0	0
T9	1274	0	0	0
T13	522	5	0	0
T17	0	4	0	0
T18	0	10	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T53	4868	22	0	0
T55	0	2	0	0
T109	0	1	0	0
T110	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	37	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	1	0	0
T142	0	1	0	0
T168	0	1	0	0
T198	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T38,T29,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T38,T29,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T38,T29,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T38,T29,T34
1	0	Covered	T1,T2,T3
1	1	Covered	T38,T29,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T29,T34
0	1	Covered	T142
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T29,T34
0	1	Covered	T38,T29,T34
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T29,T34
1	-	Covered	T38,T29,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T38,T29,T34
DetectSt	168	Covered	T38,T29,T34
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T38,T29,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T29,T34
DebounceSt->IdleSt	163	Covered	T34,T99,T140
DetectSt->IdleSt	186	Covered	T142
DetectSt->StableSt	191	Covered	T38,T29,T34
IdleSt->DebounceSt	148	Covered	T38,T29,T34
StableSt->IdleSt	206	Covered	T38,T29,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T38,T29,T34
0	1	Covered	T38,T29,T34
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T29,T34
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T38,T29,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T29,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T99,T140
DebounceSt	-	0	0	-	-	-	-	Covered	T38,T29,T34
DetectSt	-	-	-	-	1	-	-	Covered	T142
DetectSt	-	-	-	-	0	1	-	Covered	T38,T29,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T29,T34
StableSt	-	-	-	-	-	-	0	Covered	T38,T29,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	114	0	0
CntIncr_A	6888596	68966	0	0
CntNoWrap_A	6888596	6256794	0	0
DetectStDropOut_A	6888596	1	0	0
DetectedOut_A	6888596	43714	0	0
DetectedPulseOut_A	6888596	53	0	0
DisabledIdleSt_A	6888596	6104058	0	0
DisabledNoDetection_A	6888596	6106286	0	0
EnterDebounceSt_A	6888596	60	0	0
EnterDetectSt_A	6888596	54	0	0
EnterStableSt_A	6888596	53	0	0
PulseIsPulse_A	6888596	53	0	0
StayInStableSt	6888596	43635	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	114	0	0
T29	0	4	0	0
T30	0	2	0	0
T32	0	6	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	665	0	0	0
T38	1986	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T104	919	0	0	0
T142	0	2	0	0
T143	423	0	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	68966	0	0
T29	0	52	0	0
T30	0	41	0	0
T32	0	204	0	0
T33	0	64	0	0
T34	0	164	0	0
T35	665	0	0	0
T38	1986	67	0	0
T39	0	60	0	0
T41	0	56	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T104	919	0	0	0
T142	0	12	0	0
T143	423	0	0	0
T168	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256794	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1	0	0
T86	612775	0	0	0
T113	1841	0	0	0
T142	551	1	0	0
T145	99362	0	0	0
T146	5297	0	0	0
T147	697	0	0	0
T148	488	0	0	0
T149	510	0	0	0
T150	741	0	0	0
T199	532	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	43714	0	0
T29	0	169	0	0
T30	0	2	0	0
T32	0	245	0	0
T33	0	242	0	0
T34	0	74	0	0
T35	665	0	0	0
T38	1986	58	0	0
T39	0	23	0	0
T41	0	117	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T104	919	0	0	0
T143	423	0	0	0
T148	0	53	0	0
T168	0	62	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	53	0	0
T29	0	2	0	0
T30	0	1	0	0
T32	0	3	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	665	0	0	0
T38	1986	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T104	919	0	0	0
T143	423	0	0	0
T148	0	1	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6104058	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6106286	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	60	0	0
T29	0	2	0	0
T30	0	1	0	0
T32	0	3	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	665	0	0	0
T38	1986	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T104	919	0	0	0
T142	0	1	0	0
T143	423	0	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	54	0	0
T29	0	2	0	0
T30	0	1	0	0
T32	0	3	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	665	0	0	0
T38	1986	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T104	919	0	0	0
T142	0	1	0	0
T143	423	0	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	53	0	0
T29	0	2	0	0
T30	0	1	0	0
T32	0	3	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	665	0	0	0
T38	1986	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T104	919	0	0	0
T143	423	0	0	0
T148	0	1	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	53	0	0
T29	0	2	0	0
T30	0	1	0	0
T32	0	3	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	665	0	0	0
T38	1986	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T104	919	0	0	0
T143	423	0	0	0
T148	0	1	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	43635	0	0
T29	0	167	0	0
T30	0	1	0	0
T32	0	241	0	0
T33	0	240	0	0
T34	0	73	0	0
T35	665	0	0	0
T38	1986	57	0	0
T39	0	22	0	0
T41	0	115	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T104	919	0	0	0
T143	423	0	0	0
T148	0	51	0	0
T168	0	60	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	26	0	0
T29	0	2	0	0
T32	0	2	0	0
T34	0	1	0	0
T35	665	0	0	0
T38	1986	1	0	0
T39	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T104	919	0	0	0
T140	0	1	0	0
T143	423	0	0	0
T154	0	3	0	0
T200	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T38,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T38,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T38,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T38,T168,T41
1	0	Covered	T1,T2,T5
1	1	Covered	T38,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T40
0	1	Covered	T130,T203
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T40
0	1	Covered	T40,T185,T200
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T39,T40
1	-	Covered	T40,T185,T200

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T38,T39,T40
DetectSt	168	Covered	T38,T39,T40
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T38,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T39,T40
DebounceSt->IdleSt	163	Covered	T87,T76,T141
DetectSt->IdleSt	186	Covered	T130,T203
DetectSt->StableSt	191	Covered	T38,T39,T40
IdleSt->DebounceSt	148	Covered	T38,T39,T40
StableSt->IdleSt	206	Covered	T39,T40,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T38,T39,T40
0	1	Covered	T38,T39,T40
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T38,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T87,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T38,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T130,T203
DetectSt	-	-	-	-	0	1	-	Covered	T38,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T30,T185
StableSt	-	-	-	-	-	-	0	Covered	T38,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	75	0	0
CntIncr_A	6888596	38575	0	0
CntNoWrap_A	6888596	6256833	0	0
DetectStDropOut_A	6888596	2	0	0
DetectedOut_A	6888596	2940	0	0
DetectedPulseOut_A	6888596	34	0	0
DisabledIdleSt_A	6888596	6093746	0	0
DisabledNoDetection_A	6888596	6095970	0	0
EnterDebounceSt_A	6888596	39	0	0
EnterDetectSt_A	6888596	36	0	0
EnterStableSt_A	6888596	34	0	0
PulseIsPulse_A	6888596	34	0	0
StayInStableSt	6888596	2883	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6888596	6509	0	0
gen_low_level_sva.LowLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	75	0	0
T30	0	2	0	0
T35	665	0	0	0
T37	0	2	0	0
T38	1986	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	1	0	0
T90	427	0	0	0
T104	919	0	0	0
T138	0	4	0	0
T142	0	2	0	0
T143	423	0	0	0
T185	0	4	0	0
T200	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	38575	0	0
T30	0	41	0	0
T35	665	0	0	0
T37	0	77	0	0
T38	1986	67	0	0
T39	0	60	0	0
T40	0	80	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	95	0	0
T90	427	0	0	0
T104	919	0	0	0
T138	0	119	0	0
T142	0	12	0	0
T143	423	0	0	0
T185	0	110	0	0
T200	0	36	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256833	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	2	0	0
T130	954	1	0	0
T131	495	0	0	0
T132	3125	0	0	0
T178	427	0	0	0
T179	423	0	0	0
T180	5016	0	0	0
T181	404	0	0	0
T182	838	0	0	0
T183	2199	0	0	0
T184	524	0	0	0
T203	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	2940	0	0
T30	0	2	0	0
T35	665	0	0	0
T37	0	38	0	0
T38	1986	58	0	0
T39	0	47	0	0
T40	0	39	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T99	0	515	0	0
T104	919	0	0	0
T138	0	343	0	0
T142	0	43	0	0
T143	423	0	0	0
T185	0	78	0	0
T200	0	203	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	34	0	0
T30	0	1	0	0
T35	665	0	0	0
T37	0	1	0	0
T38	1986	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T99	0	3	0	0
T104	919	0	0	0
T138	0	2	0	0
T142	0	1	0	0
T143	423	0	0	0
T185	0	2	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6093746	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6095970	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	39	0	0
T30	0	1	0	0
T35	665	0	0	0
T37	0	1	0	0
T38	1986	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	1	0	0
T90	427	0	0	0
T104	919	0	0	0
T138	0	2	0	0
T142	0	1	0	0
T143	423	0	0	0
T185	0	2	0	0
T200	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	36	0	0
T30	0	1	0	0
T35	665	0	0	0
T37	0	1	0	0
T38	1986	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T99	0	3	0	0
T104	919	0	0	0
T138	0	2	0	0
T142	0	1	0	0
T143	423	0	0	0
T185	0	2	0	0
T200	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	34	0	0
T30	0	1	0	0
T35	665	0	0	0
T37	0	1	0	0
T38	1986	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T99	0	3	0	0
T104	919	0	0	0
T138	0	2	0	0
T142	0	1	0	0
T143	423	0	0	0
T185	0	2	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	34	0	0
T30	0	1	0	0
T35	665	0	0	0
T37	0	1	0	0
T38	1986	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T99	0	3	0	0
T104	919	0	0	0
T138	0	2	0	0
T142	0	1	0	0
T143	423	0	0	0
T185	0	2	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	2883	0	0
T30	0	1	0	0
T35	665	0	0	0
T37	0	36	0	0
T38	1986	56	0	0
T39	0	45	0	0
T40	0	38	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T99	0	510	0	0
T104	919	0	0	0
T138	0	339	0	0
T142	0	41	0	0
T143	423	0	0	0
T185	0	75	0	0
T200	0	202	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6509	0	0
T1	14429	13	0	0
T2	4856	28	0	0
T3	14242	26	0	0
T4	5536	22	0	0
T5	4420	0	0	0
T6	16040	23	0	0
T7	15865	13	0	0
T8	25329	16	0	0
T12	700	0	0	0
T13	522	5	0	0
T20	0	27	0	0
T44	0	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	10	0	0
T30	8245	0	0	0
T36	9267	0	0	0
T37	10761	0	0	0
T40	853	1	0	0
T99	0	1	0	0
T154	0	1	0	0
T159	721	0	0	0
T160	750	0	0	0
T161	24956	0	0	0
T185	0	1	0	0
T200	0	1	0	0
T202	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	527	0	0	0
T209	704	0	0	0
T210	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T35,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T4,T35,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T35,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T35,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T35,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T35,T32
0	1	Covered	T35,T33,T40
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T35,T32
0	1	Covered	T35,T32,T40
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T35,T32
1	-	Covered	T35,T32,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T35,T32
DetectSt	168	Covered	T4,T35,T32
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T4,T35,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T35,T32
DebounceSt->IdleSt	163	Covered	T36,T76,T202
DetectSt->IdleSt	186	Covered	T35,T33,T40
DetectSt->StableSt	191	Covered	T4,T35,T32
IdleSt->DebounceSt	148	Covered	T4,T35,T32
StableSt->IdleSt	206	Covered	T4,T35,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T35,T32
0	1	Covered	T4,T35,T32
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T35,T32
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T35,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T35,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T202,T211
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T35,T32
DetectSt	-	-	-	-	1	-	-	Covered	T35,T33,T40
DetectSt	-	-	-	-	0	1	-	Covered	T4,T35,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T32,T40
StableSt	-	-	-	-	-	-	0	Covered	T4,T35,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	115	0	0
CntIncr_A	6888596	3035	0	0
CntNoWrap_A	6888596	6256793	0	0
DetectStDropOut_A	6888596	4	0	0
DetectedOut_A	6888596	4611	0	0
DetectedPulseOut_A	6888596	51	0	0
DisabledIdleSt_A	6888596	6241170	0	0
DisabledNoDetection_A	6888596	6243402	0	0
EnterDebounceSt_A	6888596	60	0	0
EnterDetectSt_A	6888596	55	0	0
EnterStableSt_A	6888596	51	0	0
PulseIsPulse_A	6888596	51	0	0
StayInStableSt	6888596	4540	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	115	0	0
T4	5536	2	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	2	0	0
T32	0	4	0	0
T33	0	4	0	0
T35	0	6	0	0
T36	0	1	0	0
T40	0	4	0	0
T41	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	2	0	0
T142	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	3035	0	0
T4	5536	36	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	41	0	0
T32	0	136	0	0
T33	0	128	0	0
T35	0	63	0	0
T36	0	82	0	0
T40	0	160	0	0
T41	0	56	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	93	0	0
T142	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256793	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	784	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	4	0	0
T33	0	1	0	0
T35	665	1	0	0
T40	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T104	919	0	0	0
T143	423	0	0	0
T212	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	4611	0	0
T4	5536	216	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	192	0	0
T33	0	44	0	0
T35	0	88	0	0
T40	0	42	0	0
T41	0	116	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	676	0	0
T142	0	7	0	0
T151	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	51	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	1	0	0
T142	0	1	0	0
T151	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6241170	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	529	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6243402	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	540	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	60	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	2	0	0
T35	0	3	0	0
T36	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	1	0	0
T142	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	55	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	2	0	0
T35	0	3	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	1	0	0
T142	0	1	0	0
T151	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	51	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	1	0	0
T142	0	1	0	0
T151	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	51	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	1	0	0
T142	0	1	0	0
T151	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	4540	0	0
T4	5536	214	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T32	0	190	0	0
T33	0	42	0	0
T35	0	85	0	0
T40	0	41	0	0
T41	0	114	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T99	0	224	0	0
T138	0	674	0	0
T142	0	6	0	0
T151	0	78	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	30	0	0
T32	0	2	0	0
T35	665	1	0	0
T40	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T90	427	0	0	0
T99	0	4	0	0
T104	919	0	0	0
T130	0	1	0	0
T139	0	1	0	0
T142	0	1	0	0
T143	423	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T35,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T35,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T35,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T38
1	0	Covered	T1,T2,T5
1	1	Covered	T35,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Covered	T150
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Covered	T35,T37,T87
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T36,T37
1	-	Covered	T35,T37,T87

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T36,T37
DetectSt	168	Covered	T35,T36,T37
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T35,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T36,T37
DebounceSt->IdleSt	163	Covered	T76,T152,T188
DetectSt->IdleSt	186	Covered	T150
DetectSt->StableSt	191	Covered	T35,T36,T37
IdleSt->DebounceSt	148	Covered	T35,T36,T37
StableSt->IdleSt	206	Covered	T35,T36,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T35,T36,T37
0	1	Covered	T35,T36,T37
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T37
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T188
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	1	-	-	Covered	T150
DetectSt	-	-	-	-	0	1	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T37,T30
StableSt	-	-	-	-	-	-	0	Covered	T35,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	80	0	0
CntIncr_A	6888596	2092	0	0
CntNoWrap_A	6888596	6256828	0	0
DetectStDropOut_A	6888596	1	0	0
DetectedOut_A	6888596	3585	0	0
DetectedPulseOut_A	6888596	38	0	0
DisabledIdleSt_A	6888596	6185349	0	0
DisabledNoDetection_A	6888596	6187573	0	0
EnterDebounceSt_A	6888596	42	0	0
EnterDetectSt_A	6888596	39	0	0
EnterStableSt_A	6888596	38	0	0
PulseIsPulse_A	6888596	38	0	0
StayInStableSt	6888596	3532	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6888596	6126	0	0
gen_low_level_sva.LowLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	80	0	0
T30	0	2	0	0
T35	665	4	0	0
T36	0	2	0	0
T37	0	2	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T76	0	1	0	0
T87	0	2	0	0
T90	427	0	0	0
T99	0	4	0	0
T104	919	0	0	0
T138	0	6	0	0
T143	423	0	0	0
T150	0	4	0	0
T200	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	2092	0	0
T30	0	41	0	0
T35	665	42	0	0
T36	0	82	0	0
T37	0	77	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T76	0	36	0	0
T87	0	95	0	0
T90	427	0	0	0
T99	0	134	0	0
T104	919	0	0	0
T138	0	190	0	0
T143	423	0	0	0
T150	0	60	0	0
T200	0	36	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256828	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1	0	0
T86	612775	0	0	0
T150	741	1	0	0
T185	694	0	0	0
T198	477	0	0	0
T199	532	0	0	0
T213	6292	0	0	0
T214	5943	0	0	0
T215	7432	0	0	0
T216	2779	0	0	0
T217	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	3585	0	0
T30	0	2	0	0
T35	665	59	0	0
T36	0	40	0	0
T37	0	42	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	97	0	0
T90	427	0	0	0
T99	0	198	0	0
T104	919	0	0	0
T138	0	130	0	0
T143	423	0	0	0
T150	0	86	0	0
T200	0	138	0	0
T218	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	38	0	0
T30	0	1	0	0
T35	665	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	1	0	0
T90	427	0	0	0
T99	0	2	0	0
T104	919	0	0	0
T138	0	3	0	0
T143	423	0	0	0
T150	0	1	0	0
T200	0	1	0	0
T218	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6185349	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	529	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6187573	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	540	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	42	0	0
T30	0	1	0	0
T35	665	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T76	0	1	0	0
T87	0	1	0	0
T90	427	0	0	0
T99	0	2	0	0
T104	919	0	0	0
T138	0	3	0	0
T143	423	0	0	0
T150	0	2	0	0
T200	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	39	0	0
T30	0	1	0	0
T35	665	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	1	0	0
T90	427	0	0	0
T99	0	2	0	0
T104	919	0	0	0
T138	0	3	0	0
T143	423	0	0	0
T150	0	2	0	0
T200	0	1	0	0
T218	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	38	0	0
T30	0	1	0	0
T35	665	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	1	0	0
T90	427	0	0	0
T99	0	2	0	0
T104	919	0	0	0
T138	0	3	0	0
T143	423	0	0	0
T150	0	1	0	0
T200	0	1	0	0
T218	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	38	0	0
T30	0	1	0	0
T35	665	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	1	0	0
T90	427	0	0	0
T99	0	2	0	0
T104	919	0	0	0
T138	0	3	0	0
T143	423	0	0	0
T150	0	1	0	0
T200	0	1	0	0
T218	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	3532	0	0
T30	0	1	0	0
T35	665	57	0	0
T36	0	38	0	0
T37	0	41	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	96	0	0
T90	427	0	0	0
T99	0	195	0	0
T104	919	0	0	0
T138	0	126	0	0
T143	423	0	0	0
T150	0	85	0	0
T200	0	136	0	0
T218	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6126	0	0
T1	14429	6	0	0
T2	4856	29	0	0
T3	14242	27	0	0
T4	5536	24	0	0
T5	4420	0	0	0
T6	16040	22	0	0
T7	15865	12	0	0
T8	25329	17	0	0
T12	700	0	0	0
T13	522	4	0	0
T20	0	32	0	0
T44	0	24	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	22	0	0
T35	665	2	0	0
T37	0	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T48	669	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T75	10187	0	0	0
T87	0	1	0	0
T90	427	0	0	0
T99	0	1	0	0
T104	919	0	0	0
T138	0	2	0	0
T139	0	1	0	0
T143	423	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T155	0	1	0	0
T219	0	1	0	0