Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T18,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T4,T18,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T18,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T38
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T18,T38
0	1	Covered	T138
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T18,T38
0	1	Covered	T38,T29,T34
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T18,T38
1	-	Covered	T38,T29,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T18,T38
DetectSt	168	Covered	T4,T18,T38
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T4,T18,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T18,T38
DebounceSt->IdleSt	163	Covered	T36,T185,T76
DetectSt->IdleSt	186	Covered	T138
DetectSt->StableSt	191	Covered	T4,T18,T38
IdleSt->DebounceSt	148	Covered	T4,T18,T38
StableSt->IdleSt	206	Covered	T4,T18,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T18,T38
0	1	Covered	T4,T18,T38
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T38
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T18,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T18,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T185,T157
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T18,T38
DetectSt	-	-	-	-	1	-	-	Covered	T138
DetectSt	-	-	-	-	0	1	-	Covered	T4,T18,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T29,T34
StableSt	-	-	-	-	-	-	0	Covered	T4,T18,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	132	0	0
CntIncr_A	6888596	164606	0	0
CntNoWrap_A	6888596	6256776	0	0
DetectStDropOut_A	6888596	1	0	0
DetectedOut_A	6888596	48770	0	0
DetectedPulseOut_A	6888596	63	0	0
DisabledIdleSt_A	6888596	5912844	0	0
DisabledNoDetection_A	6888596	5915069	0	0
EnterDebounceSt_A	6888596	69	0	0
EnterDetectSt_A	6888596	64	0	0
EnterStableSt_A	6888596	63	0	0
PulseIsPulse_A	6888596	63	0	0
StayInStableSt	6888596	48682	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	132	0	0
T4	5536	2	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T18	0	2	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	4	0	0
T30	0	2	0	0
T33	0	2	0	0
T34	0	4	0	0
T36	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	164606	0	0
T4	5536	36	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T18	0	41	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	52	0	0
T30	0	41	0	0
T33	0	64	0	0
T34	0	164	0	0
T36	0	82	0	0
T38	0	67	0	0
T39	0	60	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	42	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256776	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	784	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1	0	0
T113	1841	0	0	0
T138	23403	1	0	0
T142	551	0	0	0
T144	553	0	0	0
T145	99362	0	0	0
T146	5297	0	0	0
T147	697	0	0	0
T148	488	0	0	0
T149	510	0	0	0
T150	741	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	48770	0	0
T4	5536	39	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T18	0	39	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	213	0	0
T30	0	2	0	0
T33	0	242	0	0
T34	0	113	0	0
T38	0	57	0	0
T39	0	132	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	103	0	0
T138	0	428	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	63	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T18	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	2	0	0
T138	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5912844	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	529	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5915069	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	540	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	69	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T18	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	64	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T18	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	2	0	0
T138	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	63	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T18	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	2	0	0
T138	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	63	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T18	0	1	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	2	0	0
T138	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	48682	0	0
T4	5536	37	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T18	0	37	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	210	0	0
T30	0	1	0	0
T33	0	240	0	0
T34	0	110	0	0
T38	0	56	0	0
T39	0	130	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	100	0	0
T138	0	419	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	37	0	0
T29	0	1	0	0
T34	0	1	0	0
T35	665	0	0	0
T38	1986	1	0	0
T42	8434	0	0	0
T43	15341	0	0	0
T56	14872	0	0	0
T66	543	0	0	0
T70	0	1	0	0
T75	10187	0	0	0
T90	427	0	0	0
T104	919	0	0	0
T138	0	3	0	0
T140	0	1	0	0
T142	0	1	0	0
T143	423	0	0	0
T198	0	1	0	0
T200	0	1	0	0
T218	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T29,T34,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T29,T34,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T29,T34,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T35,T29
1	0	Covered	T1,T2,T5
1	1	Covered	T29,T34,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T34,T32
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T34,T32
0	1	Covered	T29,T34,T32
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T34,T32
1	-	Covered	T29,T34,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T29,T34,T32
DetectSt	168	Covered	T29,T34,T32
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T29,T34,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T29,T34,T32
DebounceSt->IdleSt	163	Covered	T76,T154,T139
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T29,T34,T32
IdleSt->DebounceSt	148	Covered	T29,T34,T32
StableSt->IdleSt	206	Covered	T29,T34,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T29,T34,T32
0	1	Covered	T29,T34,T32
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T29,T34,T32
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T34,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T29,T34,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T154,T139,T166
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T34,T32
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T29,T34,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T34,T32
StableSt	-	-	-	-	-	-	0	Covered	T29,T34,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	82	0	0
CntIncr_A	6888596	49590	0	0
CntNoWrap_A	6888596	6256826	0	0
DetectStDropOut_A	6888596	0	0	0
DetectedOut_A	6888596	45250	0	0
DetectedPulseOut_A	6888596	39	0	0
DisabledIdleSt_A	6888596	6005917	0	0
DisabledNoDetection_A	6888596	6008142	0	0
EnterDebounceSt_A	6888596	43	0	0
EnterDetectSt_A	6888596	39	0	0
EnterStableSt_A	6888596	39	0	0
PulseIsPulse_A	6888596	39	0	0
StayInStableSt	6888596	45192	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6888596	6163	0	0
gen_low_level_sva.LowLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	82	0	0
T29	747	2	0	0
T30	0	2	0	0
T32	0	2	0	0
T34	0	2	0	0
T36	0	2	0	0
T40	0	4	0	0
T58	992	0	0	0
T70	0	2	0	0
T72	38954	0	0	0
T87	0	2	0	0
T142	0	2	0	0
T150	0	2	0	0
T220	427	0	0	0
T221	523	0	0	0
T222	426	0	0	0
T223	522	0	0	0
T224	402	0	0	0
T225	411	0	0	0
T226	428	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	49590	0	0
T29	747	26	0	0
T30	0	41	0	0
T32	0	68	0	0
T34	0	82	0	0
T36	0	67	0	0
T40	0	160	0	0
T58	992	0	0	0
T70	0	21	0	0
T72	38954	0	0	0
T87	0	95	0	0
T142	0	12	0	0
T150	0	30	0	0
T220	427	0	0	0
T221	523	0	0	0
T222	426	0	0	0
T223	522	0	0	0
T224	402	0	0	0
T225	411	0	0	0
T226	428	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256826	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	45250	0	0
T29	747	44	0	0
T30	0	3	0	0
T32	0	253	0	0
T34	0	79	0	0
T36	0	41	0	0
T40	0	80	0	0
T58	992	0	0	0
T70	0	18	0	0
T72	38954	0	0	0
T87	0	234	0	0
T142	0	39	0	0
T150	0	83	0	0
T220	427	0	0	0
T221	523	0	0	0
T222	426	0	0	0
T223	522	0	0	0
T224	402	0	0	0
T225	411	0	0	0
T226	428	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	39	0	0
T29	747	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T40	0	2	0	0
T58	992	0	0	0
T70	0	1	0	0
T72	38954	0	0	0
T87	0	1	0	0
T142	0	1	0	0
T150	0	1	0	0
T220	427	0	0	0
T221	523	0	0	0
T222	426	0	0	0
T223	522	0	0	0
T224	402	0	0	0
T225	411	0	0	0
T226	428	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6005917	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22748	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6008142	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22760	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	43	0	0
T29	747	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T40	0	2	0	0
T58	992	0	0	0
T70	0	1	0	0
T72	38954	0	0	0
T87	0	1	0	0
T142	0	1	0	0
T150	0	1	0	0
T220	427	0	0	0
T221	523	0	0	0
T222	426	0	0	0
T223	522	0	0	0
T224	402	0	0	0
T225	411	0	0	0
T226	428	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	39	0	0
T29	747	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T40	0	2	0	0
T58	992	0	0	0
T70	0	1	0	0
T72	38954	0	0	0
T87	0	1	0	0
T142	0	1	0	0
T150	0	1	0	0
T220	427	0	0	0
T221	523	0	0	0
T222	426	0	0	0
T223	522	0	0	0
T224	402	0	0	0
T225	411	0	0	0
T226	428	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	39	0	0
T29	747	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T40	0	2	0	0
T58	992	0	0	0
T70	0	1	0	0
T72	38954	0	0	0
T87	0	1	0	0
T142	0	1	0	0
T150	0	1	0	0
T220	427	0	0	0
T221	523	0	0	0
T222	426	0	0	0
T223	522	0	0	0
T224	402	0	0	0
T225	411	0	0	0
T226	428	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	39	0	0
T29	747	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T40	0	2	0	0
T58	992	0	0	0
T70	0	1	0	0
T72	38954	0	0	0
T87	0	1	0	0
T142	0	1	0	0
T150	0	1	0	0
T220	427	0	0	0
T221	523	0	0	0
T222	426	0	0	0
T223	522	0	0	0
T224	402	0	0	0
T225	411	0	0	0
T226	428	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	45192	0	0
T29	747	43	0	0
T30	0	2	0	0
T32	0	252	0	0
T34	0	78	0	0
T36	0	40	0	0
T40	0	77	0	0
T58	992	0	0	0
T70	0	17	0	0
T72	38954	0	0	0
T87	0	232	0	0
T142	0	38	0	0
T150	0	82	0	0
T220	427	0	0	0
T221	523	0	0	0
T222	426	0	0	0
T223	522	0	0	0
T224	402	0	0	0
T225	411	0	0	0
T226	428	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6163	0	0
T1	14429	13	0	0
T2	4856	32	0	0
T3	14242	28	0	0
T4	5536	32	0	0
T5	4420	0	0	0
T6	16040	22	0	0
T7	15865	10	0	0
T8	25329	14	0	0
T12	700	0	0	0
T13	522	5	0	0
T20	0	26	0	0
T44	0	26	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	19	0	0
T29	747	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T58	992	0	0	0
T70	0	1	0	0
T72	38954	0	0	0
T142	0	1	0	0
T150	0	1	0	0
T202	0	1	0	0
T220	427	0	0	0
T221	523	0	0	0
T222	426	0	0	0
T223	522	0	0	0
T224	402	0	0	0
T225	411	0	0	0
T226	428	0	0	0
T227	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T8,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T4,T8,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T8,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T38
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T38
0	1	Covered	T40
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T38
0	1	Covered	T4,T8,T32
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T8,T38
1	-	Covered	T4,T8,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T8,T38
DetectSt	168	Covered	T4,T8,T38
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T4,T8,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T8,T38
DebounceSt->IdleSt	163	Covered	T99,T76,T227
DetectSt->IdleSt	186	Covered	T40
DetectSt->StableSt	191	Covered	T4,T8,T38
IdleSt->DebounceSt	148	Covered	T4,T8,T38
StableSt->IdleSt	206	Covered	T4,T8,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T8,T38
0	1	Covered	T4,T8,T38
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T38
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T8,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T8,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T99,T227,T205
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T8,T38
DetectSt	-	-	-	-	1	-	-	Covered	T40
DetectSt	-	-	-	-	0	1	-	Covered	T4,T8,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T8,T32
StableSt	-	-	-	-	-	-	0	Covered	T4,T8,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	124	0	0
CntIncr_A	6888596	131497	0	0
CntNoWrap_A	6888596	6256784	0	0
DetectStDropOut_A	6888596	1	0	0
DetectedOut_A	6888596	8657	0	0
DetectedPulseOut_A	6888596	58	0	0
DisabledIdleSt_A	6888596	5912303	0	0
DisabledNoDetection_A	6888596	5914534	0	0
EnterDebounceSt_A	6888596	65	0	0
EnterDetectSt_A	6888596	59	0	0
EnterStableSt_A	6888596	58	0	0
PulseIsPulse_A	6888596	58	0	0
StayInStableSt	6888596	8578	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	124	0	0
T4	5536	2	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	4	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	2	0	0
T32	0	4	0	0
T33	0	2	0	0
T36	0	2	0	0
T38	0	2	0	0
T40	0	4	0	0
T41	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	131497	0	0
T4	5536	36	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	20	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	41	0	0
T32	0	136	0	0
T33	0	64	0	0
T36	0	67	0	0
T38	0	67	0	0
T40	0	160	0	0
T41	0	56	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	42	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256784	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	784	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22875	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1	0	0
T30	8245	0	0	0
T36	9267	0	0	0
T37	10761	0	0	0
T40	853	1	0	0
T159	721	0	0	0
T160	750	0	0	0
T161	24956	0	0	0
T208	527	0	0	0
T209	704	0	0	0
T210	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	8657	0	0
T4	5536	9	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	82	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	219	0	0
T33	0	104	0	0
T36	0	46	0	0
T38	0	58	0	0
T40	0	40	0	0
T41	0	52	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	58	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5912303	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	529	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22748	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5914534	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	540	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22760	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	65	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	59	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	58	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	58	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	8578	0	0
T4	5536	8	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	79	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T32	0	217	0	0
T33	0	103	0	0
T36	0	44	0	0
T38	0	56	0	0
T40	0	39	0	0
T41	0	50	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	82	0	0
T87	0	80	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	36	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T40	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	1	0	0
T87	0	1	0	0
T138	0	4	0	0
T185	0	1	0	0
T227	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T8,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T4,T8,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T8,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T18
1	0	Covered	T1,T2,T5
1	1	Covered	T4,T8,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T32,T33
0	1	Covered	T8,T139,T155
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T32,T33
0	1	Covered	T32,T70,T40
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T32,T33
1	-	Covered	T32,T70,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T8,T32
DetectSt	168	Covered	T4,T8,T32
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T4,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T8,T32
DebounceSt->IdleSt	163	Covered	T87,T138,T76
DetectSt->IdleSt	186	Covered	T8,T139,T155
DetectSt->StableSt	191	Covered	T4,T32,T33
IdleSt->DebounceSt	148	Covered	T4,T8,T32
StableSt->IdleSt	206	Covered	T4,T32,T70

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T8,T32
0	1	Covered	T4,T8,T32
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T32
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T8,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T8,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T87,T138
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T8,T32
DetectSt	-	-	-	-	1	-	-	Covered	T8,T139,T155
DetectSt	-	-	-	-	0	1	-	Covered	T4,T32,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T70,T40
StableSt	-	-	-	-	-	-	0	Covered	T4,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	105	0	0
CntIncr_A	6888596	60300	0	0
CntNoWrap_A	6888596	6256803	0	0
DetectStDropOut_A	6888596	3	0	0
DetectedOut_A	6888596	36930	0	0
DetectedPulseOut_A	6888596	48	0	0
DisabledIdleSt_A	6888596	6043641	0	0
DisabledNoDetection_A	6888596	6045855	0	0
EnterDebounceSt_A	6888596	55	0	0
EnterDetectSt_A	6888596	51	0	0
EnterStableSt_A	6888596	48	0	0
PulseIsPulse_A	6888596	48	0	0
StayInStableSt	6888596	36857	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6888596	6063	0	0
gen_low_level_sva.LowLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	105	0	0
T4	5536	2	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	2	0	0
T32	0	4	0	0
T33	0	2	0	0
T40	0	4	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	2	0	0
T87	0	1	0	0
T138	0	5	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	60300	0	0
T4	5536	36	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	10	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	41	0	0
T32	0	136	0	0
T33	0	64	0	0
T40	0	160	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	21	0	0
T87	0	95	0	0
T138	0	235	0	0
T168	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256803	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	784	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22877	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	3	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T44	5025	0	0	0
T45	727	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T139	0	1	0	0
T155	0	1	0	0
T228	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	36930	0	0
T4	5536	171	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	2	0	0
T32	0	177	0	0
T33	0	138	0	0
T40	0	80	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	16	0	0
T138	0	381	0	0
T148	0	38	0	0
T168	0	62	0	0
T185	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	48	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T40	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	1	0	0
T138	0	2	0	0
T148	0	1	0	0
T168	0	1	0	0
T185	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6043641	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	529	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22748	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6045855	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	540	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22760	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	55	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T40	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	1	0	0
T87	0	1	0	0
T138	0	3	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	51	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T40	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	1	0	0
T138	0	2	0	0
T148	0	1	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	48	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T40	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	1	0	0
T138	0	2	0	0
T148	0	1	0	0
T168	0	1	0	0
T185	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	48	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T40	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	1	0	0
T138	0	2	0	0
T148	0	1	0	0
T168	0	1	0	0
T185	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	36857	0	0
T4	5536	169	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T32	0	174	0	0
T33	0	136	0	0
T40	0	77	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T70	0	15	0	0
T138	0	379	0	0
T148	0	36	0	0
T168	0	60	0	0
T185	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6063	0	0
T1	14429	9	0	0
T2	4856	31	0	0
T3	14242	23	0	0
T4	5536	26	0	0
T5	4420	0	0	0
T6	16040	13	0	0
T7	15865	6	0	0
T8	25329	23	0	0
T12	700	0	0	0
T13	522	3	0	0
T20	0	26	0	0
T44	0	22	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	22	0	0
T32	1081	1	0	0
T33	781	0	0	0
T40	0	1	0	0
T62	1852	0	0	0
T63	494	0	0	0
T70	0	1	0	0
T78	686	0	0	0
T99	0	1	0	0
T122	404	0	0	0
T123	587	0	0	0
T138	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T200	0	2	0	0
T202	0	1	0	0
T229	841	0	0	0
T230	450	0	0	0
T231	404	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T8,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T4,T8,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T8,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T35
1	0	Covered	T1,T2,T12
1	1	Covered	T4,T8,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T35
0	1	Covered	T4,T8,T37
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T8,T35
1	-	Covered	T4,T8,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T8,T35
DetectSt	168	Covered	T4,T8,T35
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T4,T8,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T8,T35
DebounceSt->IdleSt	163	Covered	T35,T36,T185
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T8,T35
IdleSt->DebounceSt	148	Covered	T4,T8,T35
StableSt->IdleSt	206	Covered	T4,T8,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T8,T35
0	1	Covered	T4,T8,T35
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T35
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T8,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T8,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T185,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T8,T35
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T8,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T8,T37
StableSt	-	-	-	-	-	-	0	Covered	T4,T8,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	111	0	0
CntIncr_A	6888596	97938	0	0
CntNoWrap_A	6888596	6256797	0	0
DetectStDropOut_A	6888596	0	0	0
DetectedOut_A	6888596	50209	0	0
DetectedPulseOut_A	6888596	52	0	0
DisabledIdleSt_A	6888596	6052593	0	0
DisabledNoDetection_A	6888596	6054822	0	0
EnterDebounceSt_A	6888596	60	0	0
EnterDetectSt_A	6888596	52	0	0
EnterStableSt_A	6888596	52	0	0
PulseIsPulse_A	6888596	52	0	0
StayInStableSt	6888596	50140	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	111	0	0
T4	5536	2	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	4	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	2	0	0
T35	0	3	0	0
T37	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	4	0	0
T148	0	2	0	0
T150	0	4	0	0
T151	0	2	0	0
T185	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	97938	0	0
T4	5536	36	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	20	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	41	0	0
T35	0	42	0	0
T36	0	6	0	0
T37	0	77	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	186	0	0
T148	0	25	0	0
T150	0	60	0	0
T185	0	110	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256797	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	784	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22875	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	50209	0	0
T4	5536	17	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	41	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T35	0	43	0	0
T37	0	189	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	216	0	0
T148	0	54	0	0
T150	0	155	0	0
T151	0	81	0	0
T200	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	52	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	2	0	0
T148	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6052593	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	529	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22748	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6054822	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	540	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22760	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	60	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	2	0	0
T148	0	1	0	0
T150	0	2	0	0
T185	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	52	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	2	0	0
T148	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0
T200	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	52	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	2	0	0
T148	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	52	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T138	0	2	0	0
T148	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	50140	0	0
T4	5536	16	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	38	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T35	0	41	0	0
T37	0	188	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T99	0	49	0	0
T138	0	214	0	0
T148	0	52	0	0
T150	0	152	0	0
T151	0	79	0	0
T200	0	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	34	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T37	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T130	0	1	0	0
T138	0	2	0	0
T150	0	1	0	0
T200	0	1	0	0
T219	0	1	0	0
T232	0	2	0	0
T233	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T8,T29,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T8,T29,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T8,T29,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T29
1	0	Covered	T1,T2,T5
1	1	Covered	T8,T29,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T29,T30
0	1	Covered	T130
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T29,T87
0	1	Covered	T8,T29,T31
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T29,T30
1	-	Covered	T8,T29,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T29,T30
DetectSt	168	Covered	T8,T29,T30
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T8,T29,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T29,T30
DebounceSt->IdleSt	163	Covered	T76,T234
DetectSt->IdleSt	186	Covered	T130
DetectSt->StableSt	191	Covered	T8,T29,T30
IdleSt->DebounceSt	148	Covered	T8,T29,T30
StableSt->IdleSt	206	Covered	T8,T29,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T29,T30
0	1	Covered	T8,T29,T30
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T29,T30
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T29,T30
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T29,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T234
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T29,T30
DetectSt	-	-	-	-	1	-	-	Covered	T130
DetectSt	-	-	-	-	0	1	-	Covered	T8,T29,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T29,T30
StableSt	-	-	-	-	-	-	0	Covered	T8,T29,T87
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	84	0	0
CntIncr_A	6888596	49576	0	0
CntNoWrap_A	6888596	6256824	0	0
DetectStDropOut_A	6888596	1	0	0
DetectedOut_A	6888596	2662	0	0
DetectedPulseOut_A	6888596	40	0	0
DisabledIdleSt_A	6888596	6050145	0	0
DisabledNoDetection_A	6888596	6052368	0	0
EnterDebounceSt_A	6888596	43	0	0
EnterDetectSt_A	6888596	41	0	0
EnterStableSt_A	6888596	40	0	0
PulseIsPulse_A	6888596	40	0	0
StayInStableSt	6888596	2601	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6888596	6868	0	0
gen_low_level_sva.LowLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	84	0	0
T8	25329	2	0	0
T9	1274	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	2	0	0
T44	5025	0	0	0
T45	727	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T87	0	2	0	0
T99	0	4	0	0
T130	0	2	0	0
T150	0	2	0	0
T185	0	4	0	0
T186	0	4	0	0
T228	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	49576	0	0
T8	25329	10	0	0
T9	1274	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	52	0	0
T30	0	41	0	0
T31	0	70	0	0
T44	5025	0	0	0
T45	727	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T87	0	95	0	0
T99	0	134	0	0
T130	0	80	0	0
T150	0	30	0	0
T185	0	110	0	0
T186	0	44	0	0
T228	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256824	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22877	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1	0	0
T130	954	1	0	0
T131	495	0	0	0
T132	3125	0	0	0
T178	427	0	0	0
T179	423	0	0	0
T180	5016	0	0	0
T181	404	0	0	0
T182	838	0	0	0
T183	2199	0	0	0
T184	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	2662	0	0
T8	25329	53	0	0
T9	1274	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	85	0	0
T30	0	1	0	0
T31	0	1	0	0
T44	5025	0	0	0
T45	727	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T87	0	43	0	0
T99	0	86	0	0
T150	0	84	0	0
T185	0	79	0	0
T186	0	77	0	0
T218	0	43	0	0
T228	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	40	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T44	5025	0	0	0
T45	727	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T87	0	1	0	0
T99	0	2	0	0
T150	0	1	0	0
T185	0	2	0	0
T186	0	2	0	0
T218	0	1	0	0
T228	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6050145	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13816	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22748	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6052368	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22760	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	43	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T44	5025	0	0	0
T45	727	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T87	0	1	0	0
T99	0	2	0	0
T130	0	1	0	0
T150	0	1	0	0
T185	0	2	0	0
T186	0	2	0	0
T228	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	41	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T44	5025	0	0	0
T45	727	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T87	0	1	0	0
T99	0	2	0	0
T130	0	1	0	0
T150	0	1	0	0
T185	0	2	0	0
T186	0	2	0	0
T228	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	40	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T44	5025	0	0	0
T45	727	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T87	0	1	0	0
T99	0	2	0	0
T150	0	1	0	0
T185	0	2	0	0
T186	0	2	0	0
T218	0	1	0	0
T228	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	40	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T44	5025	0	0	0
T45	727	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T87	0	1	0	0
T99	0	2	0	0
T150	0	1	0	0
T185	0	2	0	0
T186	0	2	0	0
T218	0	1	0	0
T228	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	2601	0	0
T8	25329	52	0	0
T9	1274	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	82	0	0
T44	5025	0	0	0
T45	727	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T87	0	41	0	0
T99	0	83	0	0
T150	0	83	0	0
T152	0	51	0	0
T185	0	76	0	0
T186	0	74	0	0
T218	0	41	0	0
T219	0	141	0	0
T228	402	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6868	0	0
T1	14429	13	0	0
T2	4856	29	0	0
T3	14242	35	0	0
T4	5536	28	0	0
T5	4420	0	0	0
T6	16040	30	0	0
T7	15865	11	0	0
T8	25329	15	0	0
T12	700	3	0	0
T13	522	5	0	0
T20	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	18	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T29	0	1	0	0
T31	0	1	0	0
T44	5025	0	0	0
T45	727	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T99	0	1	0	0
T150	0	1	0	0
T153	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T202	0	2	0	0
T219	0	1	0	0
T228	402	0	0	0