Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T2,T3,T20
1	1	Covered	T2,T3,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T20
0	1	Covered	T2,T71,T91
1	0	Covered	T2,T235,T93

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T20,T42
0	1	Covered	T3,T20,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T20,T42
1	-	Covered	T3,T20,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T20
DetectSt	168	Covered	T2,T3,T20
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T3,T20,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T20
DebounceSt->IdleSt	163	Covered	T44,T30,T76
DetectSt->IdleSt	186	Covered	T2,T71,T91
DetectSt->StableSt	191	Covered	T3,T20,T42
IdleSt->DebounceSt	148	Covered	T2,T3,T20
StableSt->IdleSt	206	Covered	T3,T20,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T20
0	1	Covered	T2,T3,T20
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T20
IdleSt	0	-	-	-	-	-	-	Covered	T2,T3,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T30,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T30,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T20
DetectSt	-	-	-	-	1	-	-	Covered	T2,T71,T91
DetectSt	-	-	-	-	0	1	-	Covered	T3,T20,T42
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T20
StableSt	-	-	-	-	-	-	1	Covered	T3,T20,T42
StableSt	-	-	-	-	-	-	0	Covered	T3,T20,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	3128	0	0
CntIncr_A	6888596	102107	0	0
CntNoWrap_A	6888596	6253780	0	0
DetectStDropOut_A	6888596	385	0	0
DetectedOut_A	6888596	81350	0	0
DetectedPulseOut_A	6888596	906	0	0
DisabledIdleSt_A	6888596	5771081	0	0
DisabledNoDetection_A	6888596	5773144	0	0
EnterDebounceSt_A	6888596	1578	0	0
EnterDetectSt_A	6888596	1550	0	0
EnterStableSt_A	6888596	906	0	0
PulseIsPulse_A	6888596	906	0	0
StayInStableSt	6888596	80327	0	0
gen_high_event_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	789	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	3128	0	0
T2	4856	28	0	0
T3	14242	20	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	18	0	0
T42	0	52	0	0
T43	0	60	0	0
T44	0	17	0	0
T56	0	60	0	0
T71	0	26	0	0
T72	0	52	0	0
T73	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	102107	0	0
T2	4856	590	0	0
T3	14242	540	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	666	0	0
T42	0	1196	0	0
T43	0	1080	0	0
T44	0	833	0	0
T56	0	1140	0	0
T71	0	553	0	0
T72	0	8086	0	0
T73	0	424	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6253780	0	0
T1	14429	14000	0	0
T2	4856	4427	0	0
T3	14242	13796	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	385	0	0
T2	4856	8	0	0
T3	14242	0	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T71	0	13	0	0
T77	0	18	0	0
T91	0	11	0	0
T93	0	10	0	0
T94	0	30	0	0
T96	0	5	0	0
T97	0	20	0	0
T236	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	81350	0	0
T3	14242	382	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	807	0	0
T25	0	3561	0	0
T42	0	2973	0	0
T43	0	1256	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T56	0	1922	0	0
T72	0	7086	0	0
T73	0	55	0	0
T237	0	1955	0	0
T238	0	1929	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	906	0	0
T3	14242	10	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	9	0	0
T25	0	24	0	0
T42	0	26	0	0
T43	0	30	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T56	0	30	0	0
T72	0	26	0	0
T73	0	8	0	0
T237	0	25	0	0
T238	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5771081	0	0
T1	14429	14000	0	0
T2	4856	2153	0	0
T3	14242	9555	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5773144	0	0
T1	14429	14005	0	0
T2	4856	2153	0	0
T3	14242	9557	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1578	0	0
T2	4856	14	0	0
T3	14242	10	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	9	0	0
T42	0	26	0	0
T43	0	30	0	0
T44	0	17	0	0
T56	0	30	0	0
T71	0	13	0	0
T72	0	26	0	0
T73	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1550	0	0
T2	4856	14	0	0
T3	14242	10	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	9	0	0
T42	0	26	0	0
T43	0	30	0	0
T56	0	30	0	0
T71	0	13	0	0
T72	0	26	0	0
T73	0	8	0	0
T91	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	906	0	0
T3	14242	10	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	9	0	0
T25	0	24	0	0
T42	0	26	0	0
T43	0	30	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T56	0	30	0	0
T72	0	26	0	0
T73	0	8	0	0
T237	0	25	0	0
T238	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	906	0	0
T3	14242	10	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	9	0	0
T25	0	24	0	0
T42	0	26	0	0
T43	0	30	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T56	0	30	0	0
T72	0	26	0	0
T73	0	8	0	0
T237	0	25	0	0
T238	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	80327	0	0
T3	14242	371	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	798	0	0
T25	0	3532	0	0
T42	0	2947	0	0
T43	0	1225	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T56	0	1888	0	0
T72	0	7058	0	0
T73	0	47	0	0
T237	0	1926	0	0
T238	0	1914	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	789	0	0
T3	14242	9	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	9	0	0
T25	0	19	0	0
T42	0	26	0	0
T43	0	29	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T56	0	26	0	0
T72	0	24	0	0
T73	0	8	0	0
T237	0	21	0	0
T238	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T3,T4,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T3,T4,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T3,T4,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T5
1	1	Covered	T3,T4,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T75,T24,T27
1	0	Covered	T30,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T4,T7,T8
1	0	Covered	T30,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T7
1	-	Covered	T4,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T7
DetectSt	168	Covered	T3,T4,T7
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T3,T4,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T7
DebounceSt->IdleSt	163	Covered	T4,T46,T24
DetectSt->IdleSt	186	Covered	T75,T24,T27
DetectSt->StableSt	191	Covered	T3,T4,T7
IdleSt->DebounceSt	148	Covered	T3,T4,T7
StableSt->IdleSt	206	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T7
0	1	Covered	T3,T4,T7
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T30,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T46,T24
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T7
DetectSt	-	-	-	-	1	-	-	Covered	T75,T24,T27
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T7
DetectSt	-	-	-	-	0	0	-	Covered	T3,T4,T7
StableSt	-	-	-	-	-	-	1	Covered	T4,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	923	0	0
CntIncr_A	6888596	45093	0	0
CntNoWrap_A	6888596	6255985	0	0
DetectStDropOut_A	6888596	83	0	0
DetectedOut_A	6888596	14208	0	0
DetectedPulseOut_A	6888596	345	0	0
DisabledIdleSt_A	6888596	5896546	0	0
DisabledNoDetection_A	6888596	5898124	0	0
EnterDebounceSt_A	6888596	493	0	0
EnterDetectSt_A	6888596	432	0	0
EnterStableSt_A	6888596	345	0	0
PulseIsPulse_A	6888596	345	0	0
StayInStableSt	6888596	13825	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	303	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	923	0	0
T3	14242	2	0	0
T4	5536	3	0	0
T6	16040	0	0	0
T7	15865	8	0	0
T8	25329	2	0	0
T10	0	2	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T42	0	6	0	0
T43	0	2	0	0
T44	5025	0	0	0
T46	0	22	0	0
T53	4868	0	0	0
T56	0	6	0	0
T75	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	45093	0	0
T3	14242	58	0	0
T4	5536	45	0	0
T6	16040	0	0	0
T7	15865	244	0	0
T8	25329	63	0	0
T10	0	25	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T42	0	174	0	0
T43	0	56	0	0
T44	5025	0	0	0
T46	0	1212	0	0
T53	4868	0	0	0
T56	0	168	0	0
T75	0	115	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6255985	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13814	0	0
T4	5536	783	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15415	0	0
T8	25329	22877	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	83	0	0
T24	0	14	0	0
T27	0	13	0	0
T43	15341	0	0	0
T48	669	0	0	0
T49	8866	0	0	0
T67	521	0	0	0
T68	504	0	0	0
T75	10187	1	0	0
T92	0	3	0	0
T95	0	5	0	0
T98	0	1	0	0
T99	0	2	0	0
T100	0	3	0	0
T102	0	1	0	0
T103	0	8	0	0
T104	919	0	0	0
T105	826	0	0	0
T106	1127	0	0	0
T107	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	14208	0	0
T3	14242	55	0	0
T4	5536	3	0	0
T6	16040	0	0	0
T7	15865	182	0	0
T8	25329	57	0	0
T10	0	4	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T42	0	1247	0	0
T43	0	44	0	0
T44	5025	0	0	0
T46	0	46	0	0
T53	4868	0	0	0
T56	0	109	0	0
T72	0	163	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	345	0	0
T3	14242	1	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	4	0	0
T8	25329	1	0	0
T10	0	1	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	5025	0	0	0
T46	0	10	0	0
T53	4868	0	0	0
T56	0	3	0	0
T72	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5896546	0	0
T1	14429	10072	0	0
T2	4856	4455	0	0
T3	14242	13435	0	0
T4	5536	670	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	12086	0	0
T8	25329	19248	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5898124	0	0
T1	14429	10072	0	0
T2	4856	4456	0	0
T3	14242	13438	0	0
T4	5536	680	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	12086	0	0
T8	25329	19252	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	493	0	0
T3	14242	1	0	0
T4	5536	2	0	0
T6	16040	0	0	0
T7	15865	4	0	0
T8	25329	1	0	0
T10	0	1	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	5025	0	0	0
T46	0	12	0	0
T53	4868	0	0	0
T56	0	3	0	0
T75	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	432	0	0
T3	14242	1	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	4	0	0
T8	25329	1	0	0
T10	0	1	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	5025	0	0	0
T46	0	10	0	0
T53	4868	0	0	0
T56	0	3	0	0
T75	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	345	0	0
T3	14242	1	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	4	0	0
T8	25329	1	0	0
T10	0	1	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	5025	0	0	0
T46	0	10	0	0
T53	4868	0	0	0
T56	0	3	0	0
T72	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	345	0	0
T3	14242	1	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	4	0	0
T8	25329	1	0	0
T10	0	1	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	5025	0	0	0
T46	0	10	0	0
T53	4868	0	0	0
T56	0	3	0	0
T72	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	13825	0	0
T3	14242	53	0	0
T4	5536	2	0	0
T6	16040	0	0	0
T7	15865	178	0	0
T8	25329	56	0	0
T10	0	3	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T42	0	1244	0	0
T43	0	43	0	0
T44	5025	0	0	0
T46	0	36	0	0
T53	4868	0	0	0
T56	0	106	0	0
T72	0	159	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	303	0	0
T4	5536	1	0	0
T6	16040	0	0	0
T7	15865	4	0	0
T8	25329	1	0	0
T9	1274	0	0	0
T10	0	1	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T24	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	5025	0	0	0
T46	0	10	0	0
T53	4868	0	0	0
T56	0	3	0	0
T111	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T3,T20,T42
1	1	Covered	T2,T3,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T20
0	1	Covered	T56,T71,T91
1	0	Covered	T42,T56,T238

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T20
0	1	Covered	T2,T3,T20
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T20
1	-	Covered	T2,T3,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T20
DetectSt	168	Covered	T2,T3,T20
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T2,T3,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T20
DebounceSt->IdleSt	163	Covered	T44,T30,T76
DetectSt->IdleSt	186	Covered	T42,T56,T71
DetectSt->StableSt	191	Covered	T2,T3,T20
IdleSt->DebounceSt	148	Covered	T2,T3,T20
StableSt->IdleSt	206	Covered	T2,T3,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T20
0	1	Covered	T2,T3,T20
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T20
IdleSt	0	-	-	-	-	-	-	Covered	T2,T3,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T30,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T30,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T20
DetectSt	-	-	-	-	1	-	-	Covered	T42,T56,T71
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T20
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T20
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T20
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T20
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	3312	0	0
CntIncr_A	6888596	113528	0	0
CntNoWrap_A	6888596	6253596	0	0
DetectStDropOut_A	6888596	338	0	0
DetectedOut_A	6888596	97857	0	0
DetectedPulseOut_A	6888596	1142	0	0
DisabledIdleSt_A	6888596	5753071	0	0
DisabledNoDetection_A	6888596	5755103	0	0
EnterDebounceSt_A	6888596	1669	0	0
EnterDetectSt_A	6888596	1643	0	0
EnterStableSt_A	6888596	1142	0	0
PulseIsPulse_A	6888596	1142	0	0
StayInStableSt	6888596	96567	0	0
gen_high_event_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	993	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	3312	0	0
T2	4856	12	0	0
T3	14242	20	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	20	0	0
T42	0	26	0	0
T43	0	56	0	0
T44	0	14	0	0
T56	0	46	0	0
T71	0	54	0	0
T72	0	26	0	0
T73	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	113528	0	0
T2	4856	252	0	0
T3	14242	450	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	1000	0	0
T42	0	867	0	0
T43	0	1036	0	0
T44	0	686	0	0
T56	0	1254	0	0
T71	0	1158	0	0
T72	0	5473	0	0
T73	0	1254	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6253596	0	0
T1	14429	14000	0	0
T2	4856	4443	0	0
T3	14242	13796	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	338	0	0
T30	0	1	0	0
T43	15341	0	0	0
T48	669	0	0	0
T49	8866	0	0	0
T56	14872	11	0	0
T67	521	0	0	0
T71	0	27	0	0
T75	10187	0	0	0
T77	0	10	0	0
T91	0	15	0	0
T93	0	21	0	0
T94	0	27	0	0
T96	0	20	0	0
T104	919	0	0	0
T105	826	0	0	0
T106	1127	0	0	0
T107	402	0	0	0
T236	0	6	0	0
T238	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	97857	0	0
T2	4856	134	0	0
T3	14242	472	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	463	0	0
T25	0	1019	0	0
T26	0	668	0	0
T43	0	1880	0	0
T72	0	2491	0	0
T73	0	1354	0	0
T235	0	729	0	0
T237	0	626	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1142	0	0
T2	4856	6	0	0
T3	14242	10	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	10	0	0
T25	0	11	0	0
T26	0	10	0	0
T43	0	28	0	0
T72	0	13	0	0
T73	0	22	0	0
T235	0	17	0	0
T237	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5753071	0	0
T1	14429	14000	0	0
T2	4856	2015	0	0
T3	14242	9555	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5755103	0	0
T1	14429	14005	0	0
T2	4856	2015	0	0
T3	14242	9557	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1669	0	0
T2	4856	6	0	0
T3	14242	10	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	10	0	0
T42	0	13	0	0
T43	0	28	0	0
T44	0	14	0	0
T56	0	23	0	0
T71	0	27	0	0
T72	0	13	0	0
T73	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1643	0	0
T2	4856	6	0	0
T3	14242	10	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	10	0	0
T42	0	13	0	0
T43	0	28	0	0
T56	0	23	0	0
T71	0	27	0	0
T72	0	13	0	0
T73	0	22	0	0
T91	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1142	0	0
T2	4856	6	0	0
T3	14242	10	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	10	0	0
T25	0	11	0	0
T26	0	10	0	0
T43	0	28	0	0
T72	0	13	0	0
T73	0	22	0	0
T235	0	17	0	0
T237	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1142	0	0
T2	4856	6	0	0
T3	14242	10	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	10	0	0
T25	0	11	0	0
T26	0	10	0	0
T43	0	28	0	0
T72	0	13	0	0
T73	0	22	0	0
T235	0	17	0	0
T237	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	96567	0	0
T2	4856	128	0	0
T3	14242	461	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	453	0	0
T25	0	1007	0	0
T26	0	657	0	0
T43	0	1848	0	0
T72	0	2476	0	0
T73	0	1330	0	0
T235	0	711	0	0
T237	0	599	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	993	0	0
T2	4856	6	0	0
T3	14242	9	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	10	0	0
T25	0	10	0	0
T26	0	9	0	0
T43	0	24	0	0
T72	0	11	0	0
T73	0	20	0	0
T235	0	16	0	0
T237	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T46,T27,T92
1	0	Covered	T30,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T30,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T1,T24,T239
DetectSt->IdleSt	186	Covered	T46,T27,T92
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T30,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T24,T239
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T46,T27,T92
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	916	0	0
CntIncr_A	6888596	50641	0	0
CntNoWrap_A	6888596	6255992	0	0
DetectStDropOut_A	6888596	87	0	0
DetectedOut_A	6888596	15232	0	0
DetectedPulseOut_A	6888596	346	0	0
DisabledIdleSt_A	6888596	5880253	0	0
DisabledNoDetection_A	6888596	5881856	0	0
EnterDebounceSt_A	6888596	479	0	0
EnterDetectSt_A	6888596	437	0	0
EnterStableSt_A	6888596	346	0	0
PulseIsPulse_A	6888596	346	0	0
StayInStableSt	6888596	14840	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	296	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	916	0	0
T1	14429	4	0	0
T2	4856	2	0	0
T3	14242	2	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	4	0	0
T12	700	0	0	0
T13	522	0	0	0
T24	0	13	0	0
T43	0	2	0	0
T46	0	24	0	0
T72	0	2	0	0
T73	0	4	0	0
T75	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	50641	0	0
T1	14429	302	0	0
T2	4856	64	0	0
T3	14242	46	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	220	0	0
T12	700	0	0	0
T13	522	0	0	0
T24	0	358	0	0
T43	0	46	0	0
T46	0	1455	0	0
T72	0	314	0	0
T73	0	64	0	0
T75	0	188	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6255992	0	0
T1	14429	13996	0	0
T2	4856	4453	0	0
T3	14242	13814	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22875	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	87	0	0
T18	2067	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T35	665	0	0	0
T38	1986	0	0	0
T42	8434	0	0	0
T46	26333	12	0	0
T47	780	0	0	0
T66	543	0	0	0
T89	423	0	0	0
T90	427	0	0	0
T92	0	2	0	0
T98	0	7	0	0
T143	423	0	0	0
T240	0	2	0	0
T241	0	3	0	0
T242	0	6	0	0
T243	0	14	0	0
T244	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	15232	0	0
T1	14429	4	0	0
T2	4856	41	0	0
T3	14242	67	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	19	0	0
T12	700	0	0	0
T13	522	0	0	0
T24	0	65	0	0
T43	0	53	0	0
T72	0	67	0	0
T73	0	140	0	0
T75	0	43	0	0
T237	0	115	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	346	0	0
T1	14429	1	0	0
T2	4856	1	0	0
T3	14242	1	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T12	700	0	0	0
T13	522	0	0	0
T24	0	6	0	0
T43	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T75	0	2	0	0
T237	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5880253	0	0
T1	14429	10072	0	0
T2	4856	4321	0	0
T3	14242	13345	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	12086	0	0
T8	25329	19248	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5881856	0	0
T1	14429	10072	0	0
T2	4856	4322	0	0
T3	14242	13348	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	12086	0	0
T8	25329	19252	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	479	0	0
T1	14429	3	0	0
T2	4856	1	0	0
T3	14242	1	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T12	700	0	0	0
T13	522	0	0	0
T24	0	7	0	0
T43	0	1	0	0
T46	0	12	0	0
T72	0	1	0	0
T73	0	2	0	0
T75	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	437	0	0
T1	14429	1	0	0
T2	4856	1	0	0
T3	14242	1	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T12	700	0	0	0
T13	522	0	0	0
T24	0	6	0	0
T43	0	1	0	0
T46	0	12	0	0
T72	0	1	0	0
T73	0	2	0	0
T75	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	346	0	0
T1	14429	1	0	0
T2	4856	1	0	0
T3	14242	1	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T12	700	0	0	0
T13	522	0	0	0
T24	0	6	0	0
T43	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T75	0	2	0	0
T237	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	346	0	0
T1	14429	1	0	0
T2	4856	1	0	0
T3	14242	1	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T12	700	0	0	0
T13	522	0	0	0
T24	0	6	0	0
T43	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T75	0	2	0	0
T237	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	14840	0	0
T1	14429	3	0	0
T2	4856	40	0	0
T3	14242	65	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	17	0	0
T12	700	0	0	0
T13	522	0	0	0
T24	0	59	0	0
T43	0	51	0	0
T72	0	65	0	0
T73	0	136	0	0
T75	0	41	0	0
T237	0	111	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	296	0	0
T1	14429	1	0	0
T2	4856	1	0	0
T3	14242	0	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	2	0	0
T12	700	0	0	0
T13	522	0	0	0
T24	0	6	0	0
T26	0	1	0	0
T75	0	2	0	0
T95	0	6	0	0
T97	0	2	0	0
T235	0	1	0	0
T239	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T2,T3,T20
1	1	Covered	T2,T3,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T20
0	1	Covered	T2,T42,T71
1	0	Covered	T2,T42,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T20,T43
0	1	Covered	T3,T20,T43
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T20,T43
1	-	Covered	T3,T20,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T20
DetectSt	168	Covered	T2,T3,T20
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T3,T20,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T20
DebounceSt->IdleSt	163	Covered	T44,T30,T76
DetectSt->IdleSt	186	Covered	T2,T42,T56
DetectSt->StableSt	191	Covered	T3,T20,T43
IdleSt->DebounceSt	148	Covered	T2,T3,T20
StableSt->IdleSt	206	Covered	T3,T20,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T20
0	1	Covered	T2,T3,T20
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T20
IdleSt	0	-	-	-	-	-	-	Covered	T2,T3,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T30,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T30,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T20
DetectSt	-	-	-	-	1	-	-	Covered	T2,T42,T56
DetectSt	-	-	-	-	0	1	-	Covered	T3,T20,T43
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T20
StableSt	-	-	-	-	-	-	1	Covered	T3,T20,T43
StableSt	-	-	-	-	-	-	0	Covered	T3,T20,T43
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	3329	0	0
CntIncr_A	6888596	127733	0	0
CntNoWrap_A	6888596	6253579	0	0
DetectStDropOut_A	6888596	407	0	0
DetectedOut_A	6888596	86560	0	0
DetectedPulseOut_A	6888596	960	0	0
DisabledIdleSt_A	6888596	5762601	0	0
DisabledNoDetection_A	6888596	5764676	0	0
EnterDebounceSt_A	6888596	1674	0	0
EnterDetectSt_A	6888596	1655	0	0
EnterStableSt_A	6888596	960	0	0
PulseIsPulse_A	6888596	960	0	0
StayInStableSt	6888596	85495	0	0
gen_high_event_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	854	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	3329	0	0
T2	4856	42	0	0
T3	14242	54	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	52	0	0
T42	0	64	0	0
T43	0	50	0	0
T44	0	6	0	0
T56	0	8	0	0
T71	0	14	0	0
T72	0	60	0	0
T73	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	127733	0	0
T2	4856	879	0	0
T3	14242	1674	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	2574	0	0
T42	0	2135	0	0
T43	0	900	0	0
T44	0	294	0	0
T56	0	217	0	0
T71	0	294	0	0
T72	0	15180	0	0
T73	0	583	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6253579	0	0
T1	14429	14000	0	0
T2	4856	4413	0	0
T3	14242	13762	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	407	0	0
T2	4856	15	0	0
T3	14242	0	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T42	0	8	0	0
T71	0	7	0	0
T91	0	15	0	0
T96	0	22	0	0
T97	0	4	0	0
T215	0	12	0	0
T238	0	14	0	0
T245	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	86560	0	0
T3	14242	1934	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	2780	0	0
T25	0	788	0	0
T26	0	638	0	0
T43	0	1721	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T72	0	5281	0	0
T73	0	69	0	0
T93	0	1401	0	0
T94	0	21	0	0
T235	0	1215	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	960	0	0
T3	14242	27	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	26	0	0
T25	0	14	0	0
T26	0	10	0	0
T43	0	25	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T72	0	30	0	0
T73	0	11	0	0
T93	0	11	0	0
T94	0	3	0	0
T235	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5762601	0	0
T1	14429	14000	0	0
T2	4856	2153	0	0
T3	14242	8192	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5764676	0	0
T1	14429	14005	0	0
T2	4856	2153	0	0
T3	14242	8193	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1674	0	0
T2	4856	21	0	0
T3	14242	27	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	26	0	0
T42	0	32	0	0
T43	0	25	0	0
T44	0	6	0	0
T56	0	4	0	0
T71	0	7	0	0
T72	0	30	0	0
T73	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1655	0	0
T2	4856	21	0	0
T3	14242	27	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	26	0	0
T42	0	32	0	0
T43	0	25	0	0
T56	0	4	0	0
T71	0	7	0	0
T72	0	30	0	0
T73	0	11	0	0
T91	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	960	0	0
T3	14242	27	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	26	0	0
T25	0	14	0	0
T26	0	10	0	0
T43	0	25	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T72	0	30	0	0
T73	0	11	0	0
T93	0	11	0	0
T94	0	3	0	0
T235	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	960	0	0
T3	14242	27	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	26	0	0
T25	0	14	0	0
T26	0	10	0	0
T43	0	25	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T72	0	30	0	0
T73	0	11	0	0
T93	0	11	0	0
T94	0	3	0	0
T235	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	85495	0	0
T3	14242	1905	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	2753	0	0
T25	0	773	0	0
T26	0	627	0	0
T43	0	1693	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T72	0	5251	0	0
T73	0	58	0	0
T93	0	1390	0	0
T94	0	18	0	0
T235	0	1187	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	854	0	0
T3	14242	25	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	25	0	0
T25	0	13	0	0
T26	0	9	0	0
T43	0	22	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T72	0	30	0	0
T73	0	11	0	0
T93	0	11	0	0
T94	0	3	0	0
T235	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T3,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T3,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T3,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T5
1	1	Covered	T3,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T24,T27,T163
1	0	Covered	T30,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T8
1	-	Covered	T3,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T8
DetectSt	168	Covered	T3,T7,T8
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T8
DebounceSt->IdleSt	163	Covered	T3,T43,T24
DetectSt->IdleSt	186	Covered	T24,T27,T30
DetectSt->StableSt	191	Covered	T3,T7,T8
IdleSt->DebounceSt	148	Covered	T3,T7,T8
StableSt->IdleSt	206	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T30,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T43,T24
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T24,T27,T30
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T8
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	823	0	0
CntIncr_A	6888596	47213	0	0
CntNoWrap_A	6888596	6256085	0	0
DetectStDropOut_A	6888596	44	0	0
DetectedOut_A	6888596	13550	0	0
DetectedPulseOut_A	6888596	341	0	0
DisabledIdleSt_A	6888596	5893750	0	0
DisabledNoDetection_A	6888596	5895391	0	0
EnterDebounceSt_A	6888596	434	0	0
EnterDetectSt_A	6888596	389	0	0
EnterStableSt_A	6888596	341	0	0
PulseIsPulse_A	6888596	341	0	0
StayInStableSt	6888596	13167	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	294	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	823	0	0
T3	14242	5	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	2	0	0
T8	25329	16	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	2	0	0
T24	0	5	0	0
T25	0	2	0	0
T27	0	8	0	0
T43	0	5	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T75	0	12	0	0
T92	0	19	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	47213	0	0
T3	14242	123	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	74	0	0
T8	25329	888	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	84	0	0
T24	0	162	0	0
T25	0	92	0	0
T27	0	329	0	0
T43	0	124	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T75	0	474	0	0
T92	0	705	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256085	0	0
T1	14429	14000	0	0
T2	4856	4455	0	0
T3	14242	13811	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15421	0	0
T8	25329	22863	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	44	0	0
T24	18044	2	0	0
T27	15503	4	0	0
T51	2448	0	0	0
T52	774	0	0	0
T59	1588	0	0	0
T73	10927	0	0	0
T91	5121	0	0	0
T102	0	3	0	0
T111	1909	0	0	0
T163	0	3	0	0
T246	0	2	0	0
T247	0	1	0	0
T248	0	6	0	0
T249	0	2	0	0
T250	0	7	0	0
T251	0	4	0	0
T252	755	0	0	0
T253	521	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	13550	0	0
T3	14242	131	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	32	0	0
T8	25329	78	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	65	0	0
T25	0	55	0	0
T26	0	80	0	0
T43	0	90	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T75	0	220	0	0
T92	0	75	0	0
T235	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	341	0	0
T3	14242	2	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	1	0	0
T8	25329	8	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T43	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T75	0	6	0	0
T92	0	9	0	0
T235	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5893750	0	0
T1	14429	10072	0	0
T2	4856	4455	0	0
T3	14242	11884	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	12086	0	0
T8	25329	19248	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5895391	0	0
T1	14429	10072	0	0
T2	4856	4456	0	0
T3	14242	11886	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	12086	0	0
T8	25329	19252	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	434	0	0
T3	14242	3	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	1	0	0
T8	25329	8	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	1	0	0
T24	0	3	0	0
T25	0	1	0	0
T27	0	4	0	0
T43	0	3	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T75	0	6	0	0
T92	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	389	0	0
T3	14242	2	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	1	0	0
T8	25329	8	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T27	0	4	0	0
T43	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T75	0	6	0	0
T92	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	341	0	0
T3	14242	2	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	1	0	0
T8	25329	8	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T43	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T75	0	6	0	0
T92	0	9	0	0
T235	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	341	0	0
T3	14242	2	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	1	0	0
T8	25329	8	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T43	0	2	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T75	0	6	0	0
T92	0	9	0	0
T235	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	13167	0	0
T3	14242	129	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	31	0	0
T8	25329	70	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	63	0	0
T25	0	54	0	0
T26	0	79	0	0
T43	0	86	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T75	0	214	0	0
T92	0	66	0	0
T235	0	80	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	294	0	0
T3	14242	2	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	1	0	0
T8	25329	8	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T75	0	6	0	0
T92	0	9	0	0
T93	0	1	0	0
T235	0	2	0	0
T239	0	1	0	0