Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T3,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T2,T3,T20
1	1	Covered	T2,T3,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T20
0	1	Covered	T2,T71,T91
1	0	Covered	T2,T93,T97

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T20,T42
0	1	Covered	T3,T20,T42
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T20,T42
1	-	Covered	T3,T20,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T20
DetectSt	168	Covered	T2,T3,T20
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T3,T20,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T20
DebounceSt->IdleSt	163	Covered	T44,T30,T76
DetectSt->IdleSt	186	Covered	T2,T71,T91
DetectSt->StableSt	191	Covered	T3,T20,T42
IdleSt->DebounceSt	148	Covered	T2,T3,T20
StableSt->IdleSt	206	Covered	T3,T20,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T20
0	1	Covered	T2,T3,T20
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T20
IdleSt	0	-	-	-	-	-	-	Covered	T2,T3,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T30,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T30,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T20
DetectSt	-	-	-	-	1	-	-	Covered	T2,T71,T91
DetectSt	-	-	-	-	0	1	-	Covered	T3,T20,T42
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T20
StableSt	-	-	-	-	-	-	1	Covered	T3,T20,T42
StableSt	-	-	-	-	-	-	0	Covered	T3,T20,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	3190	0	0
CntIncr_A	6888596	118009	0	0
CntNoWrap_A	6888596	6253718	0	0
DetectStDropOut_A	6888596	364	0	0
DetectedOut_A	6888596	92597	0	0
DetectedPulseOut_A	6888596	1024	0	0
DisabledIdleSt_A	6888596	5764669	0	0
DisabledNoDetection_A	6888596	5766748	0	0
EnterDebounceSt_A	6888596	1605	0	0
EnterDetectSt_A	6888596	1585	0	0
EnterStableSt_A	6888596	1024	0	0
PulseIsPulse_A	6888596	1024	0	0
StayInStableSt	6888596	91472	0	0
gen_high_event_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	919	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	3190	0	0
T2	4856	38	0	0
T3	14242	8	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	32	0	0
T42	0	48	0	0
T43	0	54	0	0
T44	0	6	0	0
T56	0	24	0	0
T71	0	44	0	0
T72	0	60	0	0
T73	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	118009	0	0
T2	4856	799	0	0
T3	14242	240	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	1232	0	0
T42	0	1272	0	0
T43	0	1323	0	0
T44	0	294	0	0
T56	0	336	0	0
T71	0	949	0	0
T72	0	8820	0	0
T73	0	155	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6253718	0	0
T1	14429	14000	0	0
T2	4856	4417	0	0
T3	14242	13808	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	364	0	0
T2	4856	13	0	0
T3	14242	0	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	0	0	0
T30	0	1	0	0
T71	0	22	0	0
T91	0	28	0	0
T94	0	10	0	0
T97	0	4	0	0
T126	0	8	0	0
T215	0	13	0	0
T236	0	1	0	0
T254	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	92597	0	0
T3	14242	196	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	1259	0	0
T25	0	3561	0	0
T42	0	386	0	0
T43	0	823	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T56	0	1284	0	0
T72	0	11641	0	0
T73	0	141	0	0
T237	0	318	0	0
T238	0	463	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1024	0	0
T3	14242	4	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	16	0	0
T25	0	24	0	0
T42	0	24	0	0
T43	0	27	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T56	0	12	0	0
T72	0	30	0	0
T73	0	5	0	0
T237	0	12	0	0
T238	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5764669	0	0
T1	14429	14000	0	0
T2	4856	2153	0	0
T3	14242	9582	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22879	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5766748	0	0
T1	14429	14005	0	0
T2	4856	2153	0	0
T3	14242	9584	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1605	0	0
T2	4856	19	0	0
T3	14242	4	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	16	0	0
T42	0	24	0	0
T43	0	27	0	0
T44	0	6	0	0
T56	0	12	0	0
T71	0	22	0	0
T72	0	30	0	0
T73	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1585	0	0
T2	4856	19	0	0
T3	14242	4	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T20	13657	16	0	0
T42	0	24	0	0
T43	0	27	0	0
T56	0	12	0	0
T71	0	22	0	0
T72	0	30	0	0
T73	0	5	0	0
T91	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1024	0	0
T3	14242	4	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	16	0	0
T25	0	24	0	0
T42	0	24	0	0
T43	0	27	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T56	0	12	0	0
T72	0	30	0	0
T73	0	5	0	0
T237	0	12	0	0
T238	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	1024	0	0
T3	14242	4	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	16	0	0
T25	0	24	0	0
T42	0	24	0	0
T43	0	27	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T56	0	12	0	0
T72	0	30	0	0
T73	0	5	0	0
T237	0	12	0	0
T238	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	91472	0	0
T3	14242	191	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	1243	0	0
T25	0	3532	0	0
T42	0	362	0	0
T43	0	795	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T56	0	1268	0	0
T72	0	11611	0	0
T73	0	136	0	0
T237	0	304	0	0
T238	0	458	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	919	0	0
T3	14242	3	0	0
T4	5536	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T13	522	0	0	0
T19	32178	0	0	0
T20	13657	16	0	0
T25	0	19	0	0
T42	0	24	0	0
T43	0	26	0	0
T44	5025	0	0	0
T53	4868	0	0	0
T56	0	8	0	0
T72	0	30	0	0
T73	0	5	0	0
T237	0	10	0	0
T238	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T3,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T5	VC_COV_UNR
1	Covered	T1,T3,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T3,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T3,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T8,T24,T92
1	0	Covered	T30,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T56
0	1	Covered	T1,T75,T43
1	0	Covered	T77,T255

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T56
1	-	Covered	T1,T75,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T8
DetectSt	168	Covered	T1,T3,T8
IdleSt	163	Covered	T1,T2,T5
StableSt	191	Covered	T1,T3,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T8
DebounceSt->IdleSt	163	Covered	T1,T24,T25
DetectSt->IdleSt	186	Covered	T8,T24,T92
DetectSt->StableSt	191	Covered	T1,T3,T56
IdleSt->DebounceSt	148	Covered	T1,T3,T8
StableSt->IdleSt	206	Covered	T1,T3,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
0	0	Excluded	T1,T2,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T30,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T24,T25
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	1	-	-	Covered	T8,T24,T92
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T56
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T75,T43
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6888596	816	0	0
CntIncr_A	6888596	47316	0	0
CntNoWrap_A	6888596	6256092	0	0
DetectStDropOut_A	6888596	65	0	0
DetectedOut_A	6888596	14067	0	0
DetectedPulseOut_A	6888596	317	0	0
DisabledIdleSt_A	6888596	5893307	0	0
DisabledNoDetection_A	6888596	5894961	0	0
EnterDebounceSt_A	6888596	430	0	0
EnterDetectSt_A	6888596	386	0	0
EnterStableSt_A	6888596	317	0	0
PulseIsPulse_A	6888596	317	0	0
StayInStableSt	6888596	13713	0	0
gen_high_level_sva.HighLevelEvent_A	6888596	6259184	0	0
gen_not_sticky_sva.StableStDropOut_A	6888596	275	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	816	0	0
T1	14429	10	0	0
T2	4856	0	0	0
T3	14242	2	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	6	0	0
T12	700	0	0	0
T13	522	0	0	0
T24	0	5	0	0
T27	0	10	0	0
T43	0	2	0	0
T56	0	8	0	0
T75	0	2	0	0
T92	0	4	0	0
T237	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	47316	0	0
T1	14429	548	0	0
T2	4856	0	0	0
T3	14242	67	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	358	0	0
T12	700	0	0	0
T13	522	0	0	0
T24	0	162	0	0
T27	0	350	0	0
T43	0	66	0	0
T56	0	216	0	0
T75	0	97	0	0
T92	0	161	0	0
T237	0	50	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6256092	0	0
T1	14429	13990	0	0
T2	4856	4455	0	0
T3	14242	13814	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	15423	0	0
T8	25329	22873	0	0
T12	700	299	0	0
T13	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	65	0	0
T8	25329	3	0	0
T9	1274	0	0	0
T19	32178	0	0	0
T20	13657	0	0	0
T24	0	2	0	0
T44	5025	0	0	0
T45	727	0	0	0
T53	4868	0	0	0
T54	426	0	0	0
T55	51982	0	0	0
T92	0	2	0	0
T138	0	1	0	0
T218	0	1	0	0
T228	402	0	0	0
T239	0	1	0	0
T242	0	6	0	0
T247	0	4	0	0
T256	0	1	0	0
T257	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	14067	0	0
T1	14429	200	0	0
T2	4856	0	0	0
T3	14242	46	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T25	0	283	0	0
T26	0	70	0	0
T27	0	62	0	0
T43	0	34	0	0
T56	0	148	0	0
T75	0	18	0	0
T77	0	303	0	0
T237	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	317	0	0
T1	14429	4	0	0
T2	4856	0	0	0
T3	14242	1	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T25	0	4	0	0
T26	0	1	0	0
T27	0	5	0	0
T43	0	1	0	0
T56	0	4	0	0
T75	0	1	0	0
T77	0	4	0	0
T237	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5893307	0	0
T1	14429	10072	0	0
T2	4856	4455	0	0
T3	14242	13621	0	0
T4	5536	786	0	0
T5	4420	10	0	0
T6	16040	11605	0	0
T7	15865	12086	0	0
T8	25329	19248	0	0
T12	700	299	0	0
T13	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	5894961	0	0
T1	14429	10072	0	0
T2	4856	4456	0	0
T3	14242	13624	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	12086	0	0
T8	25329	19252	0	0
T12	700	300	0	0
T13	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	430	0	0
T1	14429	6	0	0
T2	4856	0	0	0
T3	14242	1	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	3	0	0
T12	700	0	0	0
T13	522	0	0	0
T24	0	3	0	0
T27	0	5	0	0
T43	0	1	0	0
T56	0	4	0	0
T75	0	1	0	0
T92	0	2	0	0
T237	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	386	0	0
T1	14429	4	0	0
T2	4856	0	0	0
T3	14242	1	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	3	0	0
T12	700	0	0	0
T13	522	0	0	0
T24	0	2	0	0
T27	0	5	0	0
T43	0	1	0	0
T56	0	4	0	0
T75	0	1	0	0
T92	0	2	0	0
T237	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	317	0	0
T1	14429	4	0	0
T2	4856	0	0	0
T3	14242	1	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T25	0	4	0	0
T26	0	1	0	0
T27	0	5	0	0
T43	0	1	0	0
T56	0	4	0	0
T75	0	1	0	0
T77	0	4	0	0
T237	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	317	0	0
T1	14429	4	0	0
T2	4856	0	0	0
T3	14242	1	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T25	0	4	0	0
T26	0	1	0	0
T27	0	5	0	0
T43	0	1	0	0
T56	0	4	0	0
T75	0	1	0	0
T77	0	4	0	0
T237	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	13713	0	0
T1	14429	196	0	0
T2	4856	0	0	0
T3	14242	44	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T25	0	275	0	0
T26	0	69	0	0
T27	0	57	0	0
T43	0	33	0	0
T56	0	140	0	0
T75	0	17	0	0
T77	0	299	0	0
T237	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	6259184	0	0
T1	14429	14005	0	0
T2	4856	4456	0	0
T3	14242	13820	0	0
T4	5536	798	0	0
T5	4420	20	0	0
T6	16040	11619	0	0
T7	15865	15429	0	0
T8	25329	22892	0	0
T12	700	300	0	0
T13	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6888596	275	0	0
T1	14429	4	0	0
T2	4856	0	0	0
T3	14242	0	0	0
T4	5536	0	0	0
T5	4420	0	0	0
T6	16040	0	0	0
T7	15865	0	0	0
T8	25329	0	0	0
T12	700	0	0	0
T13	522	0	0	0
T26	0	1	0	0
T27	0	5	0	0
T28	0	2	0	0
T43	0	1	0	0
T75	0	1	0	0
T77	0	3	0	0
T95	0	6	0	0
T96	0	6	0	0
T240	0	11	0	0