Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T19
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T19
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T19,T21,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T19,T21,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T19,T21,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T11
1	0	Covered	T6,T7,T19
1	1	Covered	T19,T21,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T48
0	1	Covered	T40,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T48
0	1	Covered	T19,T21,T48
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T21,T48
1	-	Covered	T19,T21,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T21,T11
DetectSt	168	Covered	T19,T21,T48
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T19,T21,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T21,T48
DebounceSt->IdleSt	163	Covered	T11,T48,T58
DetectSt->IdleSt	186	Covered	T32,T40,T78
DetectSt->StableSt	191	Covered	T19,T21,T48
IdleSt->DebounceSt	148	Covered	T19,T21,T11
StableSt->IdleSt	206	Covered	T19,T21,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T21,T11
0	1	Covered	T19,T21,T11
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T21,T48
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T21,T11
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T21,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T58,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T21,T11
DetectSt	-	-	-	-	1	-	-	Covered	T40,T78
DetectSt	-	-	-	-	0	1	-	Covered	T19,T21,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T21,T48
StableSt	-	-	-	-	-	-	0	Covered	T19,T21,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	321	0	0
CntIncr_A	7995523	120158	0	0
CntNoWrap_A	7995523	7319708	0	0
DetectStDropOut_A	7995523	2	0	0
DetectedOut_A	7995523	930	0	0
DetectedPulseOut_A	7995523	142	0	0
DisabledIdleSt_A	7995523	7192190	0	0
DisabledNoDetection_A	7995523	7194631	0	0
EnterDebounceSt_A	7995523	182	0	0
EnterDetectSt_A	7995523	144	0	0
EnterStableSt_A	7995523	142	0	0
PulseIsPulse_A	7995523	142	0	0
StayInStableSt	7995523	788	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7995523	7049	0	0
gen_low_level_sva.LowLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	142	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	321	0	0
T1	18127	0	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T11	0	1	0	0
T13	0	4	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T19	719	2	0	0
T20	526	0	0	0
T21	681	2	0	0
T38	0	2	0	0
T48	0	3	0	0
T49	0	4	0	0
T51	0	2	0	0
T52	0	4	0	0
T53	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	120158	0	0
T1	18127	0	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T11	0	28	0	0
T13	0	55	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T19	719	85	0	0
T20	526	0	0	0
T21	681	67	0	0
T38	0	98	0	0
T48	0	84	0	0
T49	0	57	0	0
T51	0	91	0	0
T52	0	99	0	0
T53	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7319708	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	316	0	0
T20	526	125	0	0
T21	681	278	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	2	0	0
T40	18729	1	0	0
T72	5073	0	0	0
T78	0	1	0	0
T102	7866	0	0	0
T103	1099	0	0	0
T104	755	0	0	0
T105	495	0	0	0
T106	697	0	0	0
T107	418	0	0	0
T108	25635	0	0	0
T109	664	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	930	0	0
T1	18127	0	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T13	0	12	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T19	719	10	0	0
T20	526	0	0	0
T21	681	7	0	0
T38	0	6	0	0
T48	0	10	0	0
T49	0	9	0	0
T51	0	6	0	0
T52	0	5	0	0
T53	0	12	0	0
T110	0	21	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	142	0	0
T1	18127	0	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T13	0	2	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T19	719	1	0	0
T20	526	0	0	0
T21	681	1	0	0
T38	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T110	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7192190	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	187	0	0
T20	526	125	0	0
T21	681	161	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7194631	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	188	0	0
T20	526	126	0	0
T21	681	162	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	182	0	0
T1	18127	0	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T19	719	1	0	0
T20	526	0	0	0
T21	681	1	0	0
T38	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	144	0	0
T1	18127	0	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T13	0	2	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T19	719	1	0	0
T20	526	0	0	0
T21	681	1	0	0
T38	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T110	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	142	0	0
T1	18127	0	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T13	0	2	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T19	719	1	0	0
T20	526	0	0	0
T21	681	1	0	0
T38	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T110	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	142	0	0
T1	18127	0	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T13	0	2	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T19	719	1	0	0
T20	526	0	0	0
T21	681	1	0	0
T38	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T110	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	788	0	0
T1	18127	0	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T13	0	10	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T19	719	9	0	0
T20	526	0	0	0
T21	681	6	0	0
T38	0	5	0	0
T48	0	9	0	0
T49	0	7	0	0
T51	0	5	0	0
T52	0	3	0	0
T53	0	11	0	0
T110	0	19	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7049	0	0
T1	18127	35	0	0
T2	35596	33	0	0
T4	0	12	0	0
T6	5416	30	0	0
T7	9280	26	0	0
T8	696	0	0	0
T14	875	0	0	0
T15	494	7	0	0
T16	0	6	0	0
T19	719	3	0	0
T20	526	5	0	0
T21	681	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	142	0	0
T1	18127	0	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T13	0	2	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T19	719	1	0	0
T20	526	0	0	0
T21	681	1	0	0
T38	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T110	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T19
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T19
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T11,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T4,T11,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T32,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T25
1	0	Covered	T6,T7,T19
1	1	Covered	T4,T11,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T32,T59
0	1	Covered	T4,T73,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T32,T59
0	1	Unreachable
1	0	Covered	T4,T32,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T11,T25
DetectSt	168	Covered	T4,T32,T59
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T4,T32,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T32,T59
DebounceSt->IdleSt	163	Covered	T4,T11,T25
DetectSt->IdleSt	186	Covered	T4,T73,T84
DetectSt->StableSt	191	Covered	T4,T32,T59
IdleSt->DebounceSt	148	Covered	T4,T11,T25
StableSt->IdleSt	206	Covered	T4,T32,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T11,T25
0	1	Covered	T4,T11,T25
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T32,T59
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T11,T25
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T32,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T25,T73
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T11,T25
DetectSt	-	-	-	-	1	-	-	Covered	T4,T73,T84
DetectSt	-	-	-	-	0	1	-	Covered	T4,T32,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T32,T59
StableSt	-	-	-	-	-	-	0	Covered	T4,T32,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	193	0	0
CntIncr_A	7995523	105284	0	0
CntNoWrap_A	7995523	7319836	0	0
DetectStDropOut_A	7995523	18	0	0
DetectedOut_A	7995523	256753	0	0
DetectedPulseOut_A	7995523	58	0	0
DisabledIdleSt_A	7995523	5935014	0	0
DisabledNoDetection_A	7995523	5937510	0	0
EnterDebounceSt_A	7995523	118	0	0
EnterDetectSt_A	7995523	76	0	0
EnterStableSt_A	7995523	58	0	0
PulseIsPulse_A	7995523	58	0	0
StayInStableSt	7995523	256695	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7995523	7049	0	0
gen_low_level_sva.LowLevelEvent_A	7995523	7322528	0	0
gen_sticky_sva.StableStDropOut_A	7995523	488168	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	193	0	0
T4	1820	16	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	1	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	1	0	0
T32	0	2	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	4	0	0
T60	0	6	0	0
T61	0	2	0	0
T62	0	4	0	0
T63	492	0	0	0
T73	0	3	0	0
T74	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	105284	0	0
T4	1820	558	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	69	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	60	0	0
T32	0	98	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	48	0	0
T60	0	153	0	0
T61	0	83	0	0
T62	0	34	0	0
T63	492	0	0	0
T73	0	156	0	0
T74	0	116	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7319836	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	18	0	0
T4	1820	5	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T63	492	0	0	0
T73	0	1	0	0
T84	0	2	0	0
T116	0	1	0	0
T117	0	5	0	0
T118	0	2	0	0
T119	0	1	0	0
T120	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	256753	0	0
T4	1820	194	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	80	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	112	0	0
T60	0	183	0	0
T61	0	140	0	0
T62	0	82	0	0
T63	492	0	0	0
T111	0	705	0	0
T112	0	580	0	0
T113	0	47	0	0
T114	0	99	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	58	0	0
T4	1820	2	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	2	0	0
T60	0	3	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	492	0	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	5935014	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	5937510	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	118	0	0
T4	1820	9	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	2	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	2	0	0
T60	0	3	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	492	0	0	0
T73	0	2	0	0
T74	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	76	0	0
T4	1820	7	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	2	0	0
T60	0	3	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	492	0	0	0
T73	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	58	0	0
T4	1820	2	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	2	0	0
T60	0	3	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	492	0	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	58	0	0
T4	1820	2	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	2	0	0
T60	0	3	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	492	0	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	256695	0	0
T4	1820	192	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	79	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	110	0	0
T60	0	180	0	0
T61	0	139	0	0
T62	0	80	0	0
T63	492	0	0	0
T111	0	704	0	0
T112	0	578	0	0
T113	0	46	0	0
T114	0	98	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7049	0	0
T1	18127	35	0	0
T2	35596	33	0	0
T4	0	12	0	0
T6	5416	30	0	0
T7	9280	26	0	0
T8	696	0	0	0
T14	875	0	0	0
T15	494	7	0	0
T16	0	6	0	0
T19	719	3	0	0
T20	526	5	0	0
T21	681	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	488168	0	0
T4	1820	260	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	28	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	130	0	0
T60	0	115	0	0
T61	0	48	0	0
T62	0	147	0	0
T63	492	0	0	0
T111	0	106	0	0
T112	0	185	0	0
T113	0	56	0	0
T114	0	57	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T20,T2,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T20,T2,T15
1	1	Covered	T20,T2,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T11,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T4,T11,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T32,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T25
1	0	Covered	T20,T2,T15
1	1	Covered	T4,T11,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T32,T60
0	1	Covered	T62,T84,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T32,T60
0	1	Unreachable
1	0	Covered	T4,T32,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T11,T25
DetectSt	168	Covered	T4,T32,T60
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T4,T32,T60

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T32,T60
DebounceSt->IdleSt	163	Covered	T11,T25,T59
DetectSt->IdleSt	186	Covered	T62,T84,T85
DetectSt->StableSt	191	Covered	T4,T32,T60
IdleSt->DebounceSt	148	Covered	T4,T11,T25
StableSt->IdleSt	206	Covered	T4,T32,T60

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T11,T25
0	1	Covered	T4,T11,T25
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T32,T60
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T11,T25
IdleSt	0	-	-	-	-	-	-	Covered	T20,T2,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T32,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T25,T59,T62
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T11,T25
DetectSt	-	-	-	-	1	-	-	Covered	T62,T84,T85
DetectSt	-	-	-	-	0	1	-	Covered	T4,T32,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T32,T60
StableSt	-	-	-	-	-	-	0	Covered	T4,T32,T60
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	186	0	0
CntIncr_A	7995523	132408	0	0
CntNoWrap_A	7995523	7319843	0	0
DetectStDropOut_A	7995523	13	0	0
DetectedOut_A	7995523	320242	0	0
DetectedPulseOut_A	7995523	50	0	0
DisabledIdleSt_A	7995523	5935014	0	0
DisabledNoDetection_A	7995523	5937510	0	0
EnterDebounceSt_A	7995523	124	0	0
EnterDetectSt_A	7995523	63	0	0
EnterStableSt_A	7995523	50	0	0
PulseIsPulse_A	7995523	50	0	0
StayInStableSt	7995523	320192	0	0
gen_high_level_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_sticky_sva.StableStDropOut_A	7995523	925044	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	186	0	0
T4	1820	6	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	1	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	1	0	0
T32	0	2	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	4	0	0
T60	0	6	0	0
T61	0	2	0	0
T62	0	9	0	0
T63	492	0	0	0
T73	0	2	0	0
T74	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	132408	0	0
T4	1820	237	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	70	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	41	0	0
T32	0	10	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	200	0	0
T60	0	54	0	0
T61	0	36	0	0
T62	0	160	0	0
T63	492	0	0	0
T73	0	54	0	0
T74	0	80166	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7319843	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	13	0	0
T40	18729	0	0	0
T62	978	4	0	0
T72	5073	0	0	0
T84	0	1	0	0
T85	0	4	0	0
T102	7866	0	0	0
T103	1099	0	0	0
T104	755	0	0	0
T105	495	0	0	0
T106	697	0	0	0
T121	0	2	0	0
T122	0	2	0	0
T123	502	0	0	0
T124	879	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	320242	0	0
T4	1820	790	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	27	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T60	0	99	0	0
T61	0	45	0	0
T63	492	0	0	0
T74	0	142563	0	0
T81	0	88	0	0
T111	0	611	0	0
T112	0	580	0	0
T113	0	67	0	0
T114	0	126	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	50	0	0
T4	1820	3	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T60	0	3	0	0
T61	0	1	0	0
T63	492	0	0	0
T74	0	2	0	0
T81	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	5935014	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	5937510	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	124	0	0
T4	1820	3	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	2	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	4	0	0
T60	0	3	0	0
T61	0	1	0	0
T62	0	5	0	0
T63	492	0	0	0
T73	0	2	0	0
T74	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	63	0	0
T4	1820	3	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T60	0	3	0	0
T61	0	1	0	0
T62	0	4	0	0
T63	492	0	0	0
T74	0	2	0	0
T81	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	50	0	0
T4	1820	3	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T60	0	3	0	0
T61	0	1	0	0
T63	492	0	0	0
T74	0	2	0	0
T81	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	50	0	0
T4	1820	3	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T60	0	3	0	0
T61	0	1	0	0
T63	492	0	0	0
T74	0	2	0	0
T81	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	320192	0	0
T4	1820	787	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	26	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T60	0	96	0	0
T61	0	44	0	0
T63	492	0	0	0
T74	0	142561	0	0
T81	0	87	0	0
T111	0	610	0	0
T112	0	578	0	0
T113	0	66	0	0
T114	0	125	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	925044	0	0
T4	1820	274	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	370	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T60	0	302	0	0
T61	0	197	0	0
T63	492	0	0	0
T74	0	162	0	0
T81	0	5245	0	0
T111	0	217	0	0
T112	0	124	0	0
T113	0	54	0	0
T114	0	37	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T11,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T4,T11,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T25,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T25
1	0	Covered	T6,T7,T20
1	1	Covered	T4,T11,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T25,T32
0	1	Covered	T60,T73,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T25,T32
0	1	Unreachable
1	0	Covered	T4,T25,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T11,T25
DetectSt	168	Covered	T4,T25,T32
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T4,T25,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T25,T32
DebounceSt->IdleSt	163	Covered	T11,T60,T75
DetectSt->IdleSt	186	Covered	T60,T73,T80
DetectSt->StableSt	191	Covered	T4,T25,T32
IdleSt->DebounceSt	148	Covered	T4,T11,T25
StableSt->IdleSt	206	Covered	T4,T25,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T11,T25
0	1	Covered	T4,T11,T25
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T25,T32
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T11,T25
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T25,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T60,T125,T126
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T11,T25
DetectSt	-	-	-	-	1	-	-	Covered	T60,T73,T80
DetectSt	-	-	-	-	0	1	-	Covered	T4,T25,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T25,T32
StableSt	-	-	-	-	-	-	0	Covered	T4,T25,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	190	0	0
CntIncr_A	7995523	122161	0	0
CntNoWrap_A	7995523	7319839	0	0
DetectStDropOut_A	7995523	17	0	0
DetectedOut_A	7995523	569936	0	0
DetectedPulseOut_A	7995523	56	0	0
DisabledIdleSt_A	7995523	5935014	0	0
DisabledNoDetection_A	7995523	5937510	0	0
EnterDebounceSt_A	7995523	118	0	0
EnterDetectSt_A	7995523	73	0	0
EnterStableSt_A	7995523	56	0	0
PulseIsPulse_A	7995523	56	0	0
StayInStableSt	7995523	569880	0	0
gen_high_event_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_high_level_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_sticky_sva.StableStDropOut_A	7995523	258620	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	190	0	0
T4	1820	6	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	1	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	2	0	0
T32	0	2	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	4	0	0
T60	0	8	0	0
T61	0	2	0	0
T62	0	4	0	0
T63	492	0	0	0
T73	0	4	0	0
T74	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	122161	0	0
T4	1820	180	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	72	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	45	0	0
T32	0	37	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	32	0	0
T60	0	135	0	0
T61	0	47	0	0
T62	0	36	0	0
T63	492	0	0	0
T73	0	102	0	0
T74	0	118	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7319839	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	17	0	0
T39	733	0	0	0
T42	720	0	0	0
T47	579	0	0	0
T60	964	2	0	0
T61	1385	0	0	0
T73	0	2	0	0
T80	0	1	0	0
T118	0	1	0	0
T122	0	1	0	0
T127	0	2	0	0
T128	0	4	0	0
T129	0	3	0	0
T130	0	1	0	0
T131	407	0	0	0
T132	422	0	0	0
T133	2245	0	0	0
T134	564	0	0	0
T135	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	569936	0	0
T4	1820	678	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	27	0	0
T32	0	111	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	67	0	0
T60	0	1	0	0
T61	0	99	0	0
T62	0	137	0	0
T63	492	0	0	0
T74	0	190	0	0
T81	0	321	0	0
T111	0	668	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	56	0	0
T4	1820	3	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	492	0	0	0
T74	0	2	0	0
T81	0	2	0	0
T111	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	5935014	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	5937510	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	118	0	0
T4	1820	3	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	2	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	2	0	0
T60	0	5	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	492	0	0	0
T73	0	2	0	0
T74	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	73	0	0
T4	1820	3	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	2	0	0
T60	0	3	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	492	0	0	0
T73	0	2	0	0
T74	0	2	0	0
T81	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	56	0	0
T4	1820	3	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	492	0	0	0
T74	0	2	0	0
T81	0	2	0	0
T111	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	56	0	0
T4	1820	3	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	492	0	0	0
T74	0	2	0	0
T81	0	2	0	0
T111	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	569880	0	0
T4	1820	675	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	26	0	0
T32	0	110	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	65	0	0
T61	0	98	0	0
T62	0	135	0	0
T63	492	0	0	0
T74	0	188	0	0
T81	0	319	0	0
T111	0	667	0	0
T112	0	175	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	258620	0	0
T4	1820	460	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T25	0	37	0	0
T32	0	262	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T59	0	205	0	0
T60	0	74	0	0
T61	0	138	0	0
T62	0	122	0	0
T63	492	0	0	0
T74	0	222618	0	0
T81	0	5162	0	0
T111	0	167	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T11,T45,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T11,T45,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T11,T45,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T6,T7,T8
1	1	Covered	T11,T45,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T45,T47
0	1	Covered	T39
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T45,T47
0	1	Covered	T83,T46,T136
1	0	Covered	T11

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T45,T47
1	-	Covered	T83,T46,T136

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T45,T39
DetectSt	168	Covered	T11,T45,T39
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T11,T45,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T45,T39
DebounceSt->IdleSt	163	Covered	T137,T75,T95
DetectSt->IdleSt	186	Covered	T39
DetectSt->StableSt	191	Covered	T11,T45,T47
IdleSt->DebounceSt	148	Covered	T11,T45,T39
StableSt->IdleSt	206	Covered	T11,T40,T83

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T45,T39
0	1	Covered	T11,T45,T39
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T45,T39
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T45,T39
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T45,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T137,T95
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T45,T39
DetectSt	-	-	-	-	1	-	-	Covered	T39
DetectSt	-	-	-	-	0	1	-	Covered	T11,T45,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T83,T46
StableSt	-	-	-	-	-	-	0	Covered	T11,T45,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	65	0	0
CntIncr_A	7995523	60643	0	0
CntNoWrap_A	7995523	7319964	0	0
DetectStDropOut_A	7995523	1	0	0
DetectedOut_A	7995523	119668	0	0
DetectedPulseOut_A	7995523	30	0	0
DisabledIdleSt_A	7995523	7039721	0	0
DisabledNoDetection_A	7995523	7042166	0	0
EnterDebounceSt_A	7995523	35	0	0
EnterDetectSt_A	7995523	31	0	0
EnterStableSt_A	7995523	30	0	0
PulseIsPulse_A	7995523	30	0	0
StayInStableSt	7995523	119622	0	0
gen_high_level_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	65	0	0
T11	7058	2	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T42	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	4	0	0
T86	402	0	0	0
T104	0	2	0	0
T138	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	60643	0	0
T11	7058	20	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	78	0	0
T40	0	70	0	0
T42	0	89	0	0
T45	0	64	0	0
T46	0	46	0	0
T47	0	61	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	90	0	0
T86	402	0	0	0
T104	0	55	0	0
T138	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7319964	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1	0	0
T39	733	1	0	0
T42	720	0	0	0
T47	579	0	0	0
T61	1385	0	0	0
T131	407	0	0	0
T132	422	0	0	0
T133	2245	0	0	0
T134	564	0	0	0
T135	402	0	0	0
T139	19603	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	119668	0	0
T11	7058	16	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	139	0	0
T42	0	51	0	0
T45	0	153	0	0
T46	0	44	0	0
T47	0	39	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	107	0	0
T86	402	0	0	0
T104	0	38	0	0
T138	0	38	0	0
T140	0	117	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	30	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	2	0	0
T86	402	0	0	0
T104	0	1	0	0
T138	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7039721	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7042166	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	35	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	2	0	0
T86	402	0	0	0
T104	0	1	0	0
T138	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	31	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	2	0	0
T86	402	0	0	0
T104	0	1	0	0
T138	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	30	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	2	0	0
T86	402	0	0	0
T104	0	1	0	0
T138	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	30	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	2	0	0
T86	402	0	0	0
T104	0	1	0	0
T138	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	119622	0	0
T11	7058	15	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	135	0	0
T42	0	49	0	0
T45	0	151	0	0
T46	0	43	0	0
T47	0	37	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	105	0	0
T86	402	0	0	0
T104	0	36	0	0
T138	0	36	0	0
T140	0	115	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	13	0	0
T43	3449	0	0	0
T46	0	1	0	0
T83	850	2	0	0
T85	0	2	0	0
T111	1359	0	0	0
T112	2110	0	0	0
T121	0	1	0	0
T136	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	15665	0	0	0
T147	525	0	0	0
T148	755	0	0	0
T149	661	0	0	0
T150	515	0	0	0
T151	672	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T11,T12,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T11,T12,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T11,T12,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T41
1	0	Covered	T7,T20,T1
1	1	Covered	T11,T12,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T41
0	1	Covered	T152
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T41
0	1	Covered	T39,T40,T104
1	0	Covered	T11

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T41
1	-	Covered	T39,T40,T104

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T12,T41
DetectSt	168	Covered	T11,T12,T41
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T11,T12,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T12,T41
DebounceSt->IdleSt	163	Covered	T75,T153
DetectSt->IdleSt	186	Covered	T152
DetectSt->StableSt	191	Covered	T11,T12,T41
IdleSt->DebounceSt	148	Covered	T11,T12,T41
StableSt->IdleSt	206	Covered	T11,T41,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T12,T41
0	1	Covered	T11,T12,T41
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T41
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T12,T41
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T12,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T153
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T12,T41
DetectSt	-	-	-	-	1	-	-	Covered	T152
DetectSt	-	-	-	-	0	1	-	Covered	T11,T12,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T39,T40
StableSt	-	-	-	-	-	-	0	Covered	T11,T12,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	82	0	0
CntIncr_A	7995523	29814	0	0
CntNoWrap_A	7995523	7319947	0	0
DetectStDropOut_A	7995523	1	0	0
DetectedOut_A	7995523	3735	0	0
DetectedPulseOut_A	7995523	39	0	0
DisabledIdleSt_A	7995523	7239169	0	0
DisabledNoDetection_A	7995523	7241631	0	0
EnterDebounceSt_A	7995523	42	0	0
EnterDetectSt_A	7995523	40	0	0
EnterStableSt_A	7995523	39	0	0
PulseIsPulse_A	7995523	39	0	0
StayInStableSt	7995523	3673	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7995523	2691	0	0
gen_low_level_sva.LowLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	82	0	0
T11	7058	2	0	0
T12	942	2	0	0
T13	19514	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T41	0	2	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	6	0	0
T86	402	0	0	0
T104	0	2	0	0
T137	0	4	0	0
T154	0	2	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	29814	0	0
T11	7058	20	0	0
T12	942	88	0	0
T13	19514	0	0	0
T39	0	156	0	0
T40	0	24	0	0
T41	0	51	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	135	0	0
T86	402	0	0	0
T104	0	55	0	0
T137	0	190	0	0
T154	0	27519	0	0
T155	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7319947	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1	0	0
T98	24399	0	0	0
T152	48534	1	0	0
T156	501	0	0	0
T157	776	0	0	0
T158	503	0	0	0
T159	402	0	0	0
T160	446	0	0	0
T161	436	0	0	0
T162	23538	0	0	0
T163	21061	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	3735	0	0
T11	7058	15	0	0
T12	942	268	0	0
T13	19514	0	0	0
T39	0	82	0	0
T40	0	10	0	0
T41	0	113	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	105	0	0
T86	402	0	0	0
T104	0	100	0	0
T137	0	241	0	0
T154	0	38	0	0
T155	0	158	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	39	0	0
T11	7058	1	0	0
T12	942	1	0	0
T13	19514	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	3	0	0
T86	402	0	0	0
T104	0	1	0	0
T137	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7239169	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7241631	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	42	0	0
T11	7058	1	0	0
T12	942	1	0	0
T13	19514	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	3	0	0
T86	402	0	0	0
T104	0	1	0	0
T137	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	40	0	0
T11	7058	1	0	0
T12	942	1	0	0
T13	19514	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	3	0	0
T86	402	0	0	0
T104	0	1	0	0
T137	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	39	0	0
T11	7058	1	0	0
T12	942	1	0	0
T13	19514	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	3	0	0
T86	402	0	0	0
T104	0	1	0	0
T137	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	39	0	0
T11	7058	1	0	0
T12	942	1	0	0
T13	19514	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	3	0	0
T86	402	0	0	0
T104	0	1	0	0
T137	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	3673	0	0
T11	7058	14	0	0
T12	942	266	0	0
T13	19514	0	0	0
T39	0	79	0	0
T40	0	9	0	0
T41	0	111	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	101	0	0
T86	402	0	0	0
T104	0	99	0	0
T137	0	238	0	0
T154	0	36	0	0
T155	0	156	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	2691	0	0
T1	18127	0	0	0
T2	35596	12	0	0
T3	503	1	0	0
T4	1820	0	0	0
T5	0	1	0	0
T9	22687	0	0	0
T14	875	0	0	0
T15	494	5	0	0
T16	504	3	0	0
T17	0	4	0	0
T18	0	3	0	0
T20	526	6	0	0
T21	681	0	0	0
T55	0	6	0	0
T56	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	15	0	0
T39	733	1	0	0
T40	0	1	0	0
T42	720	0	0	0
T47	579	0	0	0
T61	1385	0	0	0
T82	0	1	0	0
T83	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T104	0	1	0	0
T131	407	0	0	0
T132	422	0	0	0
T133	2245	0	0	0
T134	564	0	0	0
T135	402	0	0	0
T137	0	1	0	0
T139	19603	0	0	0
T152	0	1	0	0
T164	0	1	0	0