Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	90.21	93.48	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	97.61	97.83	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.61	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.21	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
91.56	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T1
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T7,T1,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T7,T1,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T7,T1,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T2
1	0	Covered	T6,T7,T1
1	1	Covered	T7,T1,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T2
0	1	Covered	T11,T48,T33
1	0	Covered	T11,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T2
0	1	Covered	T1,T2,T9
1	0	Covered	T11,T75,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T1,T2
1	-	Covered	T1,T2,T9

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.61	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.21	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T19,T21,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T19,T21,T3

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T19,T21,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T19,T21,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T3
0	1	Covered	T40,T77,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T3
0	1	Covered	T19,T21,T48
1	0	Covered	T11

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T21,T3
1	-	Covered	T19,T21,T48

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T1
1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T7,T1,T9
1	1	Covered	T6,T7,T1

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T6,T11,T72
1	0	Covered	T7,T9,T11

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T9
0	1	Covered	T7,T1,T9
1	0	Covered	T11,T79,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T1,T9
1	-	Covered	T7,T1,T9

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T11,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T11,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T25,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T25
1	0	Covered	T6,T7,T20
1	1	Covered	T4,T11,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T25,T32
0	1	Covered	T60,T73,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T25,T32
0	1	Unreachable
1	0	Covered	T4,T25,T32

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
91.56	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T5,T11,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T5,T11,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T11,T45,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T11
1	0	Covered	T6,T7,T8
1	1	Covered	T5,T11,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T45,T39
0	1	Covered	T39,T81,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T45,T39
0	1	Covered	T45,T40,T83
1	0	Covered	T11

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T45,T39
1	-	Covered	T45,T40,T83

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T20,T2,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T20,T2,T15
1	1	Covered	T20,T2,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T11,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T11,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T32,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T25
1	0	Covered	T20,T2,T15
1	1	Covered	T4,T11,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T32,T60
0	1	Covered	T62,T84,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T32,T60
0	1	Unreachable
1	0	Covered	T4,T32,T60

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T19
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T19
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T11,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T11,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T4,T32,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T25
1	0	Covered	T6,T7,T19
1	1	Covered	T4,T11,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T32,T59
0	1	Covered	T4,T73,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T32,T59
0	1	Unreachable
1	0	Covered	T4,T32,T59

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T21,T3
DetectSt	168	Covered	T19,T21,T3
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T19,T21,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T21,T3
DebounceSt->IdleSt	163	Covered	T11,T48,T58
DetectSt->IdleSt	186	Covered	T4,T32,T60
DetectSt->StableSt	191	Covered	T19,T21,T3
IdleSt->DebounceSt	148	Covered	T19,T21,T3
StableSt->IdleSt	206	Covered	T19,T21,T11

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.21	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
91.56	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T3
0	1	Covered	T19,T21,T3
0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T21,T3
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T19,T21,T3
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T21,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T48,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T21,T3
DetectSt	-	-	-	-	1	-	-	Covered	T4,T39,T62
DetectSt	-	-	-	-	0	1	-	Covered	T19,T21,T3
DetectSt	-	-	-	-	0	0	-	Covered	T7,T1,T2
StableSt	-	-	-	-	-	-	1	Covered	T19,T21,T11
StableSt	-	-	-	-	-	-	0	Covered	T19,T21,T3
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T1
0	1	Covered	T6,T7,T1
0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T1
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T1
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T1
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T60,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T1
DetectSt	-	-	-	-	1	-	-	Covered	T6,T11,T37
DetectSt	-	-	-	-	0	1	-	Covered	T7,T1,T4
DetectSt	-	-	-	-	0	0	-	Covered	T6,T7,T1
StableSt	-	-	-	-	-	-	1	Covered	T7,T1,T4
StableSt	-	-	-	-	-	-	0	Covered	T7,T1,T4
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	207883598	18401	0	0
CntIncr_A	207883598	2307834	0	0
CntNoWrap_A	207883598	190302353	0	0
DetectStDropOut_A	207883598	2025	0	0
DetectedOut_A	207883598	2294324	0	0
DetectedPulseOut_A	207883598	5984	0	0
DisabledIdleSt_A	207883598	177557051	0	0
DisabledNoDetection_A	207883598	177617206	0	0
EnterDebounceSt_A	207883598	9496	0	0
EnterDetectSt_A	207883598	8933	0	0
EnterStableSt_A	207883598	5984	0	0
PulseIsPulse_A	207883598	5984	0	0
StayInStableSt	207883598	2287424	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	71959707	52690	0	0
gen_high_event_sva.HighLevelEvent_A	39977615	36612640	0	0
gen_high_level_sva.HighLevelEvent_A	135923891	124482976	0	0
gen_low_level_sva.LowLevelEvent_A	71959707	65902752	0	0
gen_not_sticky_sva.StableStDropOut_A	183897029	4838	0	0
gen_sticky_sva.StableStDropOut_A	23986569	1671832	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207883598	18401	0	0
T1	145016	52	0	0
T2	320364	5	0	0
T3	2515	0	0	0
T4	5460	0	0	0
T5	678	0	0	0
T6	21664	60	0	0
T7	55680	61	0	0
T8	4176	0	0	0
T9	45374	52	0	0
T10	0	2	0	0
T11	7058	24	0	0
T12	942	0	0	0
T13	0	15	0	0
T14	7875	0	0	0
T15	4446	0	0	0
T16	1512	0	0	0
T17	988	0	0	0
T18	862	0	0	0
T19	5033	2	0	0
T20	3682	0	0	0
T21	4767	2	0	0
T33	0	2	0	0
T34	0	48	0	0
T35	0	16	0	0
T36	0	50	0	0
T37	0	26	0	0
T38	0	2	0	0
T48	7160	31	0	0
T49	0	4	0	0
T51	0	2	0	0
T52	0	4	0	0
T53	0	2	0	0
T86	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207883598	2307834	0	0
T1	145016	2062	0	0
T2	320364	251	0	0
T3	2515	0	0	0
T4	5460	0	0	0
T5	678	0	0	0
T6	21664	1680	0	0
T7	55680	1707	0	0
T8	4176	0	0	0
T9	45374	1483	0	0
T10	0	126	0	0
T11	7058	649	0	0
T12	942	0	0	0
T13	0	677	0	0
T14	7875	0	0	0
T15	4446	0	0	0
T16	1512	0	0	0
T17	988	0	0	0
T18	862	0	0	0
T19	5033	85	0	0
T20	3682	0	0	0
T21	4767	67	0	0
T33	0	104	0	0
T34	0	1272	0	0
T35	0	784	0	0
T36	0	1025	0	0
T37	0	806	0	0
T38	0	98	0	0
T48	7160	1543	0	0
T49	0	57	0	0
T51	0	91	0	0
T52	0	99	0	0
T53	0	68	0	0
T86	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207883598	190302353	0	0
T1	471302	459932	0	0
T2	925496	860418	0	0
T6	140816	130206	0	0
T7	241280	230603	0	0
T8	18096	7670	0	0
T14	22750	12324	0	0
T15	12844	2418	0	0
T19	18694	8266	0	0
T20	13676	3250	0	0
T21	17706	7278	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207883598	2025	0	0
T6	5416	30	0	0
T12	942	0	0	0
T13	19514	0	0	0
T35	0	8	0	0
T40	18729	1	0	0
T48	7160	14	0	0
T49	665	0	0	0
T50	28661	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T72	5073	10	0	0
T78	0	1	0	0
T86	402	0	0	0
T87	0	10	0	0
T88	0	11	0	0
T89	0	5	0	0
T90	0	12	0	0
T91	0	6	0	0
T92	0	26	0	0
T93	0	3	0	0
T94	0	26	0	0
T95	0	20	0	0
T96	0	6	0	0
T97	0	2	0	0
T98	0	7	0	0
T99	0	8	0	0
T100	0	6	0	0
T101	0	7	0	0
T102	7866	0	0	0
T103	1099	0	0	0
T104	755	0	0	0
T105	495	0	0	0
T106	697	0	0	0
T107	418	0	0	0
T108	25635	0	0	0
T109	664	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207883598	2294324	0	0
T1	145016	2202	0	0
T2	320364	37	0	0
T3	4527	0	0	0
T4	7280	0	0	0
T5	678	0	0	0
T7	46400	1585	0	0
T8	3480	0	0	0
T9	68061	3024	0	0
T10	0	10	0	0
T11	7058	462	0	0
T12	942	0	0	0
T13	0	457	0	0
T14	7875	0	0	0
T15	4446	0	0	0
T16	2016	0	0	0
T17	1482	0	0	0
T18	1293	0	0	0
T19	4314	10	0	0
T20	3156	0	0	0
T21	4086	7	0	0
T33	0	32	0	0
T34	0	2378	0	0
T36	0	1004	0	0
T37	0	1228	0	0
T38	0	6	0	0
T48	7160	10	0	0
T49	0	9	0	0
T51	0	6	0	0
T52	0	5	0	0
T53	0	12	0	0
T54	0	529	0	0
T68	504	0	0	0
T86	402	0	0	0
T110	0	21	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207883598	5984	0	0
T1	145016	26	0	0
T2	320364	2	0	0
T3	4527	0	0	0
T4	7280	0	0	0
T5	678	0	0	0
T7	46400	30	0	0
T8	3480	0	0	0
T9	68061	26	0	0
T10	0	1	0	0
T11	7058	6	0	0
T12	942	0	0	0
T13	0	7	0	0
T14	7875	0	0	0
T15	4446	0	0	0
T16	2016	0	0	0
T17	1482	0	0	0
T18	1293	0	0	0
T19	4314	1	0	0
T20	3156	0	0	0
T21	4086	1	0	0
T33	0	1	0	0
T34	0	26	0	0
T36	0	26	0	0
T37	0	13	0	0
T38	0	1	0	0
T48	7160	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	8	0	0
T68	504	0	0	0
T86	402	0	0	0
T110	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207883598	177557051	0	0
T1	471302	430148	0	0
T2	925496	836797	0	0
T6	140816	118386	0	0
T7	241280	209500	0	0
T8	18096	7670	0	0
T14	22750	12324	0	0
T15	12844	2418	0	0
T19	18694	8137	0	0
T20	13676	3250	0	0
T21	17706	7161	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207883598	177617206	0	0
T1	471302	430262	0	0
T2	925496	837165	0	0
T6	140816	118408	0	0
T7	241280	209544	0	0
T8	18096	7696	0	0
T14	22750	12350	0	0
T15	12844	2444	0	0
T19	18694	8163	0	0
T20	13676	3276	0	0
T21	17706	7187	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207883598	9496	0	0
T1	145016	26	0	0
T2	320364	3	0	0
T3	2515	0	0	0
T4	5460	0	0	0
T5	678	0	0	0
T6	21664	30	0	0
T7	55680	31	0	0
T8	4176	0	0	0
T9	45374	26	0	0
T10	0	1	0	0
T11	7058	15	0	0
T12	942	0	0	0
T13	0	8	0	0
T14	7875	0	0	0
T15	4446	0	0	0
T16	1512	0	0	0
T17	988	0	0	0
T18	862	0	0	0
T19	5033	1	0	0
T20	3682	0	0	0
T21	4767	1	0	0
T33	0	1	0	0
T34	0	24	0	0
T35	0	8	0	0
T36	0	25	0	0
T37	0	13	0	0
T38	0	1	0	0
T48	7160	16	0	0
T49	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T86	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207883598	8933	0	0
T1	145016	26	0	0
T2	320364	2	0	0
T3	2515	0	0	0
T4	5460	0	0	0
T5	678	0	0	0
T6	21664	30	0	0
T7	55680	30	0	0
T8	4176	0	0	0
T9	45374	26	0	0
T10	0	1	0	0
T11	7058	9	0	0
T12	942	0	0	0
T13	0	7	0	0
T14	7875	0	0	0
T15	4446	0	0	0
T16	1512	0	0	0
T17	988	0	0	0
T18	862	0	0	0
T19	5033	1	0	0
T20	3682	0	0	0
T21	4767	1	0	0
T33	0	1	0	0
T34	0	24	0	0
T35	0	8	0	0
T36	0	25	0	0
T38	0	1	0	0
T48	7160	15	0	0
T49	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T86	402	0	0	0
T110	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207883598	5984	0	0
T1	145016	26	0	0
T2	320364	2	0	0
T3	4527	0	0	0
T4	7280	0	0	0
T5	678	0	0	0
T7	46400	30	0	0
T8	3480	0	0	0
T9	68061	26	0	0
T10	0	1	0	0
T11	7058	6	0	0
T12	942	0	0	0
T13	0	7	0	0
T14	7875	0	0	0
T15	4446	0	0	0
T16	2016	0	0	0
T17	1482	0	0	0
T18	1293	0	0	0
T19	4314	1	0	0
T20	3156	0	0	0
T21	4086	1	0	0
T33	0	1	0	0
T34	0	26	0	0
T36	0	26	0	0
T37	0	13	0	0
T38	0	1	0	0
T48	7160	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	8	0	0
T68	504	0	0	0
T86	402	0	0	0
T110	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207883598	5984	0	0
T1	145016	26	0	0
T2	320364	2	0	0
T3	4527	0	0	0
T4	7280	0	0	0
T5	678	0	0	0
T7	46400	30	0	0
T8	3480	0	0	0
T9	68061	26	0	0
T10	0	1	0	0
T11	7058	6	0	0
T12	942	0	0	0
T13	0	7	0	0
T14	7875	0	0	0
T15	4446	0	0	0
T16	2016	0	0	0
T17	1482	0	0	0
T18	1293	0	0	0
T19	4314	1	0	0
T20	3156	0	0	0
T21	4086	1	0	0
T33	0	1	0	0
T34	0	26	0	0
T36	0	26	0	0
T37	0	13	0	0
T38	0	1	0	0
T48	7160	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	8	0	0
T68	504	0	0	0
T86	402	0	0	0
T110	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	207883598	2287424	0	0
T1	145016	2174	0	0
T2	320364	35	0	0
T3	4527	0	0	0
T4	7280	0	0	0
T5	678	0	0	0
T7	46400	1553	0	0
T8	3480	0	0	0
T9	68061	2985	0	0
T10	0	9	0	0
T11	7058	456	0	0
T12	942	0	0	0
T13	0	450	0	0
T14	7875	0	0	0
T15	4446	0	0	0
T16	2016	0	0	0
T17	1482	0	0	0
T18	1293	0	0	0
T19	4314	9	0	0
T20	3156	0	0	0
T21	4086	6	0	0
T33	0	31	0	0
T34	0	2348	0	0
T36	0	976	0	0
T37	0	1212	0	0
T38	0	5	0	0
T48	7160	9	0	0
T49	0	7	0	0
T51	0	5	0	0
T52	0	3	0	0
T53	0	11	0	0
T54	0	519	0	0
T68	504	0	0	0
T86	402	0	0	0
T110	0	19	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71959707	52690	0	0
T1	163143	222	0	0
T2	320364	300	0	0
T3	1006	3	0	0
T4	1820	48	0	0
T5	0	2	0	0
T6	37912	192	0	0
T7	64960	181	0	0
T8	5568	6	0	0
T9	22687	105	0	0
T14	7875	3	0	0
T15	4446	60	0	0
T16	1008	42	0	0
T17	0	32	0	0
T18	0	10	0	0
T19	5752	9	0	0
T20	4734	47	0	0
T21	6129	9	0	0
T55	0	6	0	0
T56	0	3	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39977615	36612640	0	0
T1	90635	88510	0	0
T2	177980	165555	0	0
T6	27080	25080	0	0
T7	46400	44390	0	0
T8	3480	1480	0	0
T14	4375	2375	0	0
T15	2470	470	0	0
T19	3595	1595	0	0
T20	2630	630	0	0
T21	3405	1405	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135923891	124482976	0	0
T1	308159	300934	0	0
T2	605132	562887	0	0
T6	92072	85272	0	0
T7	157760	150926	0	0
T8	11832	5032	0	0
T14	14875	8075	0	0
T15	8398	1598	0	0
T19	12223	5423	0	0
T20	8942	2142	0	0
T21	11577	4777	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71959707	65902752	0	0
T1	163143	159318	0	0
T2	320364	297999	0	0
T6	48744	45144	0	0
T7	83520	79902	0	0
T8	6264	2664	0	0
T14	7875	4275	0	0
T15	4446	846	0	0
T19	6471	2871	0	0
T20	4734	1134	0	0
T21	6129	2529	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183897029	4838	0	0
T1	90635	24	0	0
T2	249172	2	0	0
T3	3521	0	0	0
T4	9100	0	0	0
T5	1356	0	0	0
T7	18560	28	0	0
T8	1392	0	0	0
T9	90748	13	0	0
T10	0	1	0	0
T11	0	4	0	0
T12	942	0	0	0
T13	19514	7	0	0
T14	6125	0	0	0
T15	3458	0	0	0
T16	2520	0	0	0
T17	1976	0	0	0
T18	1724	0	0	0
T19	2157	1	0	0
T20	1578	0	0	0
T21	2043	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	22	0	0
T37	0	12	0	0
T38	0	1	0	0
T48	7160	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	8	0	0
T68	504	0	0	0
T86	402	0	0	0
T110	0	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23986569	1671832	0	0
T4	5460	994	0	0
T5	2034	0	0	0
T9	68061	0	0	0
T10	42372	0	0	0
T17	1482	0	0	0
T18	1293	0	0	0
T25	0	37	0	0
T32	0	660	0	0
T55	1506	0	0	0
T56	1329	0	0	0
T57	1524	0	0	0
T59	0	335	0	0
T60	0	491	0	0
T61	0	383	0	0
T62	0	269	0	0
T63	1476	0	0	0
T74	0	222780	0	0
T81	0	10407	0	0
T111	0	490	0	0
T112	0	309	0	0
T113	0	110	0	0
T114	0	94	0	0