Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T11,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T11,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T11,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T11
1	0	Covered	T6,T7,T8
1	1	Covered	T11,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T39,T40
0	1	Covered	T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T39,T40
0	1	Covered	T46,T138,T137
1	0	Covered	T11

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T39,T40
1	-	Covered	T46,T138,T137

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T39,T40
DetectSt	168	Covered	T11,T39,T40
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T11,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T39,T40
DebounceSt->IdleSt	163	Covered	T75,T82
DetectSt->IdleSt	186	Covered	T82
DetectSt->StableSt	191	Covered	T11,T39,T40
IdleSt->DebounceSt	148	Covered	T11,T39,T40
StableSt->IdleSt	206	Covered	T11,T40,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T39,T40
0	1	Covered	T11,T39,T40
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T39,T40
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T82
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T82
DetectSt	-	-	-	-	0	1	-	Covered	T11,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T46,T138
StableSt	-	-	-	-	-	-	0	Covered	T11,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	64	0	0
CntIncr_A	7995523	1831	0	0
CntNoWrap_A	7995523	7319965	0	0
DetectStDropOut_A	7995523	1	0	0
DetectedOut_A	7995523	2252	0	0
DetectedPulseOut_A	7995523	30	0	0
DisabledIdleSt_A	7995523	7208556	0	0
DisabledNoDetection_A	7995523	7211006	0	0
EnterDebounceSt_A	7995523	33	0	0
EnterDetectSt_A	7995523	31	0	0
EnterStableSt_A	7995523	30	0	0
PulseIsPulse_A	7995523	30	0	0
StayInStableSt	7995523	2206	0	0
gen_high_level_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	64	0	0
T11	7058	2	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T46	0	2	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T75	0	1	0	0
T77	0	2	0	0
T82	0	3	0	0
T86	402	0	0	0
T95	0	4	0	0
T137	0	2	0	0
T138	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1831	0	0
T11	7058	20	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	78	0	0
T40	0	24	0	0
T46	0	46	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T75	0	22	0	0
T77	0	42	0	0
T82	0	170	0	0
T86	402	0	0	0
T95	0	73	0	0
T137	0	95	0	0
T138	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7319965	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1	0	0
T82	1096	1	0	0
T165	488	0	0	0
T166	496	0	0	0
T167	524	0	0	0
T168	1340	0	0	0
T169	9002	0	0	0
T170	501	0	0	0
T171	11085	0	0	0
T172	2928	0	0	0
T173	167091	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	2252	0	0
T11	7058	15	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	121	0	0
T40	0	40	0	0
T46	0	84	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T77	0	45	0	0
T86	402	0	0	0
T95	0	134	0	0
T137	0	43	0	0
T138	0	43	0	0
T174	0	43	0	0
T175	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	30	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T46	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T77	0	1	0	0
T86	402	0	0	0
T95	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7208556	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7211006	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	33	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T46	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T75	0	1	0	0
T77	0	1	0	0
T82	0	2	0	0
T86	402	0	0	0
T95	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	31	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T46	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T77	0	1	0	0
T82	0	1	0	0
T86	402	0	0	0
T95	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	30	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T46	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T77	0	1	0	0
T86	402	0	0	0
T95	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	30	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T46	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T77	0	1	0	0
T86	402	0	0	0
T95	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	2206	0	0
T11	7058	14	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	119	0	0
T40	0	38	0	0
T46	0	83	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T77	0	43	0	0
T86	402	0	0	0
T95	0	132	0	0
T137	0	42	0	0
T138	0	42	0	0
T174	0	41	0	0
T175	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	13	0	0
T46	875	1	0	0
T79	42666	0	0	0
T95	0	2	0	0
T137	0	1	0	0
T138	1129	1	0	0
T143	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	10064	0	0	0
T182	704	0	0	0
T183	643	0	0	0
T184	502	0	0	0
T185	406	0	0	0
T186	503	0	0	0
T187	428	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T3,T5,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T3,T5,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T3,T5,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T11
1	0	Covered	T7,T8,T20
1	1	Covered	T3,T5,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T11
0	1	Covered	T77,T188
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T11
0	1	Covered	T38,T39,T104
1	0	Covered	T11

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T5,T11
1	-	Covered	T38,T39,T104

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T5,T11
DetectSt	168	Covered	T3,T5,T11
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T3,T5,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T5,T11
DebounceSt->IdleSt	163	Covered	T81,T137,T75
DetectSt->IdleSt	186	Covered	T77,T188
DetectSt->StableSt	191	Covered	T3,T5,T11
IdleSt->DebounceSt	148	Covered	T3,T5,T11
StableSt->IdleSt	206	Covered	T11,T38,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T5,T11
0	1	Covered	T3,T5,T11
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T11
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T5,T11
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T5,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T81,T137,T189
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T5,T11
DetectSt	-	-	-	-	1	-	-	Covered	T77,T188
DetectSt	-	-	-	-	0	1	-	Covered	T3,T5,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T38,T39
StableSt	-	-	-	-	-	-	0	Covered	T3,T5,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	141	0	0
CntIncr_A	7995523	172645	0	0
CntNoWrap_A	7995523	7319888	0	0
DetectStDropOut_A	7995523	2	0	0
DetectedOut_A	7995523	248352	0	0
DetectedPulseOut_A	7995523	64	0	0
DisabledIdleSt_A	7995523	6839178	0	0
DisabledNoDetection_A	7995523	6841624	0	0
EnterDebounceSt_A	7995523	76	0	0
EnterDetectSt_A	7995523	66	0	0
EnterStableSt_A	7995523	64	0	0
PulseIsPulse_A	7995523	64	0	0
StayInStableSt	7995523	248260	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7995523	3030	0	0
gen_low_level_sva.LowLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	141	0	0
T3	503	2	0	0
T4	1820	0	0	0
T5	678	2	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T38	0	4	0	0
T39	0	2	0	0
T47	0	2	0	0
T55	502	0	0	0
T56	443	0	0	0
T81	0	4	0	0
T83	0	4	0	0
T104	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	172645	0	0
T3	503	17	0	0
T4	1820	0	0	0
T5	678	83	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	20	0	0
T12	0	88	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T38	0	120	0	0
T39	0	78	0	0
T47	0	61	0	0
T55	502	0	0	0
T56	443	0	0	0
T81	0	207	0	0
T83	0	90	0	0
T104	0	110	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7319888	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	2	0	0
T77	539	1	0	0
T92	5169	0	0	0
T188	0	1	0	0
T190	444	0	0	0
T191	661	0	0	0
T192	408	0	0	0
T193	508	0	0	0
T194	461	0	0	0
T195	1714	0	0	0
T196	826	0	0	0
T197	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	248352	0	0
T3	503	44	0	0
T4	1820	0	0	0
T5	678	42	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	14	0	0
T12	0	269	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T38	0	310	0	0
T39	0	45	0	0
T47	0	109	0	0
T55	502	0	0	0
T56	443	0	0	0
T81	0	1	0	0
T83	0	85	0	0
T104	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	64	0	0
T3	503	1	0	0
T4	1820	0	0	0
T5	678	1	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T47	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T81	0	1	0	0
T83	0	2	0	0
T104	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6839178	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6841624	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	76	0	0
T3	503	1	0	0
T4	1820	0	0	0
T5	678	1	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T47	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T81	0	3	0	0
T83	0	2	0	0
T104	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	66	0	0
T3	503	1	0	0
T4	1820	0	0	0
T5	678	1	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T47	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T81	0	1	0	0
T83	0	2	0	0
T104	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	64	0	0
T3	503	1	0	0
T4	1820	0	0	0
T5	678	1	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T47	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T81	0	1	0	0
T83	0	2	0	0
T104	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	64	0	0
T3	503	1	0	0
T4	1820	0	0	0
T5	678	1	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T47	0	1	0	0
T55	502	0	0	0
T56	443	0	0	0
T81	0	1	0	0
T83	0	2	0	0
T104	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	248260	0	0
T3	503	42	0	0
T4	1820	0	0	0
T5	678	40	0	0
T9	22687	0	0	0
T10	14124	0	0	0
T11	0	13	0	0
T12	0	267	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T38	0	308	0	0
T39	0	44	0	0
T43	0	44	0	0
T47	0	107	0	0
T55	502	0	0	0
T56	443	0	0	0
T83	0	82	0	0
T104	0	76	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	3030	0	0
T1	18127	0	0	0
T2	35596	16	0	0
T3	503	1	0	0
T5	0	1	0	0
T8	696	6	0	0
T14	875	3	0	0
T15	494	6	0	0
T16	504	4	0	0
T17	0	4	0	0
T18	0	2	0	0
T19	719	0	0	0
T20	526	6	0	0
T21	681	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	35	0	0
T34	16479	0	0	0
T38	16980	2	0	0
T39	0	1	0	0
T41	11693	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T52	655	0	0	0
T53	38973	0	0	0
T81	0	1	0	0
T83	0	1	0	0
T95	0	1	0	0
T104	0	1	0	0
T138	0	1	0	0
T140	0	1	0	0
T198	502	0	0	0
T199	523	0	0	0
T200	523	0	0	0
T201	523	0	0	0
T202	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T20

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T20
1	1	Covered	T6,T7,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T11,T45,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T11,T45,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T11,T45,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T45
1	0	Covered	T6,T7,T20
1	1	Covered	T11,T45,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T45,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T45,T40
0	1	Covered	T45,T40,T43
1	0	Covered	T11

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T45,T40
1	-	Covered	T45,T40,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T45,T40
DetectSt	168	Covered	T11,T45,T40
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T11,T45,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T45,T40
DebounceSt->IdleSt	163	Covered	T137,T75,T96
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T45,T40
IdleSt->DebounceSt	148	Covered	T11,T45,T40
StableSt->IdleSt	206	Covered	T11,T45,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T45,T40
0	1	Covered	T11,T45,T40
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T45,T40
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T45,T40
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T45,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T137,T96,T173
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T45,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T45,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T45,T40
StableSt	-	-	-	-	-	-	0	Covered	T11,T45,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	109	0	0
CntIncr_A	7995523	313650	0	0
CntNoWrap_A	7995523	7319920	0	0
DetectStDropOut_A	7995523	0	0	0
DetectedOut_A	7995523	264463	0	0
DetectedPulseOut_A	7995523	51	0	0
DisabledIdleSt_A	7995523	6482293	0	0
DisabledNoDetection_A	7995523	6484748	0	0
EnterDebounceSt_A	7995523	58	0	0
EnterDetectSt_A	7995523	51	0	0
EnterStableSt_A	7995523	51	0	0
PulseIsPulse_A	7995523	51	0	0
StayInStableSt	7995523	264393	0	0
gen_high_level_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	109	0	0
T11	7058	2	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	6	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T75	0	1	0	0
T86	402	0	0	0
T137	0	3	0	0
T154	0	2	0	0
T203	0	4	0	0
T204	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	313650	0	0
T11	7058	20	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	94	0	0
T43	0	67	0	0
T44	0	71	0	0
T45	0	64	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T75	0	21	0	0
T86	402	0	0	0
T137	0	190	0	0
T154	0	27519	0	0
T203	0	85144	0	0
T204	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7319920	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	264463	0	0
T11	7058	15	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	92	0	0
T43	0	46	0	0
T44	0	68	0	0
T45	0	50	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T137	0	199	0	0
T154	0	41664	0	0
T173	0	45806	0	0
T203	0	116226	0	0
T204	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	51	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T137	0	1	0	0
T154	0	1	0	0
T173	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6482293	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6484748	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	58	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T75	0	1	0	0
T86	402	0	0	0
T137	0	2	0	0
T154	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	51	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T137	0	1	0	0
T154	0	1	0	0
T173	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	51	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T137	0	1	0	0
T154	0	1	0	0
T173	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	51	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T137	0	1	0	0
T154	0	1	0	0
T173	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	264393	0	0
T11	7058	14	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	88	0	0
T43	0	45	0	0
T44	0	67	0	0
T45	0	49	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T137	0	198	0	0
T154	0	41662	0	0
T173	0	45804	0	0
T203	0	116223	0	0
T204	0	44	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	31	0	0
T33	8334	0	0	0
T35	23513	0	0	0
T36	11527	0	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	764	1	0	0
T51	656	0	0	0
T69	524	0	0	0
T70	521	0	0	0
T71	2659	0	0	0
T137	0	1	0	0
T142	0	2	0	0
T152	0	1	0	0
T174	0	1	0	0
T203	0	1	0	0
T205	0	1	0	0
T206	404	0	0	0
T207	410	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T20
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T20
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T11,T40,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T11,T40,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T11,T40,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T47,T40
1	0	Covered	T6,T7,T20
1	1	Covered	T11,T40,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T40,T43
0	1	Covered	T144
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T40,T43
0	1	Covered	T137,T152,T208
1	0	Covered	T11

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T40,T43
1	-	Covered	T137,T152,T208

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T40,T43
DetectSt	168	Covered	T11,T40,T43
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T11,T40,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T40,T43
DebounceSt->IdleSt	163	Covered	T75
DetectSt->IdleSt	186	Covered	T144
DetectSt->StableSt	191	Covered	T11,T40,T43
IdleSt->DebounceSt	148	Covered	T11,T40,T43
StableSt->IdleSt	206	Covered	T11,T40,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T40,T43
0	1	Covered	T11,T40,T43
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T40,T43
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T40,T43
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T40,T43
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T40,T43
DetectSt	-	-	-	-	1	-	-	Covered	T144
DetectSt	-	-	-	-	0	1	-	Covered	T11,T40,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T137,T152
StableSt	-	-	-	-	-	-	0	Covered	T11,T40,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	67	0	0
CntIncr_A	7995523	60127	0	0
CntNoWrap_A	7995523	7319962	0	0
DetectStDropOut_A	7995523	1	0	0
DetectedOut_A	7995523	2612	0	0
DetectedPulseOut_A	7995523	32	0	0
DisabledIdleSt_A	7995523	6901808	0	0
DisabledNoDetection_A	7995523	6904260	0	0
EnterDebounceSt_A	7995523	34	0	0
EnterDetectSt_A	7995523	33	0	0
EnterStableSt_A	7995523	32	0	0
PulseIsPulse_A	7995523	32	0	0
StayInStableSt	7995523	2562	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7995523	6616	0	0
gen_low_level_sva.LowLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	67	0	0
T11	7058	2	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T75	0	1	0	0
T77	0	2	0	0
T86	402	0	0	0
T137	0	4	0	0
T138	0	2	0	0
T140	0	2	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	60127	0	0
T11	7058	20	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	46	0	0
T43	0	67	0	0
T44	0	71	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T75	0	22	0	0
T77	0	42	0	0
T86	402	0	0	0
T137	0	190	0	0
T138	0	81	0	0
T140	0	12	0	0
T152	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7319962	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1	0	0
T144	714	1	0	0
T209	1394	0	0	0
T210	2556	0	0	0
T211	949	0	0	0
T212	521	0	0	0
T213	942	0	0	0
T214	2262	0	0	0
T215	9448	0	0	0
T216	407	0	0	0
T217	5616	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	2612	0	0
T11	7058	15	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	48	0	0
T43	0	36	0	0
T44	0	129	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T77	0	44	0	0
T86	402	0	0	0
T137	0	82	0	0
T138	0	292	0	0
T140	0	60	0	0
T152	0	88	0	0
T208	0	67	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	32	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T77	0	1	0	0
T86	402	0	0	0
T137	0	2	0	0
T138	0	1	0	0
T140	0	1	0	0
T152	0	1	0	0
T208	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6901808	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6904260	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	34	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T75	0	1	0	0
T77	0	1	0	0
T86	402	0	0	0
T137	0	2	0	0
T138	0	1	0	0
T140	0	1	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	33	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T77	0	1	0	0
T86	402	0	0	0
T137	0	2	0	0
T138	0	1	0	0
T140	0	1	0	0
T152	0	1	0	0
T208	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	32	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T77	0	1	0	0
T86	402	0	0	0
T137	0	2	0	0
T138	0	1	0	0
T140	0	1	0	0
T152	0	1	0	0
T208	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	32	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T77	0	1	0	0
T86	402	0	0	0
T137	0	2	0	0
T138	0	1	0	0
T140	0	1	0	0
T152	0	1	0	0
T208	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	2562	0	0
T11	7058	14	0	0
T12	942	0	0	0
T13	19514	0	0	0
T40	0	46	0	0
T43	0	34	0	0
T44	0	127	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T77	0	42	0	0
T86	402	0	0	0
T137	0	79	0	0
T138	0	290	0	0
T140	0	58	0	0
T152	0	87	0	0
T208	0	66	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6616	0	0
T1	18127	27	0	0
T2	35596	42	0	0
T4	0	12	0	0
T6	5416	30	0	0
T7	9280	25	0	0
T8	696	0	0	0
T9	0	26	0	0
T14	875	0	0	0
T15	494	7	0	0
T16	0	5	0	0
T17	0	4	0	0
T19	719	0	0	0
T20	526	4	0	0
T21	681	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	13	0	0
T75	6555	0	0	0
T78	762	0	0	0
T137	1091	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T152	0	1	0	0
T176	0	1	0	0
T208	0	1	0	0
T213	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	426	0	0	0
T222	422	0	0	0
T223	540	0	0	0
T224	660	0	0	0
T225	405	0	0	0
T226	21564	0	0	0
T227	422	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T20

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T20
1	1	Covered	T6,T7,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T5,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T5,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T5,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T11,T12
1	0	Covered	T6,T7,T20
1	1	Covered	T5,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T11,T12
0	1	Covered	T228
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T11,T12
0	1	Covered	T12,T41,T39
1	0	Covered	T11

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T11,T12
1	-	Covered	T12,T41,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T11,T12
DetectSt	168	Covered	T5,T11,T12
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T5,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T11,T12
DebounceSt->IdleSt	163	Covered	T75,T229,T152
DetectSt->IdleSt	186	Covered	T228
DetectSt->StableSt	191	Covered	T5,T11,T12
IdleSt->DebounceSt	148	Covered	T5,T11,T12
StableSt->IdleSt	206	Covered	T11,T12,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T11,T12
0	1	Covered	T5,T11,T12
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T12
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T229,T230,T220
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T11,T12
DetectSt	-	-	-	-	1	-	-	Covered	T228
DetectSt	-	-	-	-	0	1	-	Covered	T5,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T12,T41
StableSt	-	-	-	-	-	-	0	Covered	T5,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	108	0	0
CntIncr_A	7995523	111904	0	0
CntNoWrap_A	7995523	7319921	0	0
DetectStDropOut_A	7995523	1	0	0
DetectedOut_A	7995523	66205	0	0
DetectedPulseOut_A	7995523	51	0	0
DisabledIdleSt_A	7995523	6967861	0	0
DisabledNoDetection_A	7995523	6970314	0	0
EnterDebounceSt_A	7995523	57	0	0
EnterDetectSt_A	7995523	52	0	0
EnterStableSt_A	7995523	51	0	0
PulseIsPulse_A	7995523	51	0	0
StayInStableSt	7995523	66134	0	0
gen_high_level_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	108	0	0
T5	678	2	0	0
T10	14124	0	0	0
T11	7058	2	0	0
T12	942	4	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T43	0	2	0	0
T45	0	2	0	0
T48	7160	0	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T63	492	0	0	0
T83	0	2	0	0
T86	402	0	0	0
T104	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	111904	0	0
T5	678	83	0	0
T10	14124	0	0	0
T11	7058	20	0	0
T12	942	176	0	0
T38	0	60	0	0
T39	0	78	0	0
T41	0	51	0	0
T43	0	67	0	0
T45	0	64	0	0
T48	7160	0	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T63	492	0	0	0
T83	0	45	0	0
T86	402	0	0	0
T104	0	55	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7319921	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1	0	0
T116	1171	0	0	0
T176	110395	0	0	0
T228	948	1	0	0
T231	496	0	0	0
T232	23851	0	0	0
T233	33962	0	0	0
T234	522	0	0	0
T235	10178	0	0	0
T236	522	0	0	0
T237	769	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	66205	0	0
T5	678	185	0	0
T10	14124	0	0	0
T11	7058	14	0	0
T12	942	95	0	0
T38	0	37	0	0
T39	0	45	0	0
T41	0	22	0	0
T43	0	149	0	0
T45	0	261	0	0
T48	7160	0	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T63	492	0	0	0
T83	0	63	0	0
T86	402	0	0	0
T104	0	99	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	51	0	0
T5	678	1	0	0
T10	14124	0	0	0
T11	7058	1	0	0
T12	942	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	7160	0	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T63	492	0	0	0
T83	0	1	0	0
T86	402	0	0	0
T104	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6967861	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6970314	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	57	0	0
T5	678	1	0	0
T10	14124	0	0	0
T11	7058	1	0	0
T12	942	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	7160	0	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T63	492	0	0	0
T83	0	1	0	0
T86	402	0	0	0
T104	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	52	0	0
T5	678	1	0	0
T10	14124	0	0	0
T11	7058	1	0	0
T12	942	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	7160	0	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T63	492	0	0	0
T83	0	1	0	0
T86	402	0	0	0
T104	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	51	0	0
T5	678	1	0	0
T10	14124	0	0	0
T11	7058	1	0	0
T12	942	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	7160	0	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T63	492	0	0	0
T83	0	1	0	0
T86	402	0	0	0
T104	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	51	0	0
T5	678	1	0	0
T10	14124	0	0	0
T11	7058	1	0	0
T12	942	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	7160	0	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T63	492	0	0	0
T83	0	1	0	0
T86	402	0	0	0
T104	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	66134	0	0
T5	678	183	0	0
T10	14124	0	0	0
T11	7058	13	0	0
T12	942	93	0	0
T38	0	35	0	0
T39	0	44	0	0
T41	0	21	0	0
T43	0	147	0	0
T45	0	259	0	0
T48	7160	0	0	0
T55	502	0	0	0
T56	443	0	0	0
T57	508	0	0	0
T63	492	0	0	0
T83	0	62	0	0
T86	402	0	0	0
T104	0	98	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	30	0	0
T12	942	2	0	0
T13	19514	0	0	0
T33	8334	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T45	764	0	0	0
T49	665	0	0	0
T50	28661	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T83	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T104	0	1	0	0
T138	0	1	0	0
T149	0	1	0	0
T155	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T20
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T20
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T11,T41,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T11,T41,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T11,T41,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T45,T38
1	0	Covered	T6,T7,T20
1	1	Covered	T11,T41,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T41,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T41,T39
0	1	Covered	T40,T46,T152
1	0	Covered	T11

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T41,T39
1	-	Covered	T40,T46,T152

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T41,T39
DetectSt	168	Covered	T11,T41,T39
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T11,T41,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T41,T39
DebounceSt->IdleSt	163	Covered	T75,T175,T238
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T41,T39
IdleSt->DebounceSt	148	Covered	T11,T41,T39
StableSt->IdleSt	206	Covered	T11,T41,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T41,T39
0	1	Covered	T11,T41,T39
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T41,T39
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T41,T39
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T41,T39
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T41,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T41,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T40,T46
StableSt	-	-	-	-	-	-	0	Covered	T11,T41,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	61	0	0
CntIncr_A	7995523	52206	0	0
CntNoWrap_A	7995523	7319968	0	0
DetectStDropOut_A	7995523	0	0	0
DetectedOut_A	7995523	2596	0	0
DetectedPulseOut_A	7995523	30	0	0
DisabledIdleSt_A	7995523	7173862	0	0
DisabledNoDetection_A	7995523	7176315	0	0
EnterDebounceSt_A	7995523	33	0	0
EnterDetectSt_A	7995523	30	0	0
EnterStableSt_A	7995523	30	0	0
PulseIsPulse_A	7995523	30	0	0
StayInStableSt	7995523	2549	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7995523	6419	0	0
gen_low_level_sva.LowLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	61	0	0
T11	7058	2	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T41	0	2	0	0
T46	0	2	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T75	0	1	0	0
T86	402	0	0	0
T95	0	2	0	0
T104	0	2	0	0
T138	0	2	0	0
T149	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	52206	0	0
T11	7058	20	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	78	0	0
T40	0	70	0	0
T41	0	51	0	0
T46	0	46	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T75	0	21	0	0
T86	402	0	0	0
T95	0	88	0	0
T104	0	55	0	0
T138	0	81	0	0
T149	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7319968	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	2596	0	0
T11	7058	14	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	121	0	0
T40	0	119	0	0
T41	0	38	0	0
T46	0	43	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T95	0	40	0	0
T104	0	39	0	0
T138	0	291	0	0
T149	0	44	0	0
T152	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	30	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T46	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T95	0	1	0	0
T104	0	1	0	0
T138	0	1	0	0
T149	0	1	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7173862	0	0
T1	18127	17697	0	0
T2	35596	33095	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7176315	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	33	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T46	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T75	0	1	0	0
T86	402	0	0	0
T95	0	1	0	0
T104	0	1	0	0
T138	0	1	0	0
T149	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	30	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T46	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T95	0	1	0	0
T104	0	1	0	0
T138	0	1	0	0
T149	0	1	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	30	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T46	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T95	0	1	0	0
T104	0	1	0	0
T138	0	1	0	0
T149	0	1	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	30	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T46	0	1	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T95	0	1	0	0
T104	0	1	0	0
T138	0	1	0	0
T149	0	1	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	2549	0	0
T11	7058	13	0	0
T12	942	0	0	0
T13	19514	0	0	0
T39	0	119	0	0
T40	0	116	0	0
T41	0	36	0	0
T46	0	42	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T95	0	38	0	0
T104	0	37	0	0
T138	0	289	0	0
T149	0	42	0	0
T152	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6419	0	0
T1	18127	30	0	0
T2	35596	51	0	0
T6	5416	24	0	0
T7	9280	29	0	0
T8	696	0	0	0
T9	0	30	0	0
T14	875	0	0	0
T15	494	9	0	0
T16	0	5	0	0
T17	0	6	0	0
T18	0	2	0	0
T19	719	0	0	0
T20	526	5	0	0
T21	681	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	12	0	0
T40	18729	1	0	0
T46	0	1	0	0
T72	5073	0	0	0
T85	0	2	0	0
T102	7866	0	0	0
T103	1099	0	0	0
T104	755	0	0	0
T105	495	0	0	0
T106	697	0	0	0
T107	418	0	0	0
T108	25635	0	0	0
T109	664	0	0	0
T142	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T220	0	1	0	0
T239	0	1	0	0