Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T1
1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T7,T1,T9
1	1	Covered	T6,T7,T1

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T6,T72,T87
1	0	Covered	T11,T87,T90

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T9
0	1	Covered	T7,T1,T9
1	0	Covered	T11,T75,T274

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T1,T9
1	-	Covered	T7,T1,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T1
DetectSt	168	Covered	T6,T7,T1
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T7,T1,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T1
DebounceSt->IdleSt	163	Covered	T11,T75,T275
DetectSt->IdleSt	186	Covered	T6,T11,T72
DetectSt->StableSt	191	Covered	T7,T1,T9
IdleSt->DebounceSt	148	Covered	T6,T7,T1
StableSt->IdleSt	206	Covered	T7,T1,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T1
0	1	Covered	T6,T7,T1
0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T1
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T1
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T1
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T75,T275
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T1
DetectSt	-	-	-	-	1	-	-	Covered	T6,T11,T72
DetectSt	-	-	-	-	0	1	-	Covered	T7,T1,T9
DetectSt	-	-	-	-	0	0	-	Covered	T6,T7,T1
StableSt	-	-	-	-	-	-	1	Covered	T7,T1,T9
StableSt	-	-	-	-	-	-	0	Covered	T7,T1,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	2696	0	0
CntIncr_A	7995523	91736	0	0
CntNoWrap_A	7995523	7317333	0	0
DetectStDropOut_A	7995523	352	0	0
DetectedOut_A	7995523	72523	0	0
DetectedPulseOut_A	7995523	753	0	0
DisabledIdleSt_A	7995523	6876896	0	0
DisabledNoDetection_A	7995523	6879202	0	0
EnterDebounceSt_A	7995523	1352	0	0
EnterDetectSt_A	7995523	1344	0	0
EnterStableSt_A	7995523	753	0	0
PulseIsPulse_A	7995523	753	0	0
StayInStableSt	7995523	71666	0	0
gen_high_event_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_high_level_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	643	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	2696	0	0
T1	18127	48	0	0
T2	35596	0	0	0
T6	5416	60	0	0
T7	9280	58	0	0
T8	696	0	0	0
T9	0	38	0	0
T11	0	15	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	48	0	0
T36	0	50	0	0
T37	0	26	0	0
T54	0	16	0	0
T72	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	91736	0	0
T1	18127	1848	0	0
T2	35596	0	0	0
T6	5416	1680	0	0
T7	9280	1653	0	0
T8	696	0	0	0
T9	0	1140	0	0
T11	0	382	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	1272	0	0
T36	0	1025	0	0
T37	0	806	0	0
T54	0	416	0	0
T72	0	482	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7317333	0	0
T1	18127	17649	0	0
T2	35596	33095	0	0
T6	5416	4955	0	0
T7	9280	8818	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	352	0	0
T1	18127	0	0	0
T2	35596	0	0	0
T6	5416	30	0	0
T7	9280	0	0	0
T8	696	0	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T72	0	10	0	0
T75	0	1	0	0
T87	0	10	0	0
T88	0	11	0	0
T90	0	12	0	0
T91	0	6	0	0
T92	0	26	0	0
T93	0	3	0	0
T94	0	26	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	72523	0	0
T1	18127	2097	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	1522	0	0
T8	696	0	0	0
T9	0	2489	0	0
T11	0	384	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	2307	0	0
T36	0	957	0	0
T37	0	1228	0	0
T54	0	529	0	0
T108	0	6009	0	0
T276	0	6243	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	753	0	0
T1	18127	24	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	29	0	0
T8	696	0	0	0
T9	0	19	0	0
T11	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	24	0	0
T36	0	25	0	0
T37	0	13	0	0
T54	0	8	0	0
T108	0	24	0	0
T276	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6876896	0	0
T1	18127	10926	0	0
T2	35596	33095	0	0
T6	5416	2014	0	0
T7	9280	4029	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6879202	0	0
T1	18127	10928	0	0
T2	35596	33111	0	0
T6	5416	2014	0	0
T7	9280	4029	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1352	0	0
T1	18127	24	0	0
T2	35596	0	0	0
T6	5416	30	0	0
T7	9280	29	0	0
T8	696	0	0	0
T9	0	19	0	0
T11	0	9	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	24	0	0
T36	0	25	0	0
T37	0	13	0	0
T54	0	8	0	0
T72	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1344	0	0
T1	18127	24	0	0
T2	35596	0	0	0
T6	5416	30	0	0
T7	9280	29	0	0
T8	696	0	0	0
T9	0	19	0	0
T11	0	6	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	24	0	0
T36	0	25	0	0
T37	0	13	0	0
T54	0	8	0	0
T72	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	753	0	0
T1	18127	24	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	29	0	0
T8	696	0	0	0
T9	0	19	0	0
T11	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	24	0	0
T36	0	25	0	0
T37	0	13	0	0
T54	0	8	0	0
T108	0	24	0	0
T276	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	753	0	0
T1	18127	24	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	29	0	0
T8	696	0	0	0
T9	0	19	0	0
T11	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	24	0	0
T36	0	25	0	0
T37	0	13	0	0
T54	0	8	0	0
T108	0	24	0	0
T276	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	71666	0	0
T1	18127	2071	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	1492	0	0
T8	696	0	0	0
T9	0	2463	0	0
T11	0	379	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	2279	0	0
T36	0	931	0	0
T37	0	1212	0	0
T54	0	519	0	0
T108	0	5982	0	0
T276	0	6216	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	643	0	0
T1	18127	22	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	28	0	0
T8	696	0	0	0
T9	0	12	0	0
T11	0	4	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	20	0	0
T36	0	24	0	0
T37	0	10	0	0
T54	0	6	0	0
T108	0	21	0	0
T276	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T1
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T7,T1,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T7,T1,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T7,T1,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T2
1	0	Covered	T6,T7,T1
1	1	Covered	T7,T1,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T2
0	1	Covered	T48,T35,T89
1	0	Covered	T11,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T2
0	1	Covered	T1,T2,T9
1	0	Covered	T11,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T1,T2
1	-	Covered	T1,T2,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T1,T2
DetectSt	168	Covered	T7,T1,T2
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T7,T1,T2

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T1,T2
DebounceSt->IdleSt	163	Covered	T7,T2,T11
DetectSt->IdleSt	186	Covered	T11,T48,T35
DetectSt->StableSt	191	Covered	T7,T1,T2
IdleSt->DebounceSt	148	Covered	T7,T1,T2
StableSt->IdleSt	206	Covered	T7,T1,T2

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T1,T2
0	1	Covered	T7,T1,T2
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T1,T2
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T1,T2
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T1,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T2,T13
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T1,T2
DetectSt	-	-	-	-	1	-	-	Covered	T11,T48,T35
DetectSt	-	-	-	-	0	1	-	Covered	T7,T1,T2
DetectSt	-	-	-	-	0	0	-	Covered	T7,T1,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T9
StableSt	-	-	-	-	-	-	0	Covered	T7,T1,T2
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	1097	0	0
CntIncr_A	7995523	58055	0	0
CntNoWrap_A	7995523	7318932	0	0
DetectStDropOut_A	7995523	98	0	0
DetectedOut_A	7995523	15007	0	0
DetectedPulseOut_A	7995523	397	0	0
DisabledIdleSt_A	7995523	6928372	0	0
DisabledNoDetection_A	7995523	6930043	0	0
EnterDebounceSt_A	7995523	602	0	0
EnterDetectSt_A	7995523	500	0	0
EnterStableSt_A	7995523	397	0	0
PulseIsPulse_A	7995523	397	0	0
StayInStableSt	7995523	14578	0	0
gen_high_level_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	362	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1097	0	0
T1	18127	4	0	0
T2	35596	5	0	0
T3	503	0	0	0
T7	9280	3	0	0
T8	696	0	0	0
T9	0	14	0	0
T10	0	2	0	0
T11	0	8	0	0
T13	0	11	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	2	0	0
T35	0	16	0	0
T48	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	58055	0	0
T1	18127	214	0	0
T2	35596	251	0	0
T3	503	0	0	0
T7	9280	54	0	0
T8	696	0	0	0
T9	0	343	0	0
T10	0	126	0	0
T11	0	239	0	0
T13	0	622	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	104	0	0
T35	0	784	0	0
T48	0	1459	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7318932	0	0
T1	18127	17693	0	0
T2	35596	33090	0	0
T6	5416	5015	0	0
T7	9280	8873	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	98	0	0
T12	942	0	0	0
T13	19514	0	0	0
T35	0	8	0	0
T48	7160	14	0	0
T49	665	0	0	0
T50	28661	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T89	0	5	0	0
T95	0	20	0	0
T96	0	6	0	0
T97	0	2	0	0
T98	0	7	0	0
T99	0	8	0	0
T100	0	6	0	0
T101	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	15007	0	0
T1	18127	105	0	0
T2	35596	37	0	0
T3	503	0	0	0
T7	9280	63	0	0
T8	696	0	0	0
T9	0	535	0	0
T10	0	10	0	0
T11	0	78	0	0
T13	0	445	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	32	0	0
T34	0	71	0	0
T36	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	397	0	0
T1	18127	2	0	0
T2	35596	2	0	0
T3	503	0	0	0
T7	9280	1	0	0
T8	696	0	0	0
T9	0	7	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6928372	0	0
T1	18127	15602	0	0
T2	35596	26469	0	0
T6	5416	5015	0	0
T7	9280	7355	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6930043	0	0
T1	18127	15605	0	0
T2	35596	26472	0	0
T6	5416	5016	0	0
T7	9280	7356	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	602	0	0
T1	18127	2	0	0
T2	35596	3	0	0
T3	503	0	0	0
T7	9280	2	0	0
T8	696	0	0	0
T9	0	7	0	0
T10	0	1	0	0
T11	0	5	0	0
T13	0	6	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	1	0	0
T35	0	8	0	0
T48	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	500	0	0
T1	18127	2	0	0
T2	35596	2	0	0
T3	503	0	0	0
T7	9280	1	0	0
T8	696	0	0	0
T9	0	7	0	0
T10	0	1	0	0
T11	0	3	0	0
T13	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	1	0	0
T35	0	8	0	0
T48	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	397	0	0
T1	18127	2	0	0
T2	35596	2	0	0
T3	503	0	0	0
T7	9280	1	0	0
T8	696	0	0	0
T9	0	7	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	397	0	0
T1	18127	2	0	0
T2	35596	2	0	0
T3	503	0	0	0
T7	9280	1	0	0
T8	696	0	0	0
T9	0	7	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	14578	0	0
T1	18127	103	0	0
T2	35596	35	0	0
T3	503	0	0	0
T7	9280	61	0	0
T8	696	0	0	0
T9	0	522	0	0
T10	0	9	0	0
T11	0	77	0	0
T13	0	440	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	31	0	0
T34	0	69	0	0
T36	0	45	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	362	0	0
T1	18127	2	0	0
T2	35596	2	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	1	0	0
T10	0	1	0	0
T13	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T37	0	2	0	0
T54	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T1
1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T7,T1,T9
1	1	Covered	T6,T7,T1

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T6,T72,T88
1	0	Covered	T11,T37,T181

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T9
0	1	Covered	T7,T1,T9
1	0	Covered	T11,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T1,T9
1	-	Covered	T7,T1,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T1
DetectSt	168	Covered	T6,T7,T1
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T7,T1,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T1
DebounceSt->IdleSt	163	Covered	T11,T75,T275
DetectSt->IdleSt	186	Covered	T6,T11,T37
DetectSt->StableSt	191	Covered	T7,T1,T9
IdleSt->DebounceSt	148	Covered	T6,T7,T1
StableSt->IdleSt	206	Covered	T7,T1,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T1
0	1	Covered	T6,T7,T1
0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T1
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T1
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T1
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T75,T275
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T1
DetectSt	-	-	-	-	1	-	-	Covered	T6,T11,T37
DetectSt	-	-	-	-	0	1	-	Covered	T7,T1,T9
DetectSt	-	-	-	-	0	0	-	Covered	T6,T7,T1
StableSt	-	-	-	-	-	-	1	Covered	T7,T1,T9
StableSt	-	-	-	-	-	-	0	Covered	T7,T1,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	3175	0	0
CntIncr_A	7995523	100727	0	0
CntNoWrap_A	7995523	7316854	0	0
DetectStDropOut_A	7995523	487	0	0
DetectedOut_A	7995523	70071	0	0
DetectedPulseOut_A	7995523	829	0	0
DisabledIdleSt_A	7995523	6873657	0	0
DisabledNoDetection_A	7995523	6875938	0	0
EnterDebounceSt_A	7995523	1593	0	0
EnterDetectSt_A	7995523	1583	0	0
EnterStableSt_A	7995523	829	0	0
PulseIsPulse_A	7995523	829	0	0
StayInStableSt	7995523	69115	0	0
gen_high_event_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_high_level_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	688	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	3175	0	0
T1	18127	32	0	0
T2	35596	0	0	0
T6	5416	50	0	0
T7	9280	58	0	0
T8	696	0	0	0
T9	0	4	0	0
T11	0	15	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	10	0	0
T36	0	40	0	0
T37	0	26	0	0
T54	0	48	0	0
T72	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	100727	0	0
T1	18127	1264	0	0
T2	35596	0	0	0
T6	5416	1400	0	0
T7	9280	1943	0	0
T8	696	0	0	0
T9	0	122	0	0
T11	0	395	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	240	0	0
T36	0	1280	0	0
T37	0	949	0	0
T54	0	1896	0	0
T72	0	434	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7316854	0	0
T1	18127	17665	0	0
T2	35596	33095	0	0
T6	5416	4965	0	0
T7	9280	8818	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	487	0	0
T1	18127	0	0	0
T2	35596	0	0	0
T6	5416	25	0	0
T7	9280	0	0	0
T8	696	0	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T72	0	9	0	0
T75	0	1	0	0
T88	0	12	0	0
T91	0	7	0	0
T92	0	23	0	0
T93	0	30	0	0
T181	0	4	0	0
T277	0	15	0	0
T278	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	70071	0	0
T1	18127	376	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	1232	0	0
T8	696	0	0	0
T9	0	26	0	0
T11	0	377	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	414	0	0
T36	0	1246	0	0
T54	0	1565	0	0
T87	0	2088	0	0
T108	0	2087	0	0
T276	0	782	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	829	0	0
T1	18127	16	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	29	0	0
T8	696	0	0	0
T9	0	2	0	0
T11	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	5	0	0
T36	0	20	0	0
T54	0	24	0	0
T87	0	15	0	0
T108	0	7	0	0
T276	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6873657	0	0
T1	18127	12422	0	0
T2	35596	33095	0	0
T6	5416	2014	0	0
T7	9280	4029	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6875938	0	0
T1	18127	12426	0	0
T2	35596	33111	0	0
T6	5416	2014	0	0
T7	9280	4029	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1593	0	0
T1	18127	16	0	0
T2	35596	0	0	0
T6	5416	25	0	0
T7	9280	29	0	0
T8	696	0	0	0
T9	0	2	0	0
T11	0	9	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	5	0	0
T36	0	20	0	0
T37	0	13	0	0
T54	0	24	0	0
T72	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1583	0	0
T1	18127	16	0	0
T2	35596	0	0	0
T6	5416	25	0	0
T7	9280	29	0	0
T8	696	0	0	0
T9	0	2	0	0
T11	0	6	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	5	0	0
T36	0	20	0	0
T37	0	13	0	0
T54	0	24	0	0
T72	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	829	0	0
T1	18127	16	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	29	0	0
T8	696	0	0	0
T9	0	2	0	0
T11	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	5	0	0
T36	0	20	0	0
T54	0	24	0	0
T87	0	15	0	0
T108	0	7	0	0
T276	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	829	0	0
T1	18127	16	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	29	0	0
T8	696	0	0	0
T9	0	2	0	0
T11	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	5	0	0
T36	0	20	0	0
T54	0	24	0	0
T87	0	15	0	0
T108	0	7	0	0
T276	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	69115	0	0
T1	18127	360	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	1202	0	0
T8	696	0	0	0
T9	0	24	0	0
T11	0	372	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	407	0	0
T36	0	1225	0	0
T54	0	1536	0	0
T87	0	2067	0	0
T108	0	2079	0	0
T276	0	776	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	688	0	0
T1	18127	16	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	28	0	0
T8	696	0	0	0
T9	0	2	0	0
T11	0	4	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	3	0	0
T36	0	19	0	0
T54	0	19	0	0
T87	0	9	0	0
T108	0	6	0	0
T276	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T1
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T7,T2,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T7,T2,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T7,T2,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T2
1	0	Covered	T6,T7,T1
1	1	Covered	T7,T2,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T2,T10
0	1	Covered	T11,T279,T280
1	0	Covered	T11,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T2,T10
0	1	Covered	T2,T10,T11
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T2,T10
1	-	Covered	T2,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T2,T10
DetectSt	168	Covered	T7,T2,T10
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T7,T2,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T2,T10
DebounceSt->IdleSt	163	Covered	T11,T50,T35
DetectSt->IdleSt	186	Covered	T11,T279,T280
DetectSt->StableSt	191	Covered	T7,T2,T10
IdleSt->DebounceSt	148	Covered	T7,T2,T10
StableSt->IdleSt	206	Covered	T7,T2,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T2,T10
0	1	Covered	T7,T2,T10
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T2,T10
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T2,T10
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T2,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T35,T279
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T2,T10
DetectSt	-	-	-	-	1	-	-	Covered	T11,T279,T280
DetectSt	-	-	-	-	0	1	-	Covered	T7,T2,T10
DetectSt	-	-	-	-	0	0	-	Covered	T7,T2,T10
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T7,T2,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	851	0	0
CntIncr_A	7995523	44760	0	0
CntNoWrap_A	7995523	7319178	0	0
DetectStDropOut_A	7995523	76	0	0
DetectedOut_A	7995523	15470	0	0
DetectedPulseOut_A	7995523	320	0	0
DisabledIdleSt_A	7995523	6940618	0	0
DisabledNoDetection_A	7995523	6942333	0	0
EnterDebounceSt_A	7995523	453	0	0
EnterDetectSt_A	7995523	400	0	0
EnterStableSt_A	7995523	320	0	0
PulseIsPulse_A	7995523	320	0	0
StayInStableSt	7995523	15127	0	0
gen_high_level_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	294	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	851	0	0
T1	18127	0	0	0
T2	35596	4	0	0
T3	503	0	0	0
T7	9280	2	0	0
T8	696	0	0	0
T10	0	4	0	0
T11	0	8	0	0
T13	0	2	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	8	0	0
T34	0	4	0	0
T35	0	6	0	0
T36	0	2	0	0
T50	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	44760	0	0
T1	18127	0	0	0
T2	35596	296	0	0
T3	503	0	0	0
T7	9280	44	0	0
T8	696	0	0	0
T10	0	154	0	0
T11	0	230	0	0
T13	0	193	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	508	0	0
T34	0	102	0	0
T35	0	268	0	0
T36	0	59	0	0
T50	0	1320	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7319178	0	0
T1	18127	17697	0	0
T2	35596	33091	0	0
T6	5416	5015	0	0
T7	9280	8874	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	76	0	0
T11	7058	1	0	0
T12	942	0	0	0
T13	19514	0	0	0
T48	7160	0	0	0
T49	665	0	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T95	0	7	0	0
T146	0	2	0	0
T152	0	1	0	0
T162	0	5	0	0
T279	0	9	0	0
T280	0	3	0	0
T281	0	1	0	0
T282	0	3	0	0
T283	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	15470	0	0
T1	18127	0	0	0
T2	35596	11	0	0
T3	503	0	0	0
T7	9280	51	0	0
T8	696	0	0	0
T10	0	118	0	0
T11	0	77	0	0
T13	0	6	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	37	0	0
T34	0	102	0	0
T35	0	15	0	0
T36	0	45	0	0
T50	0	313	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	320	0	0
T1	18127	0	0	0
T2	35596	2	0	0
T3	503	0	0	0
T7	9280	1	0	0
T8	696	0	0	0
T10	0	2	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T50	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6940618	0	0
T1	18127	17321	0	0
T2	35596	29300	0	0
T6	5416	5015	0	0
T7	9280	7645	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6942333	0	0
T1	18127	17326	0	0
T2	35596	29307	0	0
T6	5416	5016	0	0
T7	9280	7646	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	453	0	0
T1	18127	0	0	0
T2	35596	2	0	0
T3	503	0	0	0
T7	9280	1	0	0
T8	696	0	0	0
T10	0	2	0	0
T11	0	5	0	0
T13	0	1	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T35	0	4	0	0
T36	0	1	0	0
T50	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	400	0	0
T1	18127	0	0	0
T2	35596	2	0	0
T3	503	0	0	0
T7	9280	1	0	0
T8	696	0	0	0
T10	0	2	0	0
T11	0	3	0	0
T13	0	1	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T50	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	320	0	0
T1	18127	0	0	0
T2	35596	2	0	0
T3	503	0	0	0
T7	9280	1	0	0
T8	696	0	0	0
T10	0	2	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T50	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	320	0	0
T1	18127	0	0	0
T2	35596	2	0	0
T3	503	0	0	0
T7	9280	1	0	0
T8	696	0	0	0
T10	0	2	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T50	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	15127	0	0
T1	18127	0	0	0
T2	35596	9	0	0
T3	503	0	0	0
T7	9280	49	0	0
T8	696	0	0	0
T10	0	116	0	0
T11	0	76	0	0
T13	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T33	0	33	0	0
T34	0	100	0	0
T35	0	13	0	0
T36	0	44	0	0
T50	0	303	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	294	0	0
T2	35596	2	0	0
T3	503	0	0	0
T4	1820	0	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	0	2	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T50	0	10	0	0
T139	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T1
1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T7,T1,T9
1	1	Covered	T6,T7,T1

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T6,T11,T72
1	0	Covered	T7,T11,T87

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T1,T9,T11
1	0	Covered	T11,T75,T284

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T11
1	-	Covered	T1,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T1
DetectSt	168	Covered	T6,T7,T1
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T1,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T1
DebounceSt->IdleSt	163	Covered	T11,T75,T275
DetectSt->IdleSt	186	Covered	T6,T7,T11
DetectSt->StableSt	191	Covered	T1,T9,T11
IdleSt->DebounceSt	148	Covered	T6,T7,T1
StableSt->IdleSt	206	Covered	T1,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T1
0	1	Covered	T6,T7,T1
0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T1
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T1
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T1
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T75,T275
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T1
DetectSt	-	-	-	-	1	-	-	Covered	T6,T7,T11
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T11
DetectSt	-	-	-	-	0	0	-	Covered	T6,T7,T1
StableSt	-	-	-	-	-	-	1	Covered	T1,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T11
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	3145	0	0
CntIncr_A	7995523	100418	0	0
CntNoWrap_A	7995523	7316884	0	0
DetectStDropOut_A	7995523	349	0	0
DetectedOut_A	7995523	98872	0	0
DetectedPulseOut_A	7995523	1085	0	0
DisabledIdleSt_A	7995523	6850459	0	0
DisabledNoDetection_A	7995523	6852711	0	0
EnterDebounceSt_A	7995523	1575	0	0
EnterDetectSt_A	7995523	1570	0	0
EnterStableSt_A	7995523	1085	0	0
PulseIsPulse_A	7995523	1085	0	0
StayInStableSt	7995523	97629	0	0
gen_high_event_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_high_level_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	911	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	3145	0	0
T1	18127	60	0	0
T2	35596	0	0	0
T6	5416	26	0	0
T7	9280	22	0	0
T8	696	0	0	0
T9	0	46	0	0
T11	0	16	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	48	0	0
T36	0	12	0	0
T37	0	26	0	0
T54	0	48	0	0
T72	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	100418	0	0
T1	18127	2250	0	0
T2	35596	0	0	0
T6	5416	723	0	0
T7	9280	769	0	0
T8	696	0	0	0
T9	0	1380	0	0
T11	0	512	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	1920	0	0
T36	0	228	0	0
T37	0	754	0	0
T54	0	1320	0	0
T72	0	1281	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7316884	0	0
T1	18127	17637	0	0
T2	35596	33095	0	0
T6	5416	4989	0	0
T7	9280	8854	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	349	0	0
T1	18127	0	0	0
T2	35596	0	0	0
T6	5416	13	0	0
T7	9280	0	0	0
T8	696	0	0	0
T11	0	1	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T72	0	26	0	0
T87	0	17	0	0
T88	0	7	0	0
T90	0	6	0	0
T92	0	14	0	0
T93	0	9	0	0
T94	0	22	0	0
T285	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	98872	0	0
T1	18127	1654	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	869	0	0
T11	0	351	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T34	0	1659	0	0
T36	0	194	0	0
T37	0	979	0	0
T54	0	1368	0	0
T108	0	502	0	0
T276	0	1014	0	0
T286	0	1432	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1085	0	0
T1	18127	30	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	23	0	0
T11	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T34	0	24	0	0
T36	0	6	0	0
T37	0	13	0	0
T54	0	24	0	0
T108	0	4	0	0
T276	0	4	0	0
T286	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6850459	0	0
T1	18127	11576	0	0
T2	35596	33095	0	0
T6	5416	2014	0	0
T7	9280	5219	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6852711	0	0
T1	18127	11578	0	0
T2	35596	33111	0	0
T6	5416	2014	0	0
T7	9280	5220	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1575	0	0
T1	18127	30	0	0
T2	35596	0	0	0
T6	5416	13	0	0
T7	9280	11	0	0
T8	696	0	0	0
T9	0	23	0	0
T11	0	9	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	24	0	0
T36	0	6	0	0
T37	0	13	0	0
T54	0	24	0	0
T72	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1570	0	0
T1	18127	30	0	0
T2	35596	0	0	0
T6	5416	13	0	0
T7	9280	11	0	0
T8	696	0	0	0
T9	0	23	0	0
T11	0	7	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	24	0	0
T36	0	6	0	0
T37	0	13	0	0
T54	0	24	0	0
T72	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1085	0	0
T1	18127	30	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	23	0	0
T11	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T34	0	24	0	0
T36	0	6	0	0
T37	0	13	0	0
T54	0	24	0	0
T108	0	4	0	0
T276	0	4	0	0
T286	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1085	0	0
T1	18127	30	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	23	0	0
T11	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T34	0	24	0	0
T36	0	6	0	0
T37	0	13	0	0
T54	0	24	0	0
T108	0	4	0	0
T276	0	4	0	0
T286	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	97629	0	0
T1	18127	1622	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	843	0	0
T11	0	346	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T34	0	1631	0	0
T36	0	188	0	0
T37	0	963	0	0
T54	0	1339	0	0
T108	0	498	0	0
T276	0	1009	0	0
T286	0	1421	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	911	0	0
T1	18127	28	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	20	0	0
T11	0	4	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T34	0	20	0	0
T36	0	6	0	0
T37	0	10	0	0
T54	0	19	0	0
T108	0	4	0	0
T276	0	3	0	0
T286	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T1
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T2,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T2,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T2,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T6,T7,T1
1	1	Covered	T2,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T33,T287,T280
1	0	Covered	T11,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T2,T9,T10
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T10
1	-	Covered	T2,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T10
DetectSt	168	Covered	T2,T9,T10
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T2,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T10
DebounceSt->IdleSt	163	Covered	T2,T10,T11
DetectSt->IdleSt	186	Covered	T11,T33,T287
DetectSt->StableSt	191	Covered	T2,T9,T10
IdleSt->DebounceSt	148	Covered	T2,T9,T10
StableSt->IdleSt	206	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T10
0	1	Covered	T2,T9,T10
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T10,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T11,T33,T287
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	0	0	-	Covered	T2,T9,T10
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	1095	0	0
CntIncr_A	7995523	57666	0	0
CntNoWrap_A	7995523	7318934	0	0
DetectStDropOut_A	7995523	27	0	0
DetectedOut_A	7995523	19327	0	0
DetectedPulseOut_A	7995523	485	0	0
DisabledIdleSt_A	7995523	6895722	0	0
DisabledNoDetection_A	7995523	6897389	0	0
EnterDebounceSt_A	7995523	581	0	0
EnterDetectSt_A	7995523	516	0	0
EnterStableSt_A	7995523	485	0	0
PulseIsPulse_A	7995523	485	0	0
StayInStableSt	7995523	18800	0	0
gen_high_level_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	440	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1095	0	0
T2	35596	19	0	0
T3	503	0	0	0
T4	1820	0	0	0
T5	678	0	0	0
T9	22687	2	0	0
T10	0	9	0	0
T11	0	8	0	0
T13	0	4	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T33	0	2	0	0
T34	0	4	0	0
T35	0	10	0	0
T37	0	6	0	0
T48	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	57666	0	0
T2	35596	1197	0	0
T3	503	0	0	0
T4	1820	0	0	0
T5	678	0	0	0
T9	22687	63	0	0
T10	0	466	0	0
T11	0	207	0	0
T13	0	234	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T33	0	136	0	0
T34	0	92	0	0
T35	0	326	0	0
T37	0	273	0	0
T48	0	1288	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7318934	0	0
T1	18127	17697	0	0
T2	35596	33076	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	27	0	0
T33	8334	1	0	0
T35	23513	0	0	0
T36	11527	0	0	0
T51	656	0	0	0
T69	524	0	0	0
T70	521	0	0	0
T71	2659	0	0	0
T75	0	1	0	0
T95	0	1	0	0
T146	0	2	0	0
T206	404	0	0	0
T207	410	0	0	0
T280	0	4	0	0
T287	0	11	0	0
T288	0	5	0	0
T289	0	1	0	0
T290	0	1	0	0
T291	453	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	19327	0	0
T2	35596	55	0	0
T3	503	0	0	0
T4	1820	0	0	0
T5	678	0	0	0
T9	22687	63	0	0
T10	0	143	0	0
T11	0	77	0	0
T13	0	165	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T34	0	111	0	0
T35	0	153	0	0
T37	0	165	0	0
T48	0	171	0	0
T139	0	182	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	485	0	0
T2	35596	9	0	0
T3	503	0	0	0
T4	1820	0	0	0
T5	678	0	0	0
T9	22687	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T13	0	2	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T34	0	2	0	0
T35	0	4	0	0
T37	0	3	0	0
T48	0	14	0	0
T139	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6895722	0	0
T1	18127	16045	0	0
T2	35596	26469	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6897389	0	0
T1	18127	16048	0	0
T2	35596	26472	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	581	0	0
T2	35596	10	0	0
T3	503	0	0	0
T4	1820	0	0	0
T5	678	0	0	0
T9	22687	1	0	0
T10	0	5	0	0
T11	0	5	0	0
T13	0	2	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	0	6	0	0
T37	0	3	0	0
T48	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	516	0	0
T2	35596	9	0	0
T3	503	0	0	0
T4	1820	0	0	0
T5	678	0	0	0
T9	22687	1	0	0
T10	0	4	0	0
T11	0	3	0	0
T13	0	2	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	0	4	0	0
T37	0	3	0	0
T48	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	485	0	0
T2	35596	9	0	0
T3	503	0	0	0
T4	1820	0	0	0
T5	678	0	0	0
T9	22687	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T13	0	2	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T34	0	2	0	0
T35	0	4	0	0
T37	0	3	0	0
T48	0	14	0	0
T139	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	485	0	0
T2	35596	9	0	0
T3	503	0	0	0
T4	1820	0	0	0
T5	678	0	0	0
T9	22687	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T13	0	2	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T34	0	2	0	0
T35	0	4	0	0
T37	0	3	0	0
T48	0	14	0	0
T139	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	18800	0	0
T2	35596	45	0	0
T3	503	0	0	0
T4	1820	0	0	0
T5	678	0	0	0
T9	22687	62	0	0
T10	0	139	0	0
T11	0	76	0	0
T13	0	163	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T34	0	109	0	0
T35	0	149	0	0
T37	0	162	0	0
T48	0	157	0	0
T139	0	176	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	440	0	0
T2	35596	8	0	0
T3	503	0	0	0
T4	1820	0	0	0
T5	678	0	0	0
T9	22687	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T13	0	2	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T34	0	2	0	0
T35	0	4	0	0
T37	0	3	0	0
T48	0	14	0	0
T139	0	6	0	0