Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T1
1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T1

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T7,T1,T9
1	1	Covered	T6,T7,T1

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T6,T11,T72
1	0	Covered	T9,T11,T108

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T11
0	1	Covered	T7,T1,T11
1	0	Covered	T259

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T1,T11
1	-	Covered	T7,T1,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T1
DetectSt	168	Covered	T6,T7,T1
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T7,T1,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T1
DebounceSt->IdleSt	163	Covered	T11,T75,T275
DetectSt->IdleSt	186	Covered	T6,T9,T11
DetectSt->StableSt	191	Covered	T7,T1,T11
IdleSt->DebounceSt	148	Covered	T6,T7,T1
StableSt->IdleSt	206	Covered	T7,T1,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T1
0	1	Covered	T6,T7,T1
0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T1
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T1
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T1
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T75,T275
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T1
DetectSt	-	-	-	-	1	-	-	Covered	T6,T9,T11
DetectSt	-	-	-	-	0	1	-	Covered	T7,T1,T11
DetectSt	-	-	-	-	0	0	-	Covered	T6,T7,T1
StableSt	-	-	-	-	-	-	1	Covered	T7,T1,T11
StableSt	-	-	-	-	-	-	0	Covered	T7,T1,T11
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	3212	0	0
CntIncr_A	7995523	113789	0	0
CntNoWrap_A	7995523	7316817	0	0
DetectStDropOut_A	7995523	477	0	0
DetectedOut_A	7995523	67316	0	0
DetectedPulseOut_A	7995523	861	0	0
DisabledIdleSt_A	7995523	6877789	0	0
DisabledNoDetection_A	7995523	6880104	0	0
EnterDebounceSt_A	7995523	1611	0	0
EnterDetectSt_A	7995523	1602	0	0
EnterStableSt_A	7995523	861	0	0
PulseIsPulse_A	7995523	861	0	0
StayInStableSt	7995523	66361	0	0
gen_high_event_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_high_level_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	764	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	3212	0	0
T1	18127	42	0	0
T2	35596	0	0	0
T6	5416	48	0	0
T7	9280	30	0	0
T8	696	0	0	0
T9	0	18	0	0
T11	0	16	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	10	0	0
T36	0	40	0	0
T37	0	50	0	0
T54	0	42	0	0
T72	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	113789	0	0
T1	18127	1365	0	0
T2	35596	0	0	0
T6	5416	1347	0	0
T7	9280	600	0	0
T8	696	0	0	0
T9	0	652	0	0
T11	0	442	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	275	0	0
T36	0	1060	0	0
T37	0	1750	0	0
T54	0	1176	0	0
T72	0	1281	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7316817	0	0
T1	18127	17655	0	0
T2	35596	33095	0	0
T6	5416	4967	0	0
T7	9280	8846	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	477	0	0
T1	18127	0	0	0
T2	35596	0	0	0
T6	5416	24	0	0
T7	9280	0	0	0
T8	696	0	0	0
T11	0	1	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T72	0	26	0	0
T87	0	29	0	0
T88	0	11	0	0
T90	0	9	0	0
T91	0	13	0	0
T92	0	27	0	0
T93	0	14	0	0
T94	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	67316	0	0
T1	18127	1594	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	967	0	0
T8	696	0	0	0
T11	0	327	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	379	0	0
T36	0	1466	0	0
T37	0	1651	0	0
T54	0	2286	0	0
T285	0	657	0	0
T286	0	369	0	0
T292	0	507	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	861	0	0
T1	18127	21	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	15	0	0
T8	696	0	0	0
T11	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	5	0	0
T36	0	20	0	0
T37	0	25	0	0
T54	0	21	0	0
T285	0	13	0	0
T286	0	12	0	0
T292	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6877789	0	0
T1	18127	11605	0	0
T2	35596	33095	0	0
T6	5416	2014	0	0
T7	9280	4670	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6880104	0	0
T1	18127	11607	0	0
T2	35596	33111	0	0
T6	5416	2014	0	0
T7	9280	4671	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1611	0	0
T1	18127	21	0	0
T2	35596	0	0	0
T6	5416	24	0	0
T7	9280	15	0	0
T8	696	0	0	0
T9	0	9	0	0
T11	0	9	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	5	0	0
T36	0	20	0	0
T37	0	25	0	0
T54	0	21	0	0
T72	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	1602	0	0
T1	18127	21	0	0
T2	35596	0	0	0
T6	5416	24	0	0
T7	9280	15	0	0
T8	696	0	0	0
T9	0	9	0	0
T11	0	7	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	5	0	0
T36	0	20	0	0
T37	0	25	0	0
T54	0	21	0	0
T72	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	861	0	0
T1	18127	21	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	15	0	0
T8	696	0	0	0
T11	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	5	0	0
T36	0	20	0	0
T37	0	25	0	0
T54	0	21	0	0
T285	0	13	0	0
T286	0	12	0	0
T292	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	861	0	0
T1	18127	21	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	15	0	0
T8	696	0	0	0
T11	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	5	0	0
T36	0	20	0	0
T37	0	25	0	0
T54	0	21	0	0
T285	0	13	0	0
T286	0	12	0	0
T292	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	66361	0	0
T1	18127	1571	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	952	0	0
T8	696	0	0	0
T11	0	322	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	372	0	0
T36	0	1445	0	0
T37	0	1623	0	0
T54	0	2261	0	0
T285	0	643	0	0
T286	0	357	0	0
T292	0	500	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	764	0	0
T1	18127	19	0	0
T2	35596	0	0	0
T3	503	0	0	0
T7	9280	15	0	0
T8	696	0	0	0
T11	0	5	0	0
T14	875	0	0	0
T15	494	0	0	0
T19	719	0	0	0
T20	526	0	0	0
T21	681	0	0	0
T34	0	3	0	0
T36	0	19	0	0
T37	0	22	0	0
T54	0	17	0	0
T285	0	12	0	0
T286	0	12	0	0
T292	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T1
1	Covered	T6,T7,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T7,T8	VC_COV_UNR
1	Covered	T1,T2,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T2
1	0	Covered	T6,T7,T1
1	1	Covered	T1,T2,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T10
0	1	Covered	T2,T10,T293
1	0	Covered	T11,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T48
0	1	Covered	T48,T13,T50
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T48
1	-	Covered	T11,T48,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T10
DetectSt	168	Covered	T1,T2,T10
IdleSt	163	Covered	T6,T7,T8
StableSt	191	Covered	T1,T11,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T10
DebounceSt->IdleSt	163	Covered	T2,T11,T35
DetectSt->IdleSt	186	Covered	T2,T10,T11
DetectSt->StableSt	191	Covered	T1,T11,T48
IdleSt->DebounceSt	148	Covered	T1,T2,T10
StableSt->IdleSt	206	Covered	T1,T11,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T10
0	1	Covered	T1,T2,T10
0	0	Excluded	T6,T7,T8	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T10
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T11,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T35,T40
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T10
DetectSt	-	-	-	-	1	-	-	Covered	T2,T10,T11
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T48
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T10
StableSt	-	-	-	-	-	-	1	Covered	T11,T48,T13
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7995523	936	0	0
CntIncr_A	7995523	54173	0	0
CntNoWrap_A	7995523	7319093	0	0
DetectStDropOut_A	7995523	93	0	0
DetectedOut_A	7995523	14307	0	0
DetectedPulseOut_A	7995523	341	0	0
DisabledIdleSt_A	7995523	6928955	0	0
DisabledNoDetection_A	7995523	6930684	0	0
EnterDebounceSt_A	7995523	499	0	0
EnterDetectSt_A	7995523	439	0	0
EnterStableSt_A	7995523	341	0	0
PulseIsPulse_A	7995523	341	0	0
StayInStableSt	7995523	13930	0	0
gen_high_level_sva.HighLevelEvent_A	7995523	7322528	0	0
gen_not_sticky_sva.StableStDropOut_A	7995523	301	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	936	0	0
T1	18127	4	0	0
T2	35596	24	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	0	0	0
T10	0	2	0	0
T11	0	7	0	0
T13	0	8	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T33	0	2	0	0
T35	0	7	0	0
T36	0	6	0	0
T48	0	6	0	0
T50	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	54173	0	0
T1	18127	182	0	0
T2	35596	1832	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	0	0	0
T10	0	136	0	0
T11	0	182	0	0
T13	0	472	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T33	0	129	0	0
T35	0	219	0	0
T36	0	222	0	0
T48	0	282	0	0
T50	0	152	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7319093	0	0
T1	18127	17693	0	0
T2	35596	33071	0	0
T6	5416	5015	0	0
T7	9280	8876	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	93	0	0
T2	35596	11	0	0
T3	503	0	0	0
T4	1820	0	0	0
T5	678	0	0	0
T9	22687	0	0	0
T10	0	1	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T89	0	2	0	0
T97	0	2	0	0
T189	0	7	0	0
T281	0	6	0	0
T293	0	6	0	0
T294	0	3	0	0
T295	0	8	0	0
T296	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	14307	0	0
T1	18127	134	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	0	0	0
T11	0	78	0	0
T13	0	324	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T33	0	7	0	0
T35	0	114	0	0
T36	0	92	0	0
T37	0	264	0	0
T48	0	28	0	0
T50	0	149	0	0
T54	0	306	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	341	0	0
T1	18127	2	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	0	0	0
T11	0	1	0	0
T13	0	4	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T33	0	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	3	0	0
T48	0	3	0	0
T50	0	2	0	0
T54	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6928955	0	0
T1	18127	16105	0	0
T2	35596	26469	0	0
T6	5416	5015	0	0
T7	9280	7909	0	0
T8	696	295	0	0
T14	875	474	0	0
T15	494	93	0	0
T19	719	318	0	0
T20	526	125	0	0
T21	681	280	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	6930684	0	0
T1	18127	16108	0	0
T2	35596	26472	0	0
T6	5416	5016	0	0
T7	9280	7911	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	499	0	0
T1	18127	2	0	0
T2	35596	13	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	0	0	0
T10	0	1	0	0
T11	0	5	0	0
T13	0	4	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T33	0	1	0	0
T35	0	4	0	0
T36	0	3	0	0
T48	0	3	0	0
T50	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	439	0	0
T1	18127	2	0	0
T2	35596	12	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	0	0	0
T10	0	1	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T33	0	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T48	0	3	0	0
T50	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	341	0	0
T1	18127	2	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	0	0	0
T11	0	1	0	0
T13	0	4	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T33	0	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	3	0	0
T48	0	3	0	0
T50	0	2	0	0
T54	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	341	0	0
T1	18127	2	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	0	0	0
T11	0	1	0	0
T13	0	4	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T33	0	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	3	0	0
T48	0	3	0	0
T50	0	2	0	0
T54	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	13930	0	0
T1	18127	130	0	0
T2	35596	0	0	0
T3	503	0	0	0
T4	1820	0	0	0
T9	22687	0	0	0
T11	0	77	0	0
T13	0	320	0	0
T14	875	0	0	0
T15	494	0	0	0
T16	504	0	0	0
T17	494	0	0	0
T18	431	0	0	0
T33	0	6	0	0
T35	0	111	0	0
T36	0	89	0	0
T37	0	261	0	0
T48	0	25	0	0
T50	0	147	0	0
T54	0	300	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	7322528	0	0
T1	18127	17702	0	0
T2	35596	33111	0	0
T6	5416	5016	0	0
T7	9280	8878	0	0
T8	696	296	0	0
T14	875	475	0	0
T15	494	94	0	0
T19	719	319	0	0
T20	526	126	0	0
T21	681	281	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7995523	301	0	0
T12	942	0	0	0
T13	19514	4	0	0
T33	0	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	3	0	0
T48	7160	3	0	0
T49	665	0	0	0
T50	28661	2	0	0
T54	0	2	0	0
T64	492	0	0	0
T65	494	0	0	0
T66	495	0	0	0
T68	504	0	0	0
T86	402	0	0	0
T279	0	1	0	0
T287	0	6	0	0