SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
sysrst_ctrl_combo_detect_det_cg_0 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_detect_det_cg_1 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_detect_det_cg_2 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_detect_det_cg_3 | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_detect_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_detect_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_detect_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_detect_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
max_range | 18 | 1 | T384 | 11 | T103 | 5 | T386 | 2 | ||||
mid_range | 250 | 1 | T2 | 10 | T31 | 12 | T35 | 3 | ||||
min_range | 697 | 1 | T1 | 7 | T5 | 1 | T7 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
max_range | 20 | 1 | T262 | 12 | T247 | 8 | - | - | ||||
mid_range | 297 | 1 | T2 | 10 | T31 | 12 | T29 | 7 | ||||
min_range | 648 | 1 | T1 | 7 | T5 | 1 | T7 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
max_range | 35 | 1 | T252 | 9 | T102 | 1 | T103 | 5 | ||||
mid_range | 275 | 1 | T2 | 10 | T31 | 12 | T29 | 7 | ||||
min_range | 655 | 1 | T1 | 7 | T5 | 1 | T7 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
max_range | 22 | 1 | T262 | 12 | T387 | 10 | - | - | ||||
mid_range | 273 | 1 | T2 | 10 | T35 | 2 | T179 | 12 | ||||
min_range | 670 | 1 | T1 | 7 | T5 | 1 | T7 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |