Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2057

1

T1

21

T5

15

T2

11

auto[1]

677

1

T1

7

T5

5

T2

8

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2194

1

T1

28

T5

15

T2

6

auto[1]

540

1

T5

5

T2

13

T26

10

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2176

1

T1

28

T5

15

T2

15

auto[1]

558

1

T5

5

T2

4

T7

9

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2092

1

T1

25

T5

20

T7

15

auto[1]

642

1

T1

3

T2

19

T7

5

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2498

1

T1

28

T5

20

T2

19

auto[1]

236

1

T7

5

T12

9

T89

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2400

1

T1

21

T5

20

T2

19

auto[1]

334

1

T1

7

T7

9

T12

22

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2386

1

T1

18

T5

20

T2

19

auto[1]

348

1

T1

10

T26

5

T12

9

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2468

1

T1

28

T5

15

T2

19

auto[1]

266

1

T5

5

T7

4

T12

5

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2489

1

T1

25

T5

15

T2

19

auto[1]

245

1

T1

3

T5

5

T7

4

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2056

1

T1

21

T5

20

T2

17

auto[1]

678

1

T1

7

T2

2

T12

14

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

830

1

T2

13

T31

17

T29

16

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

66

1

T93

3

T341

4

T344

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

39

1

T26

3

T89

3

T117

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T117

4

T84

4

T344

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

65

1

T30

2

T89

6

T117

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T89

2

T241

4

T32

12

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

24

1

T241

8

T242

1

T338

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T338

4

T353

4

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

85

1

T26

2

T30

6

T251

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T12

4

T365

1

T366

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

36

1

T1

3

T32

3

T118

12

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T118

4

T367

1

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

25

1

T158

7

T250

2

T341

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T368

1

T369

8

T347

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

12

1

T117

1

T369

5

T361

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

84

1

T12

12

T251

8

T370

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

37

1

T7

5

T12

5

T32

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

27

1

T30

4

T371

8

T372

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T250

1

T370

2

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

10

1

T242

1

T355

1

T373

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

22

1

T7

4

T371

8

T365

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T372

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

63

1

T1

7

T118

28

T158

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T366

3

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

19

1

T374

8

T375

2

T376

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T377

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

27

1

T12

5

T338

16

T369

6

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

155

1

T31

8

T89

6

T241

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

160

1

T12

5

T32

6

T158

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

105

1

T1

7

T118

14

T158

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

142

1

T1

3

T12

12

T32

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

67

1

T30

4

T35

4

T50

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

68

1

T118

14

T78

4

T251

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

23

1

T30

6

T251

4

T358

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

102

1

T30

2

T32

6

T117

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

42

1

T7

4

T31

2

T35

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T31

5

T77

1

T33

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

31

1

T33

2

T360

2

T368

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T7

5

T29

8

T253

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T31

2

T117

8

T227

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

23

1

T12

5

T179

3

T378

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T251

4

T101

1

T354

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

101

1

T241

4

T77

3

T292

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

46

1

T26

5

T32

3

T117

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

88

1

T12

4

T89

2

T259

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T179

3

T339

1

T358

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T2

9

T118

4

T84

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T77

2

T336

2

T339

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

16

1

T379

5

T380

1

T381

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T259

1

T243

1

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

46

1

T89

3

T179

6

T292

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T117

4

T382

2

T383

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

17

1

T29

5

T107

2

T84

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T253

1

T384

3

T254

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

32

1

T341

4

T75

5

T385

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T2

2

T227

1

T336

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

10

1

T2

2

T29

3

T253

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T359

1

T104

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded