Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1091

1

T13

10

T22

12

T68

10

auto[1]

1132

1

T13

10

T22

8

T68

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T13

5

T22

3

T68

3

from_0to1

528

1

T13

4

T22

3

T68

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T13

10

T22

8

T68

10

auto[1]

1134

1

T13

10

T22

12

T68

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T13

10

T22

12

T68

12

auto[1]

1083

1

T13

10

T22

8

T68

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T68

1

T34

3

T77

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T13

2

T22

1

T34

3

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T68

1

T34

1

T29

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T22

1

T34

1

T29

1

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T13

1

T34

1

T71

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T13

2

T22

1

T34

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T68

1

T34

5

T71

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T22

1

T68

1

T34

2

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T34

6

T71

1

T77

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T22

1

T68

1

T34

2

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T13

3

T34

3

T189

2

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T34

2

T29

1

T71

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T22

1

T68

1

T34

4

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T13

1

T68

1

T34

4

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T34

3

T29

2

T39

2

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T34

1

T71

1

T77

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T13

11

T22

13

T68

12

auto[1]

1113

1

T13

9

T22

7

T68

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T13

4

T22

5

T68

3

from_0to1

514

1

T13

4

T22

4

T68

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T13

6

T22

9

T68

11

auto[1]

1123

1

T13

14

T22

11

T68

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1114

1

T13

10

T22

7

T68

10

auto[1]

1109

1

T13

10

T22

13

T68

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T13

1

T68

1

T34

2

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T22

1

T34

2

T71

3

auto[0]

from_1to0

auto[1]

auto[0]

78

1

T22

1

T34

4

T29

2

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T22

1

T68

1

T34

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T13

1

T34

2

T71

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T22

1

T68

1

T34

2

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T13

2

T68

1

T34

4

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T22

2

T34

2

T189

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T13

1

T22

1

T34

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T13

1

T34

4

T39

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T13

1

T34

4

T29

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T22

1

T68

1

T189

3

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T22

1

T34

2

T39

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T34

5

T29

1

T71

2

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T68

1

T34

1

T39

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T13

1

T34

1

T29

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T13

9

T22

8

T68

12

auto[1]

1113

1

T13

11

T22

12

T68

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

536

1

T13

6

T22

5

T68

4

from_0to1

543

1

T13

6

T22

5

T68

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T13

7

T22

12

T68

11

auto[1]

1068

1

T13

13

T22

8

T68

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T13

12

T22

11

T68

12

auto[1]

1115

1

T13

8

T22

9

T68

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T22

2

T68

1

T34

4

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T13

1

T68

2

T34

3

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T68

1

T34

2

T71

1

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T13

1

T34

4

T39

2

auto[0]

from_0to1

auto[0]

auto[0]

82

1

T13

1

T68

1

T34

8

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T34

3

T71

1

T189

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T13

3

T22

1

T34

2

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T34

1

T29

1

T77

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T34

1

T71

1

T39

2

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T22

2

T29

2

T71

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T13

4

T22

1

T34

6

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T34

3

T71

1

T189

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T22

1

T68

1

T34

2

auto[1]

from_0to1

auto[0]

auto[1]

81

1

T13

1

T22

3

T34

3

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T68

1

T34

3

T29

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T13

1

T68

1

T34

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T13

9

T22

10

T68

13

auto[1]

1127

1

T13

11

T22

10

T68

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

543

1

T13

5

T22

3

T68

6

from_0to1

533

1

T13

4

T22

3

T68

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1082

1

T13

5

T22

6

T68

9

auto[1]

1141

1

T13

15

T22

14

T68

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1168

1

T13

8

T22

12

T68

11

auto[1]

1055

1

T13

12

T22

8

T68

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

80

1

T68

1

T34

2

T29

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T22

1

T68

2

T34

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T13

2

T68

1

T34

4

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T13

1

T68

2

T34

3

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T34

2

T189

1

T39

3

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T68

1

T34

1

T29

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T22

1

T68

2

T34

2

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T13

1

T34

6

T29

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T34

4

T71

1

T77

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T13

1

T34

2

T29

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T22

2

T34

2

T29

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T13

1

T34

2

T29

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T22

1

T68

1

T34

2

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T68

1

T34

2

T29

2

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T68

1

T34

6

T29

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T13

3

T22

1

T29

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T13

10

T22

8

T68

8

auto[1]

1094

1

T13

10

T22

12

T68

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

525

1

T13

4

T22

4

T68

5

from_0to1

533

1

T13

4

T22

4

T68

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1118

1

T13

4

T22

10

T68

9

auto[1]

1105

1

T13

16

T22

10

T68

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T13

12

T22

12

T68

12

auto[1]

1098

1

T13

8

T22

8

T68

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T22

2

T34

2

T77

2

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T22

1

T68

1

T34

2

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T13

1

T68

1

T34

2

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T34

2

T29

1

T189

1

auto[0]

from_0to1

auto[0]

auto[0]

82

1

T34

3

T29

1

T71

2

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T68

1

T34

3

T189

1

auto[0]

from_0to1

auto[1]

auto[0]

44

1

T34

1

T189

1

T39

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T13

1

T68

1

T34

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T13

1

T68

2

T34

2

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T22

1

T34

2

T29

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T13

1

T68

1

T34

2

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T13

1

T34

1

T71

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T13

1

T34

2

T29

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T22

1

T68

1

T34

2

auto[1]

from_0to1

auto[1]

auto[0]

80

1

T13

1

T22

2

T68

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T13

1

T22

1

T68

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1144

1

T13

9

T22

12

T68

7

auto[1]

1079

1

T13

11

T22

8

T68

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

547

1

T13

3

T22

4

T68

3

from_0to1

546

1

T13

3

T22

4

T68

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1166

1

T13

12

T22

14

T68

14

auto[1]

1057

1

T13

8

T22

6

T68

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1118

1

T13

10

T22

10

T68

10

auto[1]

1105

1

T13

10

T22

10

T68

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T22

1

T34

1

T71

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T13

1

T34

3

T302

2

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T22

1

T68

1

T34

4

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T34

3

T29

2

T71

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T22

1

T34

4

T71

1

auto[0]

from_0to1

auto[0]

auto[1]

82

1

T22

1

T34

2

T189

2

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T22

1

T34

4

T71

2

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T68

1

T34

1

T29

2

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T13

1

T68

1

T29

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T13

1

T34

3

T189

2

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T22

2

T34

2

T189

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T68

1

T34

5

T71

2

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T22

1

T34

2

T29

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T13

2

T68

2

T34

5

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T29

1

T39

1

T106

2

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T13

1

T34

3

T71

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1088

1

T13

11

T22

11

T68

11

auto[1]

1135

1

T13

9

T22

9

T68

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

531

1

T13

4

T22

4

T68

5

from_0to1

534

1

T13

4

T22

4

T68

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T13

11

T22

11

T68

11

auto[1]

1124

1

T13

9

T22

9

T68

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107

1

T13

9

T22

9

T68

8

auto[1]

1116

1

T13

11

T22

11

T68

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T13

1

T22

1

T68

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T13

1

T22

1

T34

3

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T13

1

T34

1

T29

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T22

2

T68

2

T34

4

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T13

1

T22

1

T34

2

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T13

1

T68

1

T34

1

auto[0]

from_0to1

auto[1]

auto[0]

75

1

T13

1

T34

4

T29

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T68

2

T29

2

T189

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T13

1

T34

2

T29

1

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T34

2

T71

2

T77

3

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T68

2

T34

3

T29

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T34

4

T189

1

T106

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T22

1

T34

4

T71

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T22

1

T68

2

T34

2

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T13

1

T22

1

T34

2

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T34

3

T29

1

T189

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1130

1

T13

13

T22

10

T68

11

auto[1]

1093

1

T13

7

T22

10

T68

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

535

1

T13

5

T22

5

T68

4

from_0to1

530

1

T13

5

T22

5

T68

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T13

12

T22

12

T68

3

auto[1]

1142

1

T13

8

T22

8

T68

17

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1143

1

T13

12

T22

9

T68

11

auto[1]

1080

1

T13

8

T22

11

T68

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T13

2

T34

3

T189

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T13

2

T22

2

T34

3

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T22

1

T68

1

T34

5

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T34

1

T39

3

T302

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T13

1

T22

2

T68

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T13

1

T68

1

T34

3

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T13

2

T68

1

T34

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T68

1

T29

1

T189

1

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T22

1

T34

2

T71

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T22

1

T68

1

T34

2

auto[1]

from_1to0

auto[1]

auto[0]

83

1

T68

1

T34

4

T29

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T13

1

T68

1

T34

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T22

2

T34

2

T29

1

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T34

4

T29

1

T71

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T13

1

T34

4

T71

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T22

1

T68

1

T34

2