Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	165902	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

123876

1

T1

386

T4

5

T5

238

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	148319	1			T1	339		T4	2		T5	209
values[0x0]	70199	1			T1	325		T4	7		T5	262
values[0x1]	71260	1			T1	338		T4	5		T5	236

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	134307	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

155471

1

T1

480

T4

7

T5

296

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1133	1			T1	3		T5	3		T2	2
valid_sources[0x01]	917	1			T1	5		T5	3		T2	3
valid_sources[0x02]	1344	1			T1	4		T5	2		T2	1
valid_sources[0x03]	1010	1			T1	2		T5	3		T2	2
valid_sources[0x04]	960	1			T1	7		T2	2		T15	5
valid_sources[0x05]	974	1			T1	1		T5	4		T42	1
valid_sources[0x06]	1464	1			T1	2		T5	2		T2	1
valid_sources[0x07]	1755	1			T1	3		T5	4		T2	3
valid_sources[0x08]	1458	1			T5	1		T2	1		T8	1
valid_sources[0x09]	990	1			T1	8		T5	1		T2	3
valid_sources[0x0a]	1904	1			T1	6		T5	4		T2	1
valid_sources[0x0b]	1248	1			T1	3		T5	1		T2	2
valid_sources[0x0c]	963	1			T5	4		T2	4		T42	2
valid_sources[0x0d]	1054	1			T5	3		T2	1		T8	1
valid_sources[0x0e]	1010	1			T1	1		T2	3		T14	2
valid_sources[0x0f]	996	1			T5	3		T42	6		T12	6
valid_sources[0x10]	2051	1			T1	4		T4	1		T5	4
valid_sources[0x11]	848	1			T1	5		T5	7		T2	2
valid_sources[0x12]	975	1			T1	11		T5	1		T2	5
valid_sources[0x13]	952	1			T1	2		T5	3		T2	2
valid_sources[0x14]	1051	1			T1	11		T4	1		T5	1
valid_sources[0x15]	1017	1			T1	5		T5	4		T2	3
valid_sources[0x16]	1005	1			T5	2		T3	4		T52	6
valid_sources[0x17]	891	1			T1	2		T4	1		T5	2
valid_sources[0x18]	929	1			T1	9		T5	4		T2	2
valid_sources[0x19]	920	1			T1	3		T5	3		T2	3
valid_sources[0x1a]	861	1			T1	4		T5	4		T2	4
valid_sources[0x1b]	811	1			T1	2		T5	3		T2	2
valid_sources[0x1c]	944	1			T1	2		T4	1		T5	2
valid_sources[0x1d]	922	1			T5	3		T2	4		T8	1
valid_sources[0x1e]	1010	1			T1	8		T5	3		T2	3
valid_sources[0x1f]	1174	1			T1	3		T5	1		T2	3
valid_sources[0x20]	1037	1			T5	3		T2	7		T42	2
valid_sources[0x21]	1012	1			T1	2		T5	3		T2	4
valid_sources[0x22]	848	1			T1	8		T5	2		T2	7
valid_sources[0x23]	840	1			T1	5		T5	3		T2	1
valid_sources[0x24]	1102	1			T5	3		T2	1		T42	5
valid_sources[0x25]	1058	1			T1	7		T5	1		T2	2
valid_sources[0x26]	879	1			T1	4		T5	1		T2	2
valid_sources[0x27]	1222	1			T1	7		T5	3		T2	2
valid_sources[0x28]	1118	1			T1	2		T5	2		T2	1
valid_sources[0x29]	1656	1			T1	6		T5	4		T2	5
valid_sources[0x2a]	878	1			T5	1		T2	2		T25	1
valid_sources[0x2b]	1126	1			T1	3		T5	5		T2	2
valid_sources[0x2c]	2281	1			T5	3		T2	1		T42	3
valid_sources[0x2d]	874	1			T5	1		T2	1		T42	1
valid_sources[0x2e]	929	1			T1	5		T5	4		T2	2
valid_sources[0x2f]	1042	1			T1	9		T5	2		T2	2
valid_sources[0x30]	976	1			T1	2		T5	4		T2	6
valid_sources[0x31]	934	1			T1	7		T5	3		T2	2
valid_sources[0x32]	952	1			T1	4		T2	1		T42	1
valid_sources[0x33]	888	1			T1	13		T5	2		T2	1
valid_sources[0x34]	2120	1			T1	2		T5	3		T6	2
valid_sources[0x35]	1058	1			T1	14		T5	2		T2	3
valid_sources[0x36]	1317	1			T1	4		T5	1		T2	2
valid_sources[0x37]	1060	1			T1	1		T5	5		T2	2
valid_sources[0x38]	1027	1			T1	13		T5	2		T2	3
valid_sources[0x39]	1671	1			T1	2		T5	5		T2	3
valid_sources[0x3a]	980	1			T1	6		T2	3		T6	2
valid_sources[0x3b]	1870	1			T1	1		T5	3		T2	1
valid_sources[0x3c]	1288	1			T1	11		T5	1		T2	3
valid_sources[0x3d]	1423	1			T1	6		T2	1		T42	6
valid_sources[0x3e]	896	1			T1	3		T5	3		T2	2
valid_sources[0x3f]	945	1			T1	7		T5	2		T2	3
valid_sources[0x40]	1411	1			T1	2		T5	2		T2	1
valid_sources[0x41]	1019	1			T1	3		T4	1		T5	3
valid_sources[0x42]	995	1			T1	12		T5	3		T2	3
valid_sources[0x43]	1109	1			T1	2		T4	1		T5	3
valid_sources[0x44]	755	1			T1	7		T5	3		T2	4
valid_sources[0x45]	1687	1			T1	4		T5	1		T2	2
valid_sources[0x46]	1235	1			T1	8		T5	1		T2	4
valid_sources[0x47]	1699	1			T5	2		T2	1		T6	3
valid_sources[0x48]	957	1			T1	6		T5	7		T2	2
valid_sources[0x49]	1075	1			T1	2		T5	4		T2	1
valid_sources[0x4a]	834	1			T1	4		T5	2		T2	2
valid_sources[0x4b]	1203	1			T5	3		T2	1		T42	7
valid_sources[0x4c]	1012	1			T1	2		T5	1		T2	3
valid_sources[0x4d]	1102	1			T1	2		T5	3		T2	4
valid_sources[0x4e]	960	1			T1	18		T5	8		T2	6
valid_sources[0x4f]	1584	1			T2	1		T42	1		T12	5
valid_sources[0x50]	1250	1			T1	5		T5	3		T42	3
valid_sources[0x51]	879	1			T5	3		T2	2		T42	3
valid_sources[0x52]	1813	1			T1	2		T5	5		T2	3
valid_sources[0x53]	1089	1			T1	5		T5	5		T8	1
valid_sources[0x54]	1048	1			T1	1		T5	5		T2	4
valid_sources[0x55]	1026	1			T5	3		T2	4		T8	1
valid_sources[0x56]	880	1			T1	7		T5	4		T2	4
valid_sources[0x57]	1067	1			T5	2		T2	1		T42	3
valid_sources[0x58]	1668	1			T1	3		T5	4		T2	1
valid_sources[0x59]	862	1			T1	1		T5	2		T2	2
valid_sources[0x5a]	1029	1			T1	6		T5	1		T2	2
valid_sources[0x5b]	854	1			T5	3		T42	2		T12	4
valid_sources[0x5c]	1483	1			T1	2		T5	2		T2	2
valid_sources[0x5d]	1255	1			T1	4		T5	5		T2	2
valid_sources[0x5e]	1017	1			T1	3		T5	4		T42	2
valid_sources[0x5f]	1033	1			T5	1		T2	1		T12	11
valid_sources[0x60]	1109	1			T5	6		T2	4		T42	5
valid_sources[0x61]	1253	1			T4	1		T5	4		T2	1
valid_sources[0x62]	905	1			T1	3		T5	7		T2	4
valid_sources[0x63]	1340	1			T5	6		T2	5		T42	3
valid_sources[0x64]	1008	1			T5	3		T2	3		T42	5
valid_sources[0x65]	1081	1			T5	1		T2	1		T14	2
valid_sources[0x66]	900	1			T1	6		T5	1		T2	2
valid_sources[0x67]	918	1			T1	2		T5	1		T2	6
valid_sources[0x68]	994	1			T1	5		T5	1		T2	4
valid_sources[0x69]	865	1			T1	5		T5	3		T2	2
valid_sources[0x6a]	963	1			T1	2		T5	1		T2	4
valid_sources[0x6b]	958	1			T1	17		T5	2		T42	5
valid_sources[0x6c]	858	1			T5	2		T2	3		T14	4
valid_sources[0x6d]	1664	1			T1	2		T5	3		T2	1
valid_sources[0x6e]	855	1			T1	8		T5	3		T2	2
valid_sources[0x6f]	1116	1			T1	5		T5	1		T8	1
valid_sources[0x70]	994	1			T1	1		T2	1		T42	2
valid_sources[0x71]	942	1			T5	3		T2	2		T8	1
valid_sources[0x72]	1391	1			T1	7		T5	4		T2	3
valid_sources[0x73]	1060	1			T1	3		T5	1		T42	7
valid_sources[0x74]	997	1			T1	13		T4	1		T5	3
valid_sources[0x75]	841	1			T1	1		T5	1		T2	4
valid_sources[0x76]	1019	1			T1	5		T5	1		T2	5
valid_sources[0x77]	919	1			T5	6		T2	3		T9	6
valid_sources[0x78]	1155	1			T5	6		T2	1		T42	5
valid_sources[0x79]	886	1			T1	13		T5	2		T2	3
valid_sources[0x7a]	1141	1			T5	1		T9	1		T42	5
valid_sources[0x7b]	908	1			T1	8		T5	1		T2	2
valid_sources[0x7c]	1252	1			T1	2		T5	5		T2	2
valid_sources[0x7d]	851	1			T1	3		T5	3		T2	1
valid_sources[0x7e]	1028	1			T5	2		T2	4		T10	10
valid_sources[0x7f]	983	1			T5	4		T2	2		T12	10
valid_sources[0x80]	2022	1			T1	1		T5	2		T2	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65975

1

T1

180

T4

2

T5

107

values[0x0]

all_enables

biggest_size

34048

1

T1

131

T4

2

T5

89

values[0x1]

all_enables

biggest_size

23853

1

T1

75

T4

1

T5

42