Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T24,T25,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T24,T25,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T24,T25,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T11
1	0	Covered	T1,T5,T13
1	1	Covered	T24,T25,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T11
0	1	Covered	T102
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T11
0	1	Covered	T24,T25,T11
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T25,T11
1	-	Covered	T24,T25,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T25,T11
DetectSt	168	Covered	T24,T25,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T24,T25,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T25,T11
DebounceSt->IdleSt	163	Covered	T11,T35,T90
DetectSt->IdleSt	186	Covered	T102
DetectSt->StableSt	191	Covered	T24,T25,T11
IdleSt->DebounceSt	148	Covered	T24,T25,T11
StableSt->IdleSt	206	Covered	T24,T25,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T25,T11
0	1	Covered	T24,T25,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T25,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T25,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T35,T90
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T25,T11
DetectSt	-	-	-	-	1	-	-	Covered	T102
DetectSt	-	-	-	-	0	1	-	Covered	T24,T25,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T25,T11
StableSt	-	-	-	-	-	-	0	Covered	T24,T25,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	295	0	0
CntIncr_A	5852696	105497	0	0
CntNoWrap_A	5852696	5185394	0	0
DetectStDropOut_A	5852696	1	0	0
DetectedOut_A	5852696	890	0	0
DetectedPulseOut_A	5852696	136	0	0
DisabledIdleSt_A	5852696	5073441	0	0
DisabledNoDetection_A	5852696	5075812	0	0
EnterDebounceSt_A	5852696	159	0	0
EnterDetectSt_A	5852696	137	0	0
EnterStableSt_A	5852696	136	0	0
PulseIsPulse_A	5852696	136	0	0
StayInStableSt	5852696	754	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5852696	7039	0	0
gen_low_level_sva.LowLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	136	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	295	0	0
T11	2146	3	0	0
T12	28231	0	0	0
T20	496	0	0	0
T24	769	4	0	0
T25	754	2	0	0
T30	21557	0	0	0
T34	0	4	0	0
T35	0	9	0	0
T42	7244	0	0	0
T44	5271	0	0	0
T47	0	4	0	0
T48	0	4	0	0
T49	0	6	0	0
T50	0	2	0	0
T52	415	0	0	0
T53	410	0	0	0
T90	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	105497	0	0
T11	2146	77	0	0
T12	28231	0	0	0
T20	496	0	0	0
T24	769	154	0	0
T25	754	13	0	0
T30	21557	0	0	0
T34	0	63	0	0
T35	0	201	0	0
T42	7244	0	0	0
T44	5271	0	0	0
T47	0	133	0	0
T48	0	109	0	0
T49	0	144	0	0
T50	0	76	0	0
T52	415	0	0	0
T53	410	0	0	0
T90	0	225	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185394	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1	0	0
T102	16031	1	0	0
T108	13016	0	0	0
T109	402	0	0	0
T110	432	0	0	0
T111	702	0	0	0
T112	449	0	0	0
T113	740	0	0	0
T114	5895	0	0	0
T115	412	0	0	0
T116	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	890	0	0
T11	2146	3	0	0
T12	28231	0	0	0
T20	496	0	0	0
T24	769	12	0	0
T25	754	8	0	0
T30	21557	0	0	0
T34	0	15	0	0
T35	0	25	0	0
T42	7244	0	0	0
T44	5271	0	0	0
T47	0	9	0	0
T48	0	10	0	0
T49	0	14	0	0
T50	0	7	0	0
T52	415	0	0	0
T53	410	0	0	0
T90	0	14	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	136	0	0
T11	2146	1	0	0
T12	28231	0	0	0
T20	496	0	0	0
T24	769	2	0	0
T25	754	1	0	0
T30	21557	0	0	0
T34	0	2	0	0
T35	0	4	0	0
T42	7244	0	0	0
T44	5271	0	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	3	0	0
T50	0	1	0	0
T52	415	0	0	0
T53	410	0	0	0
T90	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5073441	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5075812	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	159	0	0
T11	2146	2	0	0
T12	28231	0	0	0
T20	496	0	0	0
T24	769	2	0	0
T25	754	1	0	0
T30	21557	0	0	0
T34	0	2	0	0
T35	0	5	0	0
T42	7244	0	0	0
T44	5271	0	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	3	0	0
T50	0	1	0	0
T52	415	0	0	0
T53	410	0	0	0
T90	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	137	0	0
T11	2146	1	0	0
T12	28231	0	0	0
T20	496	0	0	0
T24	769	2	0	0
T25	754	1	0	0
T30	21557	0	0	0
T34	0	2	0	0
T35	0	4	0	0
T42	7244	0	0	0
T44	5271	0	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	3	0	0
T50	0	1	0	0
T52	415	0	0	0
T53	410	0	0	0
T90	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	136	0	0
T11	2146	1	0	0
T12	28231	0	0	0
T20	496	0	0	0
T24	769	2	0	0
T25	754	1	0	0
T30	21557	0	0	0
T34	0	2	0	0
T35	0	4	0	0
T42	7244	0	0	0
T44	5271	0	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	3	0	0
T50	0	1	0	0
T52	415	0	0	0
T53	410	0	0	0
T90	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	136	0	0
T11	2146	1	0	0
T12	28231	0	0	0
T20	496	0	0	0
T24	769	2	0	0
T25	754	1	0	0
T30	21557	0	0	0
T34	0	2	0	0
T35	0	4	0	0
T42	7244	0	0	0
T44	5271	0	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	3	0	0
T50	0	1	0	0
T52	415	0	0	0
T53	410	0	0	0
T90	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	754	0	0
T11	2146	2	0	0
T12	28231	0	0	0
T20	496	0	0	0
T24	769	10	0	0
T25	754	7	0	0
T30	21557	0	0	0
T34	0	13	0	0
T35	0	21	0	0
T42	7244	0	0	0
T44	5271	0	0	0
T47	0	7	0	0
T48	0	8	0	0
T49	0	11	0	0
T50	0	6	0	0
T52	415	0	0	0
T53	410	0	0	0
T90	0	12	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	7039	0	0
T1	19470	27	0	0
T2	23644	10	0	0
T3	1479	3	0	0
T4	413	0	0	0
T5	7177	20	0	0
T6	1105	6	0	0
T7	13717	35	0	0
T8	0	10	0	0
T9	0	7	0	0
T13	505	6	0	0
T14	493	9	0	0
T15	644	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	136	0	0
T11	2146	1	0	0
T12	28231	0	0	0
T20	496	0	0	0
T24	769	2	0	0
T25	754	1	0	0
T30	21557	0	0	0
T34	0	2	0	0
T35	0	4	0	0
T42	7244	0	0	0
T44	5271	0	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	3	0	0
T50	0	1	0	0
T52	415	0	0	0
T53	410	0	0	0
T90	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T1,T5,T13
1	1	Covered	T6,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T9
0	1	Covered	T8,T11,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T9
0	1	Unreachable
1	0	Covered	T6,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T8,T9
DetectSt	168	Covered	T6,T8,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T8,T9
DebounceSt->IdleSt	163	Covered	T8,T73,T74
DetectSt->IdleSt	186	Covered	T8,T11,T73
DetectSt->StableSt	191	Covered	T6,T8,T9
IdleSt->DebounceSt	148	Covered	T6,T8,T9
StableSt->IdleSt	206	Covered	T6,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T8,T9
0	1	Covered	T6,T8,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T73,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T8,T11,T73
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	153	0	0
CntIncr_A	5852696	76662	0	0
CntNoWrap_A	5852696	5185536	0	0
DetectStDropOut_A	5852696	11	0	0
DetectedOut_A	5852696	221867	0	0
DetectedPulseOut_A	5852696	51	0	0
DisabledIdleSt_A	5852696	3893265	0	0
DisabledNoDetection_A	5852696	3895681	0	0
EnterDebounceSt_A	5852696	92	0	0
EnterDetectSt_A	5852696	62	0	0
EnterStableSt_A	5852696	51	0	0
PulseIsPulse_A	5852696	51	0	0
StayInStableSt	5852696	221816	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5852696	7039	0	0
gen_low_level_sva.LowLevelEvent_A	5852696	5188108	0	0
gen_sticky_sva.StableStDropOut_A	5852696	906306	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	153	0	0
T6	1105	2	0	0
T7	13717	0	0	0
T8	1527	15	0	0
T9	1304	2	0	0
T11	0	2	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	4	0	0
T51	422	0	0	0
T60	0	2	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	13	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	76662	0	0
T6	1105	58	0	0
T7	13717	0	0	0
T8	1527	621	0	0
T9	1304	66	0	0
T11	0	64	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	74	0	0
T51	422	0	0	0
T60	0	77	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	638	0	0
T74	0	66	0	0
T75	0	23	0	0
T76	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185536	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	702	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	11	0	0
T8	1527	5	0	0
T9	1304	0	0	0
T10	627	0	0	0
T11	0	1	0	0
T22	513	0	0	0
T26	12294	0	0	0
T43	4719	0	0	0
T55	557	0	0	0
T57	632	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	4	0	0
T122	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	221867	0	0
T6	1105	190	0	0
T7	13717	0	0	0
T8	1527	71	0	0
T9	1304	202	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	113	0	0
T51	422	0	0	0
T60	0	202	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T75	0	128	0	0
T76	0	11	0	0
T82	0	87	0	0
T120	0	15	0	0
T121	0	25	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	51	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	1	0	0
T9	1304	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	2	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T82	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3893265	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	367	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3895681	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	368	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	92	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	9	0	0
T9	1304	1	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	2	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	9	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	62	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	6	0	0
T9	1304	1	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	2	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	4	0	0
T75	0	1	0	0
T76	0	1	0	0
T82	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	51	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	1	0	0
T9	1304	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	2	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T82	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	51	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	1	0	0
T9	1304	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	2	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T82	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	221816	0	0
T6	1105	189	0	0
T7	13717	0	0	0
T8	1527	70	0	0
T9	1304	201	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	111	0	0
T51	422	0	0	0
T60	0	201	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T75	0	127	0	0
T76	0	10	0	0
T82	0	86	0	0
T120	0	14	0	0
T121	0	24	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	7039	0	0
T1	19470	27	0	0
T2	23644	10	0	0
T3	1479	3	0	0
T4	413	0	0	0
T5	7177	20	0	0
T6	1105	6	0	0
T7	13717	35	0	0
T8	0	10	0	0
T9	0	7	0	0
T13	505	6	0	0
T14	493	9	0	0
T15	644	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	906306	0	0
T6	1105	72	0	0
T7	13717	0	0	0
T8	1527	50	0	0
T9	1304	114	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	80533	0	0
T51	422	0	0	0
T60	0	64	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T75	0	198	0	0
T76	0	34	0	0
T82	0	25	0	0
T120	0	37	0	0
T121	0	60	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T13,T3,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T13,T3,T6
1	1	Covered	T13,T3,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T13,T3,T6
1	1	Covered	T6,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T11
0	1	Covered	T9,T74,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T11
0	1	Unreachable
1	0	Covered	T6,T8,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T8,T9
DetectSt	168	Covered	T6,T8,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T8,T9
DebounceSt->IdleSt	163	Covered	T123,T124,T125
DetectSt->IdleSt	186	Covered	T9,T74,T88
DetectSt->StableSt	191	Covered	T6,T8,T11
IdleSt->DebounceSt	148	Covered	T6,T8,T9
StableSt->IdleSt	206	Covered	T6,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T8,T9
0	1	Covered	T6,T8,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T13,T3,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T123,T124,T125
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T9,T74,T88
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T8,T11
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	150	0	0
CntIncr_A	5852696	370410	0	0
CntNoWrap_A	5852696	5185539	0	0
DetectStDropOut_A	5852696	13	0	0
DetectedOut_A	5852696	368940	0	0
DetectedPulseOut_A	5852696	50	0	0
DisabledIdleSt_A	5852696	3893265	0	0
DisabledNoDetection_A	5852696	3895681	0	0
EnterDebounceSt_A	5852696	88	0	0
EnterDetectSt_A	5852696	63	0	0
EnterStableSt_A	5852696	50	0	0
PulseIsPulse_A	5852696	50	0	0
StayInStableSt	5852696	368890	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_sticky_sva.StableStDropOut_A	5852696	427652	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	150	0	0
T6	1105	2	0	0
T7	13717	0	0	0
T8	1527	6	0	0
T9	1304	6	0	0
T11	0	2	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	4	0	0
T51	422	0	0	0
T60	0	2	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	4	0	0
T74	0	4	0	0
T75	0	2	0	0
T76	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	370410	0	0
T6	1105	16	0	0
T7	13717	0	0	0
T8	1527	54	0	0
T9	1304	87	0	0
T11	0	87	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	110	0	0
T51	422	0	0	0
T60	0	56	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	7526	0	0
T74	0	27928	0	0
T75	0	36	0	0
T76	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185539	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	702	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	13	0	0
T9	1304	3	0	0
T10	627	0	0	0
T22	513	0	0	0
T26	12294	0	0	0
T43	4719	0	0	0
T55	557	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T74	0	2	0	0
T88	0	3	0	0
T124	0	2	0	0
T126	0	1	0	0
T127	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	368940	0	0
T6	1105	58	0	0
T7	13717	0	0	0
T8	1527	199	0	0
T9	1304	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	112	0	0
T51	422	0	0	0
T60	0	66	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	33359	0	0
T75	0	174	0	0
T76	0	20	0	0
T82	0	1	0	0
T119	0	33	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	50	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	3	0	0
T9	1304	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	2	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T82	0	1	0	0
T119	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3893265	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	367	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3895681	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	368	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	88	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	3	0	0
T9	1304	3	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	2	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	63	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	3	0	0
T9	1304	3	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	2	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	50	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	3	0	0
T9	1304	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	2	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T82	0	1	0	0
T119	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	50	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	3	0	0
T9	1304	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	2	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T82	0	1	0	0
T119	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	368890	0	0
T6	1105	57	0	0
T7	13717	0	0	0
T8	1527	196	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	110	0	0
T51	422	0	0	0
T60	0	65	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	33357	0	0
T75	0	173	0	0
T76	0	19	0	0
T119	0	32	0	0
T120	0	17	0	0
T121	0	13	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	427652	0	0
T6	1105	237	0	0
T7	13717	0	0	0
T8	1527	747	0	0
T9	1304	0	0	0
T11	0	24	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	80483	0	0
T51	422	0	0	0
T60	0	220	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	345	0	0
T75	0	127	0	0
T76	0	48	0	0
T82	0	136	0	0
T119	0	216	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T1,T5,T13
1	1	Covered	T6,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T11
0	1	Covered	T8,T86,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T11
0	1	Unreachable
1	0	Covered	T6,T8,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T8,T9
DetectSt	168	Covered	T6,T8,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T8,T11
DebounceSt->IdleSt	163	Covered	T9,T34,T119
DetectSt->IdleSt	186	Covered	T8,T86,T87
DetectSt->StableSt	191	Covered	T6,T8,T11
IdleSt->DebounceSt	148	Covered	T6,T8,T9
StableSt->IdleSt	206	Covered	T6,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T8,T9
0	1	Covered	T6,T8,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T34,T119
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T8,T86,T87
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T8,T11
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	174	0	0
CntIncr_A	5852696	226007	0	0
CntNoWrap_A	5852696	5185515	0	0
DetectStDropOut_A	5852696	17	0	0
DetectedOut_A	5852696	80044	0	0
DetectedPulseOut_A	5852696	49	0	0
DisabledIdleSt_A	5852696	3893265	0	0
DisabledNoDetection_A	5852696	3895681	0	0
EnterDebounceSt_A	5852696	109	0	0
EnterDetectSt_A	5852696	66	0	0
EnterStableSt_A	5852696	49	0	0
PulseIsPulse_A	5852696	49	0	0
StayInStableSt	5852696	79995	0	0
gen_high_event_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_sticky_sva.StableStDropOut_A	5852696	859400	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	174	0	0
T6	1105	2	0	0
T7	13717	0	0	0
T8	1527	8	0	0
T9	1304	3	0	0
T11	0	2	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	5	0	0
T51	422	0	0	0
T60	0	2	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	4	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	226007	0	0
T6	1105	71	0	0
T7	13717	0	0	0
T8	1527	352	0	0
T9	1304	162	0	0
T11	0	74	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	41213	0	0
T51	422	0	0	0
T60	0	86	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	5851	0	0
T74	0	53	0	0
T75	0	53	0	0
T76	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185515	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	702	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	17	0	0
T8	1527	1	0	0
T9	1304	0	0	0
T10	627	0	0	0
T22	513	0	0	0
T26	12294	0	0	0
T43	4719	0	0	0
T55	557	0	0	0
T57	632	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T86	0	3	0	0
T87	0	1	0	0
T128	0	4	0	0
T129	0	4	0	0
T130	0	1	0	0
T131	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	80044	0	0
T6	1105	207	0	0
T7	13717	0	0	0
T8	1527	537	0	0
T9	1304	0	0	0
T11	0	2	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	39309	0	0
T51	422	0	0	0
T60	0	215	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	27679	0	0
T74	0	104	0	0
T75	0	249	0	0
T76	0	14	0	0
T82	0	59	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	49	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	3	0	0
T9	1304	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	1	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T82	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3893265	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	367	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3895681	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	368	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	109	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	4	0	0
T9	1304	3	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	4	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	66	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	4	0	0
T9	1304	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	1	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T82	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	49	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	3	0	0
T9	1304	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	1	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T82	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	49	0	0
T6	1105	1	0	0
T7	13717	0	0	0
T8	1527	3	0	0
T9	1304	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	1	0	0
T51	422	0	0	0
T60	0	1	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T82	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	79995	0	0
T6	1105	206	0	0
T7	13717	0	0	0
T8	1527	534	0	0
T9	1304	0	0	0
T11	0	1	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	39308	0	0
T51	422	0	0	0
T60	0	214	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	27677	0	0
T74	0	103	0	0
T75	0	248	0	0
T76	0	13	0	0
T82	0	58	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	859400	0	0
T6	1105	53	0	0
T7	13717	0	0	0
T8	1527	134	0	0
T9	1304	0	0	0
T11	0	48	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	29	0	0
T51	422	0	0	0
T60	0	45	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T73	0	7726	0	0
T74	0	27855	0	0
T75	0	49	0	0
T76	0	25	0	0
T82	0	80	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T10,T23,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T10,T23,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T10,T23,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T23
1	0	Covered	T1,T4,T5
1	1	Covered	T10,T23,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T23,T34
0	1	Covered	T132
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T23,T34
0	1	Covered	T34,T38,T133
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T23,T34
1	-	Covered	T34,T38,T133

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T23,T34
DetectSt	168	Covered	T10,T23,T34
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T10,T23,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T23,T34
DebounceSt->IdleSt	163	Covered	T76,T134,T135
DetectSt->IdleSt	186	Covered	T132
DetectSt->StableSt	191	Covered	T10,T23,T34
IdleSt->DebounceSt	148	Covered	T10,T23,T34
StableSt->IdleSt	206	Covered	T34,T38,T133

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T23,T34
0	1	Covered	T10,T23,T34
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T23,T34
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T23,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T23,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T76,T134,T135
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T23,T34
DetectSt	-	-	-	-	1	-	-	Covered	T132
DetectSt	-	-	-	-	0	1	-	Covered	T10,T23,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T38,T133
StableSt	-	-	-	-	-	-	0	Covered	T10,T23,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	69	0	0
CntIncr_A	5852696	1992	0	0
CntNoWrap_A	5852696	5185620	0	0
DetectStDropOut_A	5852696	1	0	0
DetectedOut_A	5852696	2048	0	0
DetectedPulseOut_A	5852696	31	0	0
DisabledIdleSt_A	5852696	5167810	0	0
DisabledNoDetection_A	5852696	5170170	0	0
EnterDebounceSt_A	5852696	37	0	0
EnterDetectSt_A	5852696	32	0	0
EnterStableSt_A	5852696	31	0	0
PulseIsPulse_A	5852696	31	0	0
StayInStableSt	5852696	1996	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	69	0	0
T10	627	2	0	0
T22	513	0	0	0
T23	0	2	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	4	0	0
T38	0	4	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T76	0	1	0	0
T133	0	4	0	0
T134	0	1	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1992	0	0
T10	627	60	0	0
T22	513	0	0	0
T23	0	82	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	92	0	0
T38	0	172	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T76	0	67	0	0
T133	0	145	0	0
T134	0	96	0	0
T136	0	65	0	0
T137	0	43	0	0
T138	0	73	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185620	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1	0	0
T82	3218	0	0	0
T120	572	0	0	0
T132	613	1	0	0
T139	522	0	0	0
T140	422	0	0	0
T141	421	0	0	0
T142	522	0	0	0
T143	499	0	0	0
T144	422	0	0	0
T145	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	2048	0	0
T10	627	58	0	0
T22	513	0	0	0
T23	0	43	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	192	0	0
T38	0	82	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T87	0	43	0	0
T133	0	95	0	0
T136	0	42	0	0
T137	0	168	0	0
T138	0	44	0	0
T146	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	31	0	0
T10	627	1	0	0
T22	513	0	0	0
T23	0	1	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	2	0	0
T38	0	2	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T87	0	1	0	0
T133	0	2	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5167810	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	25	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5170170	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	26	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	37	0	0
T10	627	1	0	0
T22	513	0	0	0
T23	0	1	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	2	0	0
T38	0	2	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T76	0	1	0	0
T133	0	2	0	0
T134	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	32	0	0
T10	627	1	0	0
T22	513	0	0	0
T23	0	1	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	2	0	0
T38	0	2	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T132	0	1	0	0
T133	0	2	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T146	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	31	0	0
T10	627	1	0	0
T22	513	0	0	0
T23	0	1	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	2	0	0
T38	0	2	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T87	0	1	0	0
T133	0	2	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	31	0	0
T10	627	1	0	0
T22	513	0	0	0
T23	0	1	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	2	0	0
T38	0	2	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T87	0	1	0	0
T133	0	2	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1996	0	0
T10	627	56	0	0
T22	513	0	0	0
T23	0	41	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	189	0	0
T38	0	79	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T87	0	41	0	0
T133	0	93	0	0
T136	0	40	0	0
T137	0	167	0	0
T138	0	42	0	0
T146	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	9	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T38	0	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T89	36101	0	0	0
T133	0	2	0	0
T137	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T10,T23,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T10,T23,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T10,T23,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T23,T34
1	0	Covered	T1,T13,T2
1	1	Covered	T10,T23,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T23,T34
0	1	Covered	T38,T82,T149
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T23,T34
0	1	Covered	T10,T23,T34
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T23,T34
1	-	Covered	T10,T23,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T23,T34
DetectSt	168	Covered	T10,T23,T34
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T10,T23,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T23,T34
DebounceSt->IdleSt	163	Covered	T155,T102,T156
DetectSt->IdleSt	186	Covered	T38,T82,T149
DetectSt->StableSt	191	Covered	T10,T23,T34
IdleSt->DebounceSt	148	Covered	T10,T23,T34
StableSt->IdleSt	206	Covered	T10,T23,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T23,T34
0	1	Covered	T10,T23,T34
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T23,T34
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T23,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T23,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T155,T102,T156
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T23,T34
DetectSt	-	-	-	-	1	-	-	Covered	T38,T82,T149
DetectSt	-	-	-	-	0	1	-	Covered	T10,T23,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T23,T34
StableSt	-	-	-	-	-	-	0	Covered	T10,T23,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	139	0	0
CntIncr_A	5852696	3851	0	0
CntNoWrap_A	5852696	5185550	0	0
DetectStDropOut_A	5852696	3	0	0
DetectedOut_A	5852696	4530	0	0
DetectedPulseOut_A	5852696	64	0	0
DisabledIdleSt_A	5852696	5166601	0	0
DisabledNoDetection_A	5852696	5168958	0	0
EnterDebounceSt_A	5852696	72	0	0
EnterDetectSt_A	5852696	67	0	0
EnterStableSt_A	5852696	64	0	0
PulseIsPulse_A	5852696	64	0	0
StayInStableSt	5852696	4440	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5852696	2726	0	0
gen_low_level_sva.LowLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	139	0	0
T10	627	2	0	0
T22	513	0	0	0
T23	0	2	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	4	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	2	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T76	0	4	0	0
T133	0	4	0	0
T155	0	3	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3851	0	0
T10	627	60	0	0
T22	513	0	0	0
T23	0	82	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	87	0	0
T37	0	27	0	0
T38	0	172	0	0
T39	0	33	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T76	0	134	0	0
T133	0	138	0	0
T155	0	38	0	0
T157	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185550	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3	0	0
T33	16702	0	0	0
T38	3204	1	0	0
T39	7108	0	0	0
T41	659	0	0	0
T67	509	0	0	0
T78	13057	0	0	0
T82	0	1	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T149	0	1	0	0
T158	7909	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4530	0	0
T10	627	39	0	0
T22	513	0	0	0
T23	0	15	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	80	0	0
T37	0	284	0	0
T38	0	94	0	0
T39	0	97	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T76	0	83	0	0
T133	0	153	0	0
T155	0	95	0	0
T157	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	64	0	0
T10	627	1	0	0
T22	513	0	0	0
T23	0	1	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T76	0	2	0	0
T133	0	2	0	0
T155	0	1	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5166601	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5168958	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	72	0	0
T10	627	1	0	0
T22	513	0	0	0
T23	0	1	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T76	0	2	0	0
T133	0	2	0	0
T155	0	2	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	67	0	0
T10	627	1	0	0
T22	513	0	0	0
T23	0	1	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T76	0	2	0	0
T133	0	2	0	0
T155	0	1	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	64	0	0
T10	627	1	0	0
T22	513	0	0	0
T23	0	1	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T76	0	2	0	0
T133	0	2	0	0
T155	0	1	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	64	0	0
T10	627	1	0	0
T22	513	0	0	0
T23	0	1	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T76	0	2	0	0
T133	0	2	0	0
T155	0	1	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4440	0	0
T10	627	38	0	0
T22	513	0	0	0
T23	0	14	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	77	0	0
T37	0	282	0	0
T38	0	93	0	0
T39	0	96	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T76	0	80	0	0
T133	0	150	0	0
T155	0	94	0	0
T157	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	2726	0	0
T2	23644	0	0	0
T3	1479	3	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T10	0	1	0	0
T13	505	5	0	0
T14	493	4	0	0
T15	644	0	0	0
T20	0	6	0	0
T22	0	5	0	0
T51	422	3	0	0
T52	0	3	0	0
T61	405	0	0	0
T62	0	7	0	0
T63	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	37	0	0
T10	627	1	0	0
T22	513	0	0	0
T23	0	1	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T76	0	1	0	0
T133	0	1	0	0
T137	0	1	0	0
T155	0	1	0	0
T157	0	1	0	0