Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T38,T39,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T38,T39,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T38,T39,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T23,T38
1	0	Covered	T1,T4,T5
1	1	Covered	T38,T39,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T41
0	1	Covered	T134
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T41
0	1	Covered	T38,T39,T37
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T39,T41
1	-	Covered	T38,T39,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T38,T39,T41
DetectSt	168	Covered	T38,T39,T41
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T38,T39,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T39,T41
DebounceSt->IdleSt	163	Covered	T38,T159,T79
DetectSt->IdleSt	186	Covered	T134
DetectSt->StableSt	191	Covered	T38,T39,T41
IdleSt->DebounceSt	148	Covered	T38,T39,T41
StableSt->IdleSt	206	Covered	T38,T39,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T38,T39,T41
0	1	Covered	T38,T39,T41
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T41
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T38,T39,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T39,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T159
DebounceSt	-	0	0	-	-	-	-	Covered	T38,T39,T41
DetectSt	-	-	-	-	1	-	-	Covered	T134
DetectSt	-	-	-	-	0	1	-	Covered	T38,T39,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T39,T37
StableSt	-	-	-	-	-	-	0	Covered	T38,T39,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	77	0	0
CntIncr_A	5852696	2327	0	0
CntNoWrap_A	5852696	5185612	0	0
DetectStDropOut_A	5852696	1	0	0
DetectedOut_A	5852696	3074	0	0
DetectedPulseOut_A	5852696	36	0	0
DisabledIdleSt_A	5852696	5168652	0	0
DisabledNoDetection_A	5852696	5171021	0	0
EnterDebounceSt_A	5852696	40	0	0
EnterDetectSt_A	5852696	37	0	0
EnterStableSt_A	5852696	36	0	0
PulseIsPulse_A	5852696	36	0	0
StayInStableSt	5852696	3020	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	77	0	0
T33	16702	0	0	0
T37	0	4	0	0
T38	3204	3	0	0
T39	7108	4	0	0
T41	659	2	0	0
T67	509	0	0	0
T78	13057	0	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T133	0	2	0	0
T134	0	4	0	0
T137	0	2	0	0
T138	0	2	0	0
T155	0	4	0	0
T158	7909	0	0	0
T160	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	2327	0	0
T33	16702	0	0	0
T37	0	54	0	0
T38	3204	172	0	0
T39	7108	66	0	0
T41	659	41	0	0
T67	509	0	0	0
T78	13057	0	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T133	0	69	0	0
T134	0	192	0	0
T137	0	43	0	0
T138	0	97	0	0
T155	0	38	0	0
T158	7909	0	0	0
T160	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185612	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1	0	0
T134	12175	1	0	0
T160	754	0	0	0
T161	568	0	0	0
T162	423	0	0	0
T163	499	0	0	0
T164	526	0	0	0
T165	402	0	0	0
T166	502	0	0	0
T167	527	0	0	0
T168	6854	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3074	0	0
T33	16702	0	0	0
T37	0	97	0	0
T38	3204	41	0	0
T39	7108	189	0	0
T41	659	84	0	0
T67	509	0	0	0
T78	13057	0	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T133	0	166	0	0
T134	0	41	0	0
T137	0	45	0	0
T138	0	213	0	0
T155	0	82	0	0
T158	7909	0	0	0
T160	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	36	0	0
T33	16702	0	0	0
T37	0	2	0	0
T38	3204	1	0	0
T39	7108	2	0	0
T41	659	1	0	0
T67	509	0	0	0
T78	13057	0	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T133	0	1	0	0
T134	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T155	0	2	0	0
T158	7909	0	0	0
T160	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5168652	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5171021	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	40	0	0
T33	16702	0	0	0
T37	0	2	0	0
T38	3204	2	0	0
T39	7108	2	0	0
T41	659	1	0	0
T67	509	0	0	0
T78	13057	0	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T133	0	1	0	0
T134	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T155	0	2	0	0
T158	7909	0	0	0
T160	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	37	0	0
T33	16702	0	0	0
T37	0	2	0	0
T38	3204	1	0	0
T39	7108	2	0	0
T41	659	1	0	0
T67	509	0	0	0
T78	13057	0	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T133	0	1	0	0
T134	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T155	0	2	0	0
T158	7909	0	0	0
T160	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	36	0	0
T33	16702	0	0	0
T37	0	2	0	0
T38	3204	1	0	0
T39	7108	2	0	0
T41	659	1	0	0
T67	509	0	0	0
T78	13057	0	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T133	0	1	0	0
T134	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T155	0	2	0	0
T158	7909	0	0	0
T160	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	36	0	0
T33	16702	0	0	0
T37	0	2	0	0
T38	3204	1	0	0
T39	7108	2	0	0
T41	659	1	0	0
T67	509	0	0	0
T78	13057	0	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T133	0	1	0	0
T134	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T155	0	2	0	0
T158	7909	0	0	0
T160	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3020	0	0
T33	16702	0	0	0
T37	0	94	0	0
T38	3204	40	0	0
T39	7108	186	0	0
T41	659	82	0	0
T67	509	0	0	0
T78	13057	0	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T133	0	165	0	0
T134	0	39	0	0
T137	0	43	0	0
T138	0	211	0	0
T155	0	79	0	0
T158	7909	0	0	0
T160	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	17	0	0
T33	16702	0	0	0
T37	0	1	0	0
T38	3204	1	0	0
T39	7108	1	0	0
T41	659	0	0	0
T67	509	0	0	0
T78	13057	0	0	0
T91	6447	0	0	0
T100	0	1	0	0
T106	503	0	0	0
T107	11016	0	0	0
T133	0	1	0	0
T155	0	1	0	0
T158	7909	0	0	0
T160	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T34,T36,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T34,T36,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T34,T36,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T36,T38
1	0	Covered	T1,T13,T2
1	1	Covered	T34,T36,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T36,T38
0	1	Covered	T172
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T36,T38
0	1	Covered	T36,T38,T39
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T36,T38
1	-	Covered	T36,T38,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T36,T38
DetectSt	168	Covered	T34,T36,T38
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T34,T36,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T36,T38
DebounceSt->IdleSt	163	Covered	T34,T72,T173
DetectSt->IdleSt	186	Covered	T172
DetectSt->StableSt	191	Covered	T34,T36,T38
IdleSt->DebounceSt	148	Covered	T34,T36,T38
StableSt->IdleSt	206	Covered	T34,T36,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T36,T38
0	1	Covered	T34,T36,T38
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T36,T38
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T36,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T36,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T72,T173
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T36,T38
DetectSt	-	-	-	-	1	-	-	Covered	T172
DetectSt	-	-	-	-	0	1	-	Covered	T34,T36,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T38,T39
StableSt	-	-	-	-	-	-	0	Covered	T34,T36,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	161	0	0
CntIncr_A	5852696	4735	0	0
CntNoWrap_A	5852696	5185528	0	0
DetectStDropOut_A	5852696	1	0	0
DetectedOut_A	5852696	5894	0	0
DetectedPulseOut_A	5852696	75	0	0
DisabledIdleSt_A	5852696	5165633	0	0
DisabledNoDetection_A	5852696	5167989	0	0
EnterDebounceSt_A	5852696	85	0	0
EnterDetectSt_A	5852696	76	0	0
EnterStableSt_A	5852696	75	0	0
PulseIsPulse_A	5852696	75	0	0
StayInStableSt	5852696	5783	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5852696	3075	0	0
gen_low_level_sva.LowLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	161	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	3	0	0
T36	0	2	0	0
T38	0	6	0	0
T39	0	6	0	0
T64	500	0	0	0
T70	526	0	0	0
T72	0	1	0	0
T75	0	2	0	0
T89	36101	0	0	0
T136	0	2	0	0
T137	0	2	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	2	0	0
T174	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4735	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	144	0	0
T36	0	12	0	0
T38	0	258	0	0
T39	0	131	0	0
T64	500	0	0	0
T70	526	0	0	0
T72	0	46	0	0
T75	0	40	0	0
T89	36101	0	0	0
T136	0	65	0	0
T137	0	43	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	96	0	0
T174	0	51	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185528	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1	0	0
T172	1016	1	0	0
T175	755	0	0	0
T176	740	0	0	0
T177	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5894	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	114	0	0
T36	0	59	0	0
T38	0	219	0	0
T39	0	164	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	42	0	0
T89	36101	0	0	0
T136	0	108	0	0
T137	0	242	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	58	0	0
T160	0	125	0	0
T174	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	75	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T36	0	1	0	0
T38	0	3	0	0
T39	0	3	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	1	0	0
T89	36101	0	0	0
T136	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	1	0	0
T160	0	2	0	0
T174	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5165633	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5167989	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	85	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	2	0	0
T36	0	1	0	0
T38	0	3	0	0
T39	0	3	0	0
T64	500	0	0	0
T70	526	0	0	0
T72	0	1	0	0
T75	0	1	0	0
T89	36101	0	0	0
T136	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	1	0	0
T174	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	76	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T36	0	1	0	0
T38	0	3	0	0
T39	0	3	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	1	0	0
T89	36101	0	0	0
T136	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	1	0	0
T160	0	2	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	75	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T36	0	1	0	0
T38	0	3	0	0
T39	0	3	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	1	0	0
T89	36101	0	0	0
T136	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	1	0	0
T160	0	2	0	0
T174	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	75	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T36	0	1	0	0
T38	0	3	0	0
T39	0	3	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	1	0	0
T89	36101	0	0	0
T136	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	1	0	0
T160	0	2	0	0
T174	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5783	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	112	0	0
T36	0	58	0	0
T38	0	215	0	0
T39	0	160	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	40	0	0
T89	36101	0	0	0
T136	0	106	0	0
T137	0	241	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	57	0	0
T160	0	122	0	0
T174	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3075	0	0
T2	23644	0	0	0
T3	1479	2	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T13	505	6	0	0
T14	493	5	0	0
T15	644	2	0	0
T22	0	9	0	0
T51	422	2	0	0
T55	0	5	0	0
T56	0	4	0	0
T61	405	0	0	0
T62	0	7	0	0
T63	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	38	0	0
T33	16702	0	0	0
T36	2309	1	0	0
T38	3204	2	0	0
T39	7108	2	0	0
T77	11495	0	0	0
T87	0	1	0	0
T132	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T178	421	0	0	0
T179	27818	0	0	0
T180	423	0	0	0
T181	525	0	0	0
T182	522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T10,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T10,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T10,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T34,T35
1	0	Covered	T1,T5,T13
1	1	Covered	T10,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T34,T35
0	1	Covered	T35,T136,T173
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T34,T35
0	1	Covered	T34,T35,T36
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T34,T35
1	-	Covered	T34,T35,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T34,T35
DetectSt	168	Covered	T10,T34,T35
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T10,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T34,T35
DebounceSt->IdleSt	163	Covered	T41,T183,T79
DetectSt->IdleSt	186	Covered	T35,T136,T173
DetectSt->StableSt	191	Covered	T10,T34,T35
IdleSt->DebounceSt	148	Covered	T10,T34,T35
StableSt->IdleSt	206	Covered	T34,T35,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T34,T35
0	1	Covered	T10,T34,T35
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T34,T35
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T183
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T35,T136,T173
DetectSt	-	-	-	-	0	1	-	Covered	T10,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T10,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	131	0	0
CntIncr_A	5852696	3544	0	0
CntNoWrap_A	5852696	5185558	0	0
DetectStDropOut_A	5852696	4	0	0
DetectedOut_A	5852696	4392	0	0
DetectedPulseOut_A	5852696	60	0	0
DisabledIdleSt_A	5852696	5169121	0	0
DisabledNoDetection_A	5852696	5171489	0	0
EnterDebounceSt_A	5852696	67	0	0
EnterDetectSt_A	5852696	64	0	0
EnterStableSt_A	5852696	60	0	0
PulseIsPulse_A	5852696	60	0	0
StayInStableSt	5852696	4310	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	131	0	0
T10	627	2	0	0
T22	513	0	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	8	0	0
T35	0	4	0	0
T36	0	4	0	0
T39	0	4	0	0
T41	0	3	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T133	0	4	0	0
T136	0	2	0	0
T157	0	4	0	0
T174	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3544	0	0
T10	627	60	0	0
T22	513	0	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	122	0	0
T35	0	62	0	0
T36	0	24	0	0
T39	0	66	0	0
T41	0	82	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T133	0	152	0	0
T136	0	65	0	0
T157	0	192	0	0
T174	0	51	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185558	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4	0	0
T35	16925	1	0	0
T46	648	0	0	0
T59	910	0	0	0
T66	497	0	0	0
T136	0	1	0	0
T173	0	1	0	0
T184	0	1	0	0
T185	524	0	0	0
T186	445	0	0	0
T187	427	0	0	0
T188	402	0	0	0
T189	507	0	0	0
T190	420	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4392	0	0
T10	627	58	0	0
T22	513	0	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	83	0	0
T35	0	15	0	0
T36	0	81	0	0
T39	0	208	0	0
T41	0	85	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T133	0	129	0	0
T155	0	74	0	0
T157	0	84	0	0
T174	0	34	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	60	0	0
T10	627	1	0	0
T22	513	0	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	4	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T133	0	2	0	0
T155	0	1	0	0
T157	0	2	0	0
T174	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5169121	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5171489	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	67	0	0
T10	627	1	0	0
T22	513	0	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	4	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T133	0	2	0	0
T136	0	1	0	0
T157	0	2	0	0
T174	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	64	0	0
T10	627	1	0	0
T22	513	0	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	4	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T133	0	2	0	0
T136	0	1	0	0
T157	0	2	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	60	0	0
T10	627	1	0	0
T22	513	0	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	4	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T133	0	2	0	0
T155	0	1	0	0
T157	0	2	0	0
T174	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	60	0	0
T10	627	1	0	0
T22	513	0	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	4	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T133	0	2	0	0
T155	0	1	0	0
T157	0	2	0	0
T174	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4310	0	0
T10	627	56	0	0
T22	513	0	0	0
T24	769	0	0	0
T25	754	0	0	0
T26	12294	0	0	0
T34	0	78	0	0
T35	0	14	0	0
T36	0	78	0	0
T39	0	205	0	0
T41	0	83	0	0
T43	4719	0	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T57	632	0	0	0
T133	0	127	0	0
T155	0	73	0	0
T157	0	81	0	0
T174	0	33	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	37	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T76	0	1	0	0
T89	36101	0	0	0
T133	0	2	0	0
T134	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T155	0	1	0	0
T157	0	1	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T34
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T35,T36
0	1	Covered	T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T35,T36
0	1	Covered	T35,T36,T38
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T35,T36
1	-	Covered	T35,T36,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T35,T36
DetectSt	168	Covered	T3,T35,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T35,T36
DebounceSt->IdleSt	163	Covered	T79
DetectSt->IdleSt	186	Covered	T83
DetectSt->StableSt	191	Covered	T3,T35,T36
IdleSt->DebounceSt	148	Covered	T3,T35,T36
StableSt->IdleSt	206	Covered	T35,T36,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T35,T36
0	1	Covered	T3,T35,T36
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T35,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T35,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T83
DetectSt	-	-	-	-	0	1	-	Covered	T3,T35,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T36,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T35,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	97	0	0
CntIncr_A	5852696	2552	0	0
CntNoWrap_A	5852696	5185592	0	0
DetectStDropOut_A	5852696	1	0	0
DetectedOut_A	5852696	3121	0	0
DetectedPulseOut_A	5852696	47	0	0
DisabledIdleSt_A	5852696	5166263	0	0
DisabledNoDetection_A	5852696	5168623	0	0
EnterDebounceSt_A	5852696	49	0	0
EnterDetectSt_A	5852696	48	0	0
EnterStableSt_A	5852696	47	0	0
PulseIsPulse_A	5852696	47	0	0
StayInStableSt	5852696	3048	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5852696	6722	0	0
gen_low_level_sva.LowLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	97	0	0
T3	1479	2	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T35	0	4	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T75	0	2	0	0
T133	0	4	0	0
T174	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	2552	0	0
T3	1479	35	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T35	0	62	0	0
T36	0	12	0	0
T37	0	54	0	0
T38	0	86	0	0
T40	0	35	0	0
T41	0	41	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T75	0	40	0	0
T133	0	152	0	0
T174	0	51	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185592	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	275	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1	0	0
T83	1234	1	0	0
T88	58295	0	0	0
T99	9216	0	0	0
T121	1112	0	0	0
T173	635	0	0	0
T191	426	0	0	0
T192	422	0	0	0
T193	408	0	0	0
T194	730	0	0	0
T195	534	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3121	0	0
T3	1479	98	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T35	0	83	0	0
T36	0	2	0	0
T37	0	87	0	0
T38	0	96	0	0
T40	0	108	0	0
T41	0	40	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T75	0	42	0	0
T133	0	81	0	0
T174	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	47	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T75	0	1	0	0
T133	0	2	0	0
T174	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5166263	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	25	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5168623	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	26	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	49	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T75	0	1	0	0
T133	0	2	0	0
T174	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	48	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T75	0	1	0	0
T133	0	2	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	47	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T75	0	1	0	0
T133	0	2	0	0
T174	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	47	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T75	0	1	0	0
T133	0	2	0	0
T174	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3048	0	0
T3	1479	96	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T35	0	80	0	0
T36	0	1	0	0
T37	0	84	0	0
T38	0	95	0	0
T40	0	107	0	0
T41	0	39	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T75	0	40	0	0
T133	0	78	0	0
T174	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	6722	0	0
T1	19470	31	0	0
T2	23644	10	0	0
T3	1479	2	0	0
T4	413	0	0	0
T5	7177	27	0	0
T6	1105	6	0	0
T7	13717	30	0	0
T8	0	10	0	0
T13	505	4	0	0
T14	493	5	0	0
T15	644	0	0	0
T51	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	20	0	0
T35	16925	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T46	648	0	0	0
T59	910	0	0	0
T66	497	0	0	0
T133	0	1	0	0
T137	0	2	0	0
T185	524	0	0	0
T186	445	0	0	0
T187	427	0	0	0
T188	402	0	0	0
T189	507	0	0	0
T190	420	0	0	0
T196	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T23,T34,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T23,T34,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T23,T34,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T23,T34,T36
1	0	Covered	T1,T5,T13
1	1	Covered	T23,T34,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T34,T38
0	1	Covered	T40,T156,T198
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T34,T38
0	1	Covered	T34,T38,T37
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T34,T38
1	-	Covered	T34,T38,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T23,T34,T36
DetectSt	168	Covered	T23,T34,T38
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T23,T34,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T23,T34,T38
DebounceSt->IdleSt	163	Covered	T36,T147,T79
DetectSt->IdleSt	186	Covered	T40,T156,T198
DetectSt->StableSt	191	Covered	T23,T34,T38
IdleSt->DebounceSt	148	Covered	T23,T34,T36
StableSt->IdleSt	206	Covered	T34,T38,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T34,T36
0	1	Covered	T23,T34,T36
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T23,T34,T38
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T34,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T34,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T147
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T34,T36
DetectSt	-	-	-	-	1	-	-	Covered	T40,T156,T198
DetectSt	-	-	-	-	0	1	-	Covered	T23,T34,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T38,T37
StableSt	-	-	-	-	-	-	0	Covered	T23,T34,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	157	0	0
CntIncr_A	5852696	4300	0	0
CntNoWrap_A	5852696	5185532	0	0
DetectStDropOut_A	5852696	3	0	0
DetectedOut_A	5852696	5795	0	0
DetectedPulseOut_A	5852696	74	0	0
DisabledIdleSt_A	5852696	5166255	0	0
DisabledNoDetection_A	5852696	5168617	0	0
EnterDebounceSt_A	5852696	80	0	0
EnterDetectSt_A	5852696	77	0	0
EnterStableSt_A	5852696	74	0	0
PulseIsPulse_A	5852696	74	0	0
StayInStableSt	5852696	5685	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	157	0	0
T23	632	2	0	0
T31	29436	0	0	0
T34	97591	6	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	2	0	0
T40	0	4	0	0
T45	4015	0	0	0
T68	507	0	0	0
T69	527	0	0	0
T89	36101	0	0	0
T133	0	4	0	0
T151	452	0	0	0
T152	811	0	0	0
T157	0	6	0	0
T199	0	4	0	0
T200	770	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4300	0	0
T23	632	82	0	0
T31	29436	0	0	0
T34	97591	164	0	0
T36	0	12	0	0
T37	0	27	0	0
T38	0	172	0	0
T39	0	65	0	0
T40	0	70	0	0
T45	4015	0	0	0
T68	507	0	0	0
T69	527	0	0	0
T89	36101	0	0	0
T133	0	145	0	0
T151	452	0	0	0
T152	811	0	0	0
T157	0	286	0	0
T199	0	112	0	0
T200	770	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185532	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3	0	0
T40	802	1	0	0
T84	14537	0	0	0
T133	10417	0	0	0
T156	0	1	0	0
T198	0	1	0	0
T201	876	0	0	0
T202	433	0	0	0
T203	423	0	0	0
T204	506	0	0	0
T205	494	0	0	0
T206	1347	0	0	0
T207	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5795	0	0
T23	632	44	0	0
T31	29436	0	0	0
T34	97591	392	0	0
T37	0	20	0	0
T38	0	122	0	0
T39	0	41	0	0
T40	0	111	0	0
T45	4015	0	0	0
T68	507	0	0	0
T69	527	0	0	0
T75	0	41	0	0
T89	36101	0	0	0
T133	0	405	0	0
T151	452	0	0	0
T152	811	0	0	0
T157	0	402	0	0
T199	0	149	0	0
T200	770	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	74	0	0
T23	632	1	0	0
T31	29436	0	0	0
T34	97591	3	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	4015	0	0	0
T68	507	0	0	0
T69	527	0	0	0
T75	0	1	0	0
T89	36101	0	0	0
T133	0	2	0	0
T151	452	0	0	0
T152	811	0	0	0
T157	0	3	0	0
T199	0	2	0	0
T200	770	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5166255	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5168617	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	80	0	0
T23	632	1	0	0
T31	29436	0	0	0
T34	97591	3	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T45	4015	0	0	0
T68	507	0	0	0
T69	527	0	0	0
T89	36101	0	0	0
T133	0	2	0	0
T151	452	0	0	0
T152	811	0	0	0
T157	0	3	0	0
T199	0	2	0	0
T200	770	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	77	0	0
T23	632	1	0	0
T31	29436	0	0	0
T34	97591	3	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T45	4015	0	0	0
T68	507	0	0	0
T69	527	0	0	0
T75	0	1	0	0
T89	36101	0	0	0
T133	0	2	0	0
T151	452	0	0	0
T152	811	0	0	0
T157	0	3	0	0
T199	0	2	0	0
T200	770	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	74	0	0
T23	632	1	0	0
T31	29436	0	0	0
T34	97591	3	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	4015	0	0	0
T68	507	0	0	0
T69	527	0	0	0
T75	0	1	0	0
T89	36101	0	0	0
T133	0	2	0	0
T151	452	0	0	0
T152	811	0	0	0
T157	0	3	0	0
T199	0	2	0	0
T200	770	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	74	0	0
T23	632	1	0	0
T31	29436	0	0	0
T34	97591	3	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	4015	0	0	0
T68	507	0	0	0
T69	527	0	0	0
T75	0	1	0	0
T89	36101	0	0	0
T133	0	2	0	0
T151	452	0	0	0
T152	811	0	0	0
T157	0	3	0	0
T199	0	2	0	0
T200	770	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5685	0	0
T23	632	42	0	0
T31	29436	0	0	0
T34	97591	388	0	0
T37	0	19	0	0
T38	0	119	0	0
T39	0	39	0	0
T40	0	109	0	0
T45	4015	0	0	0
T68	507	0	0	0
T69	527	0	0	0
T75	0	39	0	0
T89	36101	0	0	0
T133	0	402	0	0
T151	452	0	0	0
T152	811	0	0	0
T157	0	397	0	0
T199	0	146	0	0
T200	770	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	37	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T83	0	2	0	0
T89	36101	0	0	0
T133	0	1	0	0
T137	0	2	0	0
T138	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	1	0	0
T160	0	1	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T38,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T38,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T38,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T23,T34,T35
1	0	Covered	T1,T5,T13
1	1	Covered	T38,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T40
0	1	Covered	T111
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T40
0	1	Covered	T38,T40,T132
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T39,T40
1	-	Covered	T38,T40,T132

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T38,T39,T40
DetectSt	168	Covered	T38,T39,T40
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T38,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T39,T40
DebounceSt->IdleSt	163	Covered	T150,T79
DetectSt->IdleSt	186	Covered	T111
DetectSt->StableSt	191	Covered	T38,T39,T40
IdleSt->DebounceSt	148	Covered	T38,T39,T40
StableSt->IdleSt	206	Covered	T38,T39,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T38,T39,T40
0	1	Covered	T38,T39,T40
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T38,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T150
DebounceSt	-	0	0	-	-	-	-	Covered	T38,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T111
DetectSt	-	-	-	-	0	1	-	Covered	T38,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T40,T132
StableSt	-	-	-	-	-	-	0	Covered	T38,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	70	0	0
CntIncr_A	5852696	1706	0	0
CntNoWrap_A	5852696	5185619	0	0
DetectStDropOut_A	5852696	2	0	0
DetectedOut_A	5852696	2351	0	0
DetectedPulseOut_A	5852696	32	0	0
DisabledIdleSt_A	5852696	5169370	0	0
DisabledNoDetection_A	5852696	5171738	0	0
EnterDebounceSt_A	5852696	36	0	0
EnterDetectSt_A	5852696	34	0	0
EnterStableSt_A	5852696	32	0	0
PulseIsPulse_A	5852696	32	0	0
StayInStableSt	5852696	2303	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5852696	6456	0	0
gen_low_level_sva.LowLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	70	0	0
T33	16702	0	0	0
T38	3204	2	0	0
T39	7108	2	0	0
T40	0	2	0	0
T41	659	0	0	0
T67	509	0	0	0
T78	13057	0	0	0
T83	0	4	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T132	0	2	0	0
T138	0	2	0	0
T147	0	4	0	0
T158	7909	0	0	0
T159	0	2	0	0
T170	0	2	0	0
T197	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1706	0	0
T33	16702	0	0	0
T38	3204	86	0	0
T39	7108	33	0	0
T40	0	35	0	0
T41	659	0	0	0
T67	509	0	0	0
T78	13057	0	0	0
T83	0	186	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T132	0	23	0	0
T138	0	73	0	0
T147	0	26	0	0
T158	7909	0	0	0
T159	0	13	0	0
T170	0	12	0	0
T197	0	186	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185619	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	2	0	0
T111	702	2	0	0
T112	449	0	0	0
T113	740	0	0	0
T114	5895	0	0	0
T115	412	0	0	0
T116	504	0	0	0
T208	530	0	0	0
T209	739	0	0	0
T210	664	0	0	0
T211	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	2351	0	0
T33	16702	0	0	0
T38	3204	310	0	0
T39	7108	279	0	0
T40	0	175	0	0
T41	659	0	0	0
T67	509	0	0	0
T78	13057	0	0	0
T83	0	180	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T132	0	43	0	0
T138	0	44	0	0
T147	0	82	0	0
T158	7909	0	0	0
T159	0	68	0	0
T170	0	10	0	0
T197	0	89	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	32	0	0
T33	16702	0	0	0
T38	3204	1	0	0
T39	7108	1	0	0
T40	0	1	0	0
T41	659	0	0	0
T67	509	0	0	0
T78	13057	0	0	0
T83	0	2	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T132	0	1	0	0
T138	0	1	0	0
T147	0	2	0	0
T158	7909	0	0	0
T159	0	1	0	0
T170	0	1	0	0
T197	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5169370	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5171738	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	36	0	0
T33	16702	0	0	0
T38	3204	1	0	0
T39	7108	1	0	0
T40	0	1	0	0
T41	659	0	0	0
T67	509	0	0	0
T78	13057	0	0	0
T83	0	2	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T132	0	1	0	0
T138	0	1	0	0
T147	0	2	0	0
T158	7909	0	0	0
T159	0	1	0	0
T170	0	1	0	0
T197	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	34	0	0
T33	16702	0	0	0
T38	3204	1	0	0
T39	7108	1	0	0
T40	0	1	0	0
T41	659	0	0	0
T67	509	0	0	0
T78	13057	0	0	0
T83	0	2	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T132	0	1	0	0
T138	0	1	0	0
T147	0	2	0	0
T158	7909	0	0	0
T159	0	1	0	0
T170	0	1	0	0
T197	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	32	0	0
T33	16702	0	0	0
T38	3204	1	0	0
T39	7108	1	0	0
T40	0	1	0	0
T41	659	0	0	0
T67	509	0	0	0
T78	13057	0	0	0
T83	0	2	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T132	0	1	0	0
T138	0	1	0	0
T147	0	2	0	0
T158	7909	0	0	0
T159	0	1	0	0
T170	0	1	0	0
T197	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	32	0	0
T33	16702	0	0	0
T38	3204	1	0	0
T39	7108	1	0	0
T40	0	1	0	0
T41	659	0	0	0
T67	509	0	0	0
T78	13057	0	0	0
T83	0	2	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T132	0	1	0	0
T138	0	1	0	0
T147	0	2	0	0
T158	7909	0	0	0
T159	0	1	0	0
T170	0	1	0	0
T197	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	2303	0	0
T33	16702	0	0	0
T38	3204	309	0	0
T39	7108	277	0	0
T40	0	174	0	0
T41	659	0	0	0
T67	509	0	0	0
T78	13057	0	0	0
T83	0	178	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T132	0	42	0	0
T138	0	42	0	0
T147	0	79	0	0
T158	7909	0	0	0
T159	0	67	0	0
T170	0	9	0	0
T197	0	86	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	6456	0	0
T1	19470	35	0	0
T2	23644	14	0	0
T3	1479	3	0	0
T4	413	0	0	0
T5	7177	24	0	0
T6	1105	0	0	0
T7	13717	27	0	0
T13	505	5	0	0
T14	493	5	0	0
T15	644	0	0	0
T51	0	5	0	0
T62	0	5	0	0
T63	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	15	0	0
T33	16702	0	0	0
T38	3204	1	0	0
T39	7108	0	0	0
T40	0	1	0	0
T41	659	0	0	0
T67	509	0	0	0
T78	13057	0	0	0
T83	0	2	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T113	0	2	0	0
T132	0	1	0	0
T147	0	1	0	0
T158	7909	0	0	0
T159	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T197	0	1	0	0