Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T34,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T34,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T34,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T34,T35
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T34,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T36
0	1	Covered	T212
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T36
0	1	Covered	T34,T36,T38
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T34,T36
1	-	Covered	T34,T36,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T34,T36
DetectSt	168	Covered	T3,T34,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T34,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T34,T36
DebounceSt->IdleSt	163	Covered	T148,T79
DetectSt->IdleSt	186	Covered	T212
DetectSt->StableSt	191	Covered	T3,T34,T36
IdleSt->DebounceSt	148	Covered	T3,T34,T36
StableSt->IdleSt	206	Covered	T34,T36,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T34,T36
0	1	Covered	T3,T34,T36
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T34,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T34,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T34,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T148
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T34,T36
DetectSt	-	-	-	-	1	-	-	Covered	T212
DetectSt	-	-	-	-	0	1	-	Covered	T3,T34,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T36,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T34,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	113	0	0
CntIncr_A	5852696	2887	0	0
CntNoWrap_A	5852696	5185576	0	0
DetectStDropOut_A	5852696	1	0	0
DetectedOut_A	5852696	6034	0	0
DetectedPulseOut_A	5852696	54	0	0
DisabledIdleSt_A	5852696	5168893	0	0
DisabledNoDetection_A	5852696	5171260	0	0
EnterDebounceSt_A	5852696	58	0	0
EnterDetectSt_A	5852696	55	0	0
EnterStableSt_A	5852696	54	0	0
PulseIsPulse_A	5852696	54	0	0
StayInStableSt	5852696	5956	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	113	0	0
T3	1479	2	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T72	0	2	0	0
T155	0	2	0	0
T157	0	2	0	0
T199	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	2887	0	0
T3	1479	35	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	15	0	0
T36	0	12	0	0
T37	0	27	0	0
T38	0	86	0	0
T39	0	33	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T72	0	46	0	0
T155	0	19	0	0
T157	0	95	0	0
T199	0	112	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185576	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	275	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1	0	0
T212	575	1	0	0
T213	5366	0	0	0
T214	505	0	0	0
T215	661	0	0	0
T216	548	0	0	0
T217	38482	0	0	0
T218	697	0	0	0
T219	2799	0	0	0
T220	503	0	0	0
T221	695	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	6034	0	0
T3	1479	98	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	39	0	0
T36	0	58	0	0
T37	0	165	0	0
T38	0	264	0	0
T39	0	174	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T72	0	62	0	0
T155	0	84	0	0
T157	0	442	0	0
T199	0	253	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	54	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T72	0	1	0	0
T155	0	1	0	0
T157	0	1	0	0
T199	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5168893	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	25	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5171260	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	26	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	58	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T72	0	1	0	0
T155	0	1	0	0
T157	0	1	0	0
T199	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	55	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T72	0	1	0	0
T155	0	1	0	0
T157	0	1	0	0
T199	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	54	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T72	0	1	0	0
T155	0	1	0	0
T157	0	1	0	0
T199	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	54	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T72	0	1	0	0
T155	0	1	0	0
T157	0	1	0	0
T199	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5956	0	0
T3	1479	96	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	38	0	0
T36	0	57	0	0
T37	0	164	0	0
T38	0	263	0	0
T39	0	173	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T72	0	60	0	0
T155	0	83	0	0
T157	0	440	0	0
T199	0	250	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	29	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T82	0	1	0	0
T83	0	2	0	0
T89	36101	0	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T155	0	1	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T34,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T34,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T34,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T34,T35
1	0	Covered	T1,T5,T13
1	1	Covered	T34,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T36,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T36,T37
0	1	Covered	T34,T40,T83
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T36,T37
1	-	Covered	T34,T40,T83

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T36,T37
DetectSt	168	Covered	T34,T36,T37
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T34,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T36,T37
DebounceSt->IdleSt	163	Covered	T222,T111,T79
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T34,T36,T37
IdleSt->DebounceSt	148	Covered	T34,T36,T37
StableSt->IdleSt	206	Covered	T34,T36,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T36,T37
0	1	Covered	T34,T36,T37
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T36,T37
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T222,T111,T172
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T36,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T34,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T40,T83
StableSt	-	-	-	-	-	-	0	Covered	T34,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	77	0	0
CntIncr_A	5852696	2294	0	0
CntNoWrap_A	5852696	5185612	0	0
DetectStDropOut_A	5852696	0	0	0
DetectedOut_A	5852696	2242	0	0
DetectedPulseOut_A	5852696	36	0	0
DisabledIdleSt_A	5852696	5166316	0	0
DisabledNoDetection_A	5852696	5168675	0	0
EnterDebounceSt_A	5852696	41	0	0
EnterDetectSt_A	5852696	36	0	0
EnterStableSt_A	5852696	36	0	0
PulseIsPulse_A	5852696	36	0	0
StayInStableSt	5852696	2184	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5852696	6385	0	0
gen_low_level_sva.LowLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	77	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	0	4	0	0
T64	500	0	0	0
T70	526	0	0	0
T83	0	4	0	0
T89	36101	0	0	0
T133	0	2	0	0
T137	0	2	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T155	0	2	0	0
T159	0	2	0	0
T174	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	2294	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	77	0	0
T36	0	12	0	0
T37	0	27	0	0
T40	0	70	0	0
T64	500	0	0	0
T70	526	0	0	0
T83	0	186	0	0
T89	36101	0	0	0
T133	0	76	0	0
T137	0	43	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T155	0	19	0	0
T159	0	13	0	0
T174	0	51	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185612	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	2242	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	40	0	0
T36	0	40	0	0
T37	0	43	0	0
T40	0	64	0	0
T64	500	0	0	0
T70	526	0	0	0
T83	0	81	0	0
T89	36101	0	0	0
T133	0	38	0	0
T137	0	44	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T155	0	38	0	0
T159	0	47	0	0
T174	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	36	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	2	0	0
T64	500	0	0	0
T70	526	0	0	0
T83	0	2	0	0
T89	36101	0	0	0
T133	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T155	0	1	0	0
T159	0	1	0	0
T174	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5166316	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	25	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5168675	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	26	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	41	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	2	0	0
T64	500	0	0	0
T70	526	0	0	0
T83	0	2	0	0
T89	36101	0	0	0
T133	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T155	0	1	0	0
T159	0	1	0	0
T174	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	36	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	2	0	0
T64	500	0	0	0
T70	526	0	0	0
T83	0	2	0	0
T89	36101	0	0	0
T133	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T155	0	1	0	0
T159	0	1	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	36	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	2	0	0
T64	500	0	0	0
T70	526	0	0	0
T83	0	2	0	0
T89	36101	0	0	0
T133	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T155	0	1	0	0
T159	0	1	0	0
T174	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	36	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	2	0	0
T64	500	0	0	0
T70	526	0	0	0
T83	0	2	0	0
T89	36101	0	0	0
T133	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T155	0	1	0	0
T159	0	1	0	0
T174	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	2184	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	39	0	0
T36	0	38	0	0
T37	0	41	0	0
T40	0	61	0	0
T64	500	0	0	0
T70	526	0	0	0
T83	0	78	0	0
T89	36101	0	0	0
T133	0	36	0	0
T137	0	42	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T155	0	36	0	0
T159	0	45	0	0
T174	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	6385	0	0
T1	19470	26	0	0
T2	23644	9	0	0
T3	1479	1	0	0
T4	413	0	0	0
T5	7177	28	0	0
T6	1105	0	0	0
T7	13717	27	0	0
T13	505	3	0	0
T14	493	10	0	0
T15	644	0	0	0
T51	0	3	0	0
T62	0	5	0	0
T63	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	13	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T40	0	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T83	0	1	0	0
T89	36101	0	0	0
T111	0	1	0	0
T148	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T196	0	1	0	0
T223	0	1	0	0
T224	0	1	0	0
T225	0	1	0	0
T226	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T34,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T34,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T34,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T1,T5,T13
1	1	Covered	T34,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T41,T137
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T35,T36
1	-	Covered	T34,T35,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T35,T36
DetectSt	168	Covered	T34,T35,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T34,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T35,T36
DebounceSt->IdleSt	163	Covered	T222,T171,T150
DetectSt->IdleSt	186	Covered	T41,T137
DetectSt->StableSt	191	Covered	T34,T35,T36
IdleSt->DebounceSt	148	Covered	T34,T35,T36
StableSt->IdleSt	206	Covered	T34,T35,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T222,T150,T172
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T41,T137
DetectSt	-	-	-	-	0	1	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T34,T35,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	138	0	0
CntIncr_A	5852696	4189	0	0
CntNoWrap_A	5852696	5185551	0	0
DetectStDropOut_A	5852696	2	0	0
DetectedOut_A	5852696	4855	0	0
DetectedPulseOut_A	5852696	65	0	0
DisabledIdleSt_A	5852696	5166783	0	0
DisabledNoDetection_A	5852696	5169145	0	0
EnterDebounceSt_A	5852696	72	0	0
EnterDetectSt_A	5852696	67	0	0
EnterStableSt_A	5852696	65	0	0
PulseIsPulse_A	5852696	65	0	0
StayInStableSt	5852696	4759	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	138	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	4	0	0
T35	0	2	0	0
T36	0	4	0	0
T38	0	6	0	0
T39	0	8	0	0
T41	0	4	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	2	0	0
T89	36101	0	0	0
T133	0	4	0	0
T134	0	2	0	0
T137	0	2	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4189	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	99	0	0
T35	0	31	0	0
T36	0	24	0	0
T38	0	256	0	0
T39	0	164	0	0
T41	0	82	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	40	0	0
T89	36101	0	0	0
T133	0	152	0	0
T134	0	96	0	0
T137	0	43	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185551	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	2	0	0
T41	659	1	0	0
T67	509	0	0	0
T78	13057	0	0	0
T91	6447	0	0	0
T106	503	0	0	0
T107	11016	0	0	0
T137	0	1	0	0
T158	7909	0	0	0
T227	10235	0	0	0
T228	491	0	0	0
T229	862	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4855	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	61	0	0
T35	0	121	0	0
T36	0	83	0	0
T38	0	547	0	0
T39	0	161	0	0
T41	0	84	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	42	0	0
T89	36101	0	0	0
T133	0	112	0	0
T134	0	136	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T160	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	65	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	3	0	0
T39	0	4	0	0
T41	0	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	1	0	0
T89	36101	0	0	0
T133	0	2	0	0
T134	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T160	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5166783	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5169145	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	72	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	3	0	0
T39	0	4	0	0
T41	0	2	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	1	0	0
T89	36101	0	0	0
T133	0	2	0	0
T134	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	67	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	3	0	0
T39	0	4	0	0
T41	0	2	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	1	0	0
T89	36101	0	0	0
T133	0	2	0	0
T134	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	65	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	3	0	0
T39	0	4	0	0
T41	0	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	1	0	0
T89	36101	0	0	0
T133	0	2	0	0
T134	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T160	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	65	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	3	0	0
T39	0	4	0	0
T41	0	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	1	0	0
T89	36101	0	0	0
T133	0	2	0	0
T134	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T160	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4759	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	58	0	0
T35	0	120	0	0
T36	0	80	0	0
T38	0	542	0	0
T39	0	155	0	0
T41	0	82	0	0
T64	500	0	0	0
T70	526	0	0	0
T75	0	40	0	0
T89	36101	0	0	0
T133	0	109	0	0
T134	0	135	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T160	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	33	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T64	500	0	0	0
T70	526	0	0	0
T89	36101	0	0	0
T123	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T138	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T160	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T34,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T34,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T34,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T34,T35
1	0	Covered	T1,T5,T13
1	1	Covered	T34,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T150
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T38
0	1	Covered	T34,T36,T38
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T35,T38
1	-	Covered	T34,T36,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T35,T36
DetectSt	168	Covered	T34,T35,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T34,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T35,T36
DebounceSt->IdleSt	163	Covered	T79
DetectSt->IdleSt	186	Covered	T150
DetectSt->StableSt	191	Covered	T34,T35,T36
IdleSt->DebounceSt	148	Covered	T34,T35,T36
StableSt->IdleSt	206	Covered	T34,T35,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T150
DetectSt	-	-	-	-	0	1	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T36,T38
StableSt	-	-	-	-	-	-	0	Covered	T34,T35,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	83	0	0
CntIncr_A	5852696	2162	0	0
CntNoWrap_A	5852696	5185606	0	0
DetectStDropOut_A	5852696	1	0	0
DetectedOut_A	5852696	3151	0	0
DetectedPulseOut_A	5852696	40	0	0
DisabledIdleSt_A	5852696	5167877	0	0
DisabledNoDetection_A	5852696	5170241	0	0
EnterDebounceSt_A	5852696	42	0	0
EnterDetectSt_A	5852696	41	0	0
EnterStableSt_A	5852696	40	0	0
PulseIsPulse_A	5852696	40	0	0
StayInStableSt	5852696	3089	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5852696	6446	0	0
gen_low_level_sva.LowLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	83	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	6	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T64	500	0	0	0
T70	526	0	0	0
T89	36101	0	0	0
T133	0	2	0	0
T136	0	2	0	0
T137	0	2	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	2162	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	107	0	0
T35	0	31	0	0
T36	0	12	0	0
T37	0	27	0	0
T38	0	86	0	0
T40	0	35	0	0
T64	500	0	0	0
T70	526	0	0	0
T89	36101	0	0	0
T133	0	69	0	0
T136	0	65	0	0
T137	0	43	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	95	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185606	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1	0	0
T150	24173	1	0	0
T230	526	0	0	0
T231	1877	0	0	0
T232	527	0	0	0
T233	1004	0	0	0
T234	620	0	0	0
T235	505	0	0	0
T236	2109	0	0	0
T237	18081	0	0	0
T238	15186	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3151	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	416	0	0
T35	0	40	0	0
T36	0	1	0	0
T37	0	168	0	0
T38	0	41	0	0
T40	0	110	0	0
T64	500	0	0	0
T70	526	0	0	0
T89	36101	0	0	0
T133	0	166	0	0
T136	0	42	0	0
T137	0	204	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	181	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	40	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T89	36101	0	0	0
T133	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5167877	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5170241	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	42	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T89	36101	0	0	0
T133	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	41	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T89	36101	0	0	0
T133	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	40	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T89	36101	0	0	0
T133	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	40	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T89	36101	0	0	0
T133	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3089	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	411	0	0
T35	0	38	0	0
T37	0	166	0	0
T38	0	40	0	0
T40	0	109	0	0
T64	500	0	0	0
T70	526	0	0	0
T89	36101	0	0	0
T133	0	165	0	0
T134	0	54	0	0
T136	0	40	0	0
T137	0	202	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T157	0	179	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	6446	0	0
T1	19470	25	0	0
T2	23644	14	0	0
T3	1479	5	0	0
T4	413	0	0	0
T5	7177	35	0	0
T6	1105	0	0	0
T7	13717	23	0	0
T13	505	6	0	0
T14	493	7	0	0
T15	644	0	0	0
T51	0	1	0	0
T62	0	3	0	0
T63	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	17	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T89	36101	0	0	0
T113	0	1	0	0
T133	0	1	0	0
T149	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T159	0	1	0	0
T226	0	1	0	0
T239	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T34,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T34,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T34,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T34,T38
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T34,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T38
0	1	Covered	T34,T132,T197
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T38
0	1	Covered	T3,T34,T38
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T34,T38
1	-	Covered	T3,T34,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T34,T38
DetectSt	168	Covered	T3,T34,T38
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T34,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T34,T38
DebounceSt->IdleSt	163	Covered	T79,T176
DetectSt->IdleSt	186	Covered	T34,T132,T197
DetectSt->StableSt	191	Covered	T3,T34,T38
IdleSt->DebounceSt	148	Covered	T3,T34,T38
StableSt->IdleSt	206	Covered	T3,T34,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T34,T38
0	1	Covered	T3,T34,T38
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T34,T38
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T34,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T34,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T176
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T34,T38
DetectSt	-	-	-	-	1	-	-	Covered	T34,T132,T197
DetectSt	-	-	-	-	0	1	-	Covered	T3,T34,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T34,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T34,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	136	0	0
CntIncr_A	5852696	4224	0	0
CntNoWrap_A	5852696	5185553	0	0
DetectStDropOut_A	5852696	3	0	0
DetectedOut_A	5852696	5571	0	0
DetectedPulseOut_A	5852696	64	0	0
DisabledIdleSt_A	5852696	5165862	0	0
DisabledNoDetection_A	5852696	5168229	0	0
EnterDebounceSt_A	5852696	69	0	0
EnterDetectSt_A	5852696	67	0	0
EnterStableSt_A	5852696	64	0	0
PulseIsPulse_A	5852696	64	0	0
StayInStableSt	5852696	5483	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	136	0	0
T3	1479	2	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	6	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	4	0	0
T40	0	2	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T137	0	2	0	0
T157	0	2	0	0
T174	0	2	0	0
T199	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4224	0	0
T3	1479	35	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	226	0	0
T37	0	27	0	0
T38	0	170	0	0
T39	0	66	0	0
T40	0	35	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T137	0	43	0	0
T157	0	95	0	0
T174	0	51	0	0
T199	0	168	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185553	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	275	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T89	36101	0	0	0
T132	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T197	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5571	0	0
T3	1479	44	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	183	0	0
T37	0	44	0	0
T38	0	281	0	0
T39	0	189	0	0
T40	0	98	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T137	0	154	0	0
T157	0	443	0	0
T174	0	128	0	0
T199	0	74	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	64	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T137	0	1	0	0
T157	0	1	0	0
T174	0	1	0	0
T199	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5165862	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	25	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5168229	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	26	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	69	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	3	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T137	0	1	0	0
T157	0	1	0	0
T174	0	1	0	0
T199	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	67	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	3	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T137	0	1	0	0
T157	0	1	0	0
T174	0	1	0	0
T199	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	64	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T137	0	1	0	0
T157	0	1	0	0
T174	0	1	0	0
T199	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	64	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T137	0	1	0	0
T157	0	1	0	0
T174	0	1	0	0
T199	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5483	0	0
T3	1479	43	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	180	0	0
T37	0	43	0	0
T38	0	278	0	0
T39	0	186	0	0
T40	0	97	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T137	0	153	0	0
T157	0	441	0	0
T174	0	126	0	0
T199	0	70	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	39	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T134	0	1	0	0
T137	0	1	0	0
T138	0	2	0	0
T199	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T23,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T23,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T23,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T23
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T23,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T34
0	1	Covered	T34,T157,T111
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T23,T34
1	-	Covered	T34,T157,T111

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T23,T34
DetectSt	168	Covered	T3,T23,T34
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T23,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T23,T34
DebounceSt->IdleSt	163	Covered	T102,T150,T79
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T23,T34
IdleSt->DebounceSt	148	Covered	T3,T23,T34
StableSt->IdleSt	206	Covered	T34,T35,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T23,T34
0	1	Covered	T3,T23,T34
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T23,T34
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T23,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T23,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T102,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T23,T34
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T23,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T157,T54
StableSt	-	-	-	-	-	-	0	Covered	T3,T23,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	55	0	0
CntIncr_A	5852696	1437	0	0
CntNoWrap_A	5852696	5185634	0	0
DetectStDropOut_A	5852696	0	0	0
DetectedOut_A	5852696	1942	0	0
DetectedPulseOut_A	5852696	26	0	0
DisabledIdleSt_A	5852696	5171505	0	0
DisabledNoDetection_A	5852696	5173872	0	0
EnterDebounceSt_A	5852696	29	0	0
EnterDetectSt_A	5852696	26	0	0
EnterStableSt_A	5852696	26	0	0
PulseIsPulse_A	5852696	26	0	0
StayInStableSt	5852696	1897	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5852696	7039	0	0
gen_low_level_sva.LowLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	6	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	55	0	0
T3	1479	2	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T23	0	2	0	0
T34	0	6	0	0
T35	0	2	0	0
T36	0	2	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T76	0	2	0	0
T87	0	4	0	0
T157	0	2	0	0
T196	0	2	0	0
T224	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1437	0	0
T3	1479	35	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T23	0	82	0	0
T34	0	164	0	0
T35	0	31	0	0
T36	0	12	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T76	0	67	0	0
T87	0	49	0	0
T157	0	96	0	0
T196	0	27	0	0
T224	0	73	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5185634	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	275	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1942	0	0
T3	1479	97	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T23	0	44	0	0
T34	0	120	0	0
T35	0	41	0	0
T36	0	110	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T76	0	178	0	0
T87	0	87	0	0
T157	0	59	0	0
T196	0	77	0	0
T224	0	107	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	26	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T23	0	1	0	0
T34	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T76	0	1	0	0
T87	0	2	0	0
T157	0	1	0	0
T196	0	1	0	0
T224	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5171505	0	0
T1	19470	19027	0	0
T2	23644	23181	0	0
T3	1479	25	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5173872	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	26	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	29	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T23	0	1	0	0
T34	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T76	0	1	0	0
T87	0	2	0	0
T157	0	1	0	0
T196	0	1	0	0
T224	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	26	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T23	0	1	0	0
T34	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T76	0	1	0	0
T87	0	2	0	0
T157	0	1	0	0
T196	0	1	0	0
T224	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	26	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T23	0	1	0	0
T34	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T76	0	1	0	0
T87	0	2	0	0
T157	0	1	0	0
T196	0	1	0	0
T224	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	26	0	0
T3	1479	1	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T23	0	1	0	0
T34	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T76	0	1	0	0
T87	0	2	0	0
T157	0	1	0	0
T196	0	1	0	0
T224	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1897	0	0
T3	1479	95	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T23	0	42	0	0
T34	0	115	0	0
T35	0	39	0	0
T36	0	108	0	0
T51	422	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T76	0	176	0	0
T87	0	83	0	0
T157	0	58	0	0
T196	0	75	0	0
T224	0	105	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	7039	0	0
T1	19470	27	0	0
T2	23644	10	0	0
T3	1479	3	0	0
T4	413	0	0	0
T5	7177	20	0	0
T6	1105	6	0	0
T7	13717	35	0	0
T8	0	10	0	0
T9	0	7	0	0
T13	505	6	0	0
T14	493	9	0	0
T15	644	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	6	0	0
T21	494	0	0	0
T31	29436	0	0	0
T34	97591	1	0	0
T64	500	0	0	0
T70	526	0	0	0
T89	36101	0	0	0
T111	0	1	0	0
T129	0	1	0	0
T151	452	0	0	0
T152	811	0	0	0
T153	406	0	0	0
T154	402	0	0	0
T156	0	1	0	0
T157	0	1	0	0
T176	0	1	0	0