Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T5,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T7
0	1	Covered	T43,T44,T80
1	0	Covered	T80,T91,T93

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T7
0	1	Covered	T1,T5,T7
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T7
1	-	Covered	T1,T5,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T7
DetectSt	168	Covered	T1,T5,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T5,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T7
DebounceSt->IdleSt	163	Covered	T45,T240,T54
DetectSt->IdleSt	186	Covered	T43,T44,T80
DetectSt->StableSt	191	Covered	T1,T5,T7
IdleSt->DebounceSt	148	Covered	T1,T5,T7
StableSt->IdleSt	206	Covered	T1,T5,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T7
0	1	Covered	T1,T5,T7
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T240,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T7
DetectSt	-	-	-	-	1	-	-	Covered	T43,T44,T80
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T7
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	3016	0	0
CntIncr_A	5852696	110652	0	0
CntNoWrap_A	5852696	5182673	0	0
DetectStDropOut_A	5852696	363	0	0
DetectedOut_A	5852696	77166	0	0
DetectedPulseOut_A	5852696	927	0	0
DisabledIdleSt_A	5852696	4695478	0	0
DisabledNoDetection_A	5852696	4697680	0	0
EnterDebounceSt_A	5852696	1521	0	0
EnterDetectSt_A	5852696	1496	0	0
EnterStableSt_A	5852696	927	0	0
PulseIsPulse_A	5852696	927	0	0
StayInStableSt	5852696	76118	0	0
gen_high_event_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	805	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3016	0	0
T1	19470	14	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	10	0	0
T6	1105	0	0	0
T7	13717	18	0	0
T12	0	30	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	60	0	0
T30	0	58	0	0
T42	0	48	0	0
T43	0	12	0	0
T44	0	30	0	0
T45	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	110652	0	0
T1	19470	329	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	240	0	0
T6	1105	0	0	0
T7	13717	522	0	0
T12	0	765	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	1200	0	0
T30	0	2378	0	0
T42	0	1128	0	0
T43	0	247	0	0
T44	0	789	0	0
T45	0	179	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5182673	0	0
T1	19470	19013	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6766	0	0
T6	1105	704	0	0
T7	13717	13282	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	363	0	0
T11	2146	0	0	0
T20	496	0	0	0
T22	513	0	0	0
T24	769	0	0	0
T25	754	0	0	0
T42	7244	0	0	0
T43	4719	6	0	0
T44	0	15	0	0
T52	415	0	0	0
T53	410	0	0	0
T56	552	0	0	0
T80	0	20	0	0
T91	0	9	0	0
T92	0	8	0	0
T93	0	9	0	0
T94	0	12	0	0
T95	0	6	0	0
T96	0	4	0	0
T97	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	77166	0	0
T1	19470	432	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	96	0	0
T6	1105	0	0	0
T7	13717	734	0	0
T12	0	1131	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	978	0	0
T30	0	1395	0	0
T32	0	976	0	0
T42	0	878	0	0
T89	0	3854	0	0
T241	0	1827	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	927	0	0
T1	19470	7	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	5	0	0
T6	1105	0	0	0
T7	13717	9	0	0
T12	0	15	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	30	0	0
T30	0	29	0	0
T32	0	12	0	0
T42	0	24	0	0
T89	0	21	0	0
T241	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4695478	0	0
T1	19470	15674	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	3296	0	0
T6	1105	704	0	0
T7	13717	9078	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4697680	0	0
T1	19470	15678	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	3296	0	0
T6	1105	705	0	0
T7	13717	9079	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1521	0	0
T1	19470	7	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	5	0	0
T6	1105	0	0	0
T7	13717	9	0	0
T12	0	15	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	30	0	0
T30	0	29	0	0
T42	0	24	0	0
T43	0	6	0	0
T44	0	15	0	0
T45	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1496	0	0
T1	19470	7	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	5	0	0
T6	1105	0	0	0
T7	13717	9	0	0
T12	0	15	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	30	0	0
T30	0	29	0	0
T42	0	24	0	0
T43	0	6	0	0
T44	0	15	0	0
T89	0	21	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	927	0	0
T1	19470	7	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	5	0	0
T6	1105	0	0	0
T7	13717	9	0	0
T12	0	15	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	30	0	0
T30	0	29	0	0
T32	0	12	0	0
T42	0	24	0	0
T89	0	21	0	0
T241	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	927	0	0
T1	19470	7	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	5	0	0
T6	1105	0	0	0
T7	13717	9	0	0
T12	0	15	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	30	0	0
T30	0	29	0	0
T32	0	12	0	0
T42	0	24	0	0
T89	0	21	0	0
T241	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	76118	0	0
T1	19470	423	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	91	0	0
T6	1105	0	0	0
T7	13717	723	0	0
T12	0	1114	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	946	0	0
T30	0	1364	0	0
T32	0	959	0	0
T42	0	854	0	0
T89	0	3827	0	0
T241	0	1820	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	805	0	0
T1	19470	5	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	5	0	0
T6	1105	0	0	0
T7	13717	7	0	0
T12	0	13	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	28	0	0
T30	0	27	0	0
T32	0	7	0	0
T42	0	24	0	0
T89	0	15	0	0
T241	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T77,T78,T50
1	0	Covered	T54,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T54,T81,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T7
1	-	Covered	T1,T2,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T7
DetectSt	168	Covered	T1,T2,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T2,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T7
DebounceSt->IdleSt	163	Covered	T2,T34,T31
DetectSt->IdleSt	186	Covered	T77,T78,T50
DetectSt->StableSt	191	Covered	T1,T2,T7
IdleSt->DebounceSt	148	Covered	T1,T2,T7
StableSt->IdleSt	206	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T34,T31
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T77,T78,T50
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	936	0	0
CntIncr_A	5852696	43994	0	0
CntNoWrap_A	5852696	5184753	0	0
DetectStDropOut_A	5852696	56	0	0
DetectedOut_A	5852696	16737	0	0
DetectedPulseOut_A	5852696	358	0	0
DisabledIdleSt_A	5852696	4857232	0	0
DisabledNoDetection_A	5852696	4858944	0	0
EnterDebounceSt_A	5852696	520	0	0
EnterDetectSt_A	5852696	418	0	0
EnterStableSt_A	5852696	358	0	0
PulseIsPulse_A	5852696	358	0	0
StayInStableSt	5852696	16343	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	316	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	936	0	0
T1	19470	4	0	0
T2	23644	19	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	4	0	0
T12	0	2	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	6	0	0
T29	0	8	0	0
T30	0	4	0	0
T31	0	6	0	0
T34	0	2	0	0
T89	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	43994	0	0
T1	19470	106	0	0
T2	23644	784	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	130	0	0
T12	0	52	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	165	0	0
T29	0	313	0	0
T30	0	168	0	0
T31	0	388	0	0
T34	0	40	0	0
T89	0	808	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5184753	0	0
T1	19470	19023	0	0
T2	23644	23162	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13296	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	56	0	0
T33	16702	0	0	0
T38	3204	0	0	0
T39	7108	0	0	0
T41	659	0	0	0
T50	0	1	0	0
T67	509	0	0	0
T77	11495	2	0	0
T78	13057	7	0	0
T91	6447	0	0	0
T98	0	4	0	0
T99	0	4	0	0
T100	0	9	0	0
T101	0	8	0	0
T103	0	5	0	0
T104	0	3	0	0
T105	0	1	0	0
T106	503	0	0	0
T107	11016	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	16737	0	0
T1	19470	121	0	0
T2	23644	265	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	113	0	0
T12	0	65	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	150	0	0
T29	0	286	0	0
T30	0	88	0	0
T31	0	95	0	0
T32	0	126	0	0
T89	0	262	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	358	0	0
T1	19470	2	0	0
T2	23644	9	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	2	0	0
T12	0	1	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	3	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T89	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4857232	0	0
T1	19470	18597	0	0
T2	23644	20144	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6680	0	0
T6	1105	704	0	0
T7	13717	12568	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4858944	0	0
T1	19470	18602	0	0
T2	23644	20144	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6681	0	0
T6	1105	705	0	0
T7	13717	12570	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	520	0	0
T1	19470	2	0	0
T2	23644	10	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	2	0	0
T12	0	1	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	3	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	4	0	0
T34	0	2	0	0
T89	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	418	0	0
T1	19470	2	0	0
T2	23644	9	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	2	0	0
T12	0	1	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	3	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T89	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	358	0	0
T1	19470	2	0	0
T2	23644	9	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	2	0	0
T12	0	1	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	3	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T89	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	358	0	0
T1	19470	2	0	0
T2	23644	9	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	2	0	0
T12	0	1	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	3	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T89	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	16343	0	0
T1	19470	118	0	0
T2	23644	256	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	111	0	0
T12	0	64	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	145	0	0
T29	0	282	0	0
T30	0	84	0	0
T31	0	93	0	0
T32	0	122	0	0
T89	0	254	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	316	0	0
T1	19470	1	0	0
T2	23644	9	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	2	0	0
T12	0	1	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	1	0	0
T29	0	4	0	0
T31	0	2	0	0
T35	0	5	0	0
T117	0	6	0	0
T118	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T5,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T7
0	1	Covered	T5,T26,T43
1	0	Covered	T1,T5,T26

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T42,T12
0	1	Covered	T7,T42,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T42,T12
1	-	Covered	T7,T42,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T7
DetectSt	168	Covered	T1,T5,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T42,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T7
DebounceSt->IdleSt	163	Covered	T45,T240,T54
DetectSt->IdleSt	186	Covered	T1,T5,T26
DetectSt->StableSt	191	Covered	T7,T42,T12
IdleSt->DebounceSt	148	Covered	T1,T5,T7
StableSt->IdleSt	206	Covered	T7,T42,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T7
0	1	Covered	T1,T5,T7
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T240,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T7
DetectSt	-	-	-	-	1	-	-	Covered	T1,T5,T26
DetectSt	-	-	-	-	0	1	-	Covered	T7,T42,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T7
StableSt	-	-	-	-	-	-	1	Covered	T7,T42,T12
StableSt	-	-	-	-	-	-	0	Covered	T7,T42,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	3375	0	0
CntIncr_A	5852696	115750	0	0
CntNoWrap_A	5852696	5182314	0	0
DetectStDropOut_A	5852696	480	0	0
DetectedOut_A	5852696	87790	0	0
DetectedPulseOut_A	5852696	983	0	0
DisabledIdleSt_A	5852696	4691301	0	0
DisabledNoDetection_A	5852696	4693480	0	0
EnterDebounceSt_A	5852696	1708	0	0
EnterDetectSt_A	5852696	1669	0	0
EnterStableSt_A	5852696	983	0	0
PulseIsPulse_A	5852696	983	0	0
StayInStableSt	5852696	86663	0	0
gen_high_event_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	838	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3375	0	0
T1	19470	14	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	24	0	0
T6	1105	0	0	0
T7	13717	34	0	0
T12	0	64	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	24	0	0
T30	0	36	0	0
T42	0	42	0	0
T43	0	34	0	0
T44	0	48	0	0
T45	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	115750	0	0
T1	19470	389	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	779	0	0
T6	1105	0	0	0
T7	13717	833	0	0
T12	0	1696	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	497	0	0
T30	0	1530	0	0
T42	0	1281	0	0
T43	0	710	0	0
T44	0	1270	0	0
T45	0	690	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5182314	0	0
T1	19470	19013	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6752	0	0
T6	1105	704	0	0
T7	13717	13266	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	480	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T5	7177	8	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	3	0	0
T43	0	17	0	0
T44	0	24	0	0
T51	422	0	0	0
T61	405	0	0	0
T80	0	16	0	0
T91	0	13	0	0
T92	0	28	0	0
T95	0	12	0	0
T96	0	22	0	0
T242	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	87790	0	0
T7	13717	1602	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T10	627	0	0	0
T12	0	3771	0	0
T30	0	697	0	0
T32	0	1048	0	0
T42	0	979	0	0
T51	422	0	0	0
T55	557	0	0	0
T57	632	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T89	0	3591	0	0
T107	0	146	0	0
T117	0	1818	0	0
T118	0	2088	0	0
T241	0	4790	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	983	0	0
T7	13717	17	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T10	627	0	0	0
T12	0	32	0	0
T30	0	18	0	0
T32	0	12	0	0
T42	0	21	0	0
T51	422	0	0	0
T55	557	0	0	0
T57	632	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T89	0	19	0	0
T107	0	6	0	0
T117	0	26	0	0
T118	0	13	0	0
T241	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4691301	0	0
T1	19470	16049	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	3313	0	0
T6	1105	704	0	0
T7	13717	8438	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4693480	0	0
T1	19470	16055	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	3313	0	0
T6	1105	705	0	0
T7	13717	8438	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1708	0	0
T1	19470	7	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	12	0	0
T6	1105	0	0	0
T7	13717	17	0	0
T12	0	32	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	12	0	0
T30	0	18	0	0
T42	0	21	0	0
T43	0	17	0	0
T44	0	24	0	0
T45	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1669	0	0
T1	19470	7	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	12	0	0
T6	1105	0	0	0
T7	13717	17	0	0
T12	0	32	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	12	0	0
T30	0	18	0	0
T42	0	21	0	0
T43	0	17	0	0
T44	0	24	0	0
T89	0	19	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	983	0	0
T7	13717	17	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T10	627	0	0	0
T12	0	32	0	0
T30	0	18	0	0
T32	0	12	0	0
T42	0	21	0	0
T51	422	0	0	0
T55	557	0	0	0
T57	632	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T89	0	19	0	0
T107	0	6	0	0
T117	0	26	0	0
T118	0	13	0	0
T241	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	983	0	0
T7	13717	17	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T10	627	0	0	0
T12	0	32	0	0
T30	0	18	0	0
T32	0	12	0	0
T42	0	21	0	0
T51	422	0	0	0
T55	557	0	0	0
T57	632	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T89	0	19	0	0
T107	0	6	0	0
T117	0	26	0	0
T118	0	13	0	0
T241	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	86663	0	0
T7	13717	1582	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T10	627	0	0	0
T12	0	3730	0	0
T30	0	677	0	0
T32	0	1031	0	0
T42	0	958	0	0
T51	422	0	0	0
T55	557	0	0	0
T57	632	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T89	0	3569	0	0
T107	0	140	0	0
T117	0	1789	0	0
T118	0	2069	0	0
T241	0	4773	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	838	0	0
T7	13717	14	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T10	627	0	0	0
T12	0	23	0	0
T30	0	16	0	0
T32	0	7	0	0
T42	0	21	0	0
T51	422	0	0	0
T55	557	0	0	0
T57	632	0	0	0
T61	405	0	0	0
T62	445	0	0	0
T63	426	0	0	0
T89	0	15	0	0
T107	0	6	0	0
T117	0	23	0	0
T118	0	7	0	0
T241	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T7,T42

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T42
1	0	Covered	T1,T5,T2
1	1	Covered	T2,T7,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T12
0	1	Covered	T35,T227,T243
1	0	Covered	T54,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T12
0	1	Covered	T2,T7,T12
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T12
1	-	Covered	T2,T7,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T42
DetectSt	168	Covered	T2,T7,T12
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T7,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T12
DebounceSt->IdleSt	163	Covered	T7,T42,T31
DetectSt->IdleSt	186	Covered	T35,T227,T73
DetectSt->StableSt	191	Covered	T2,T7,T12
IdleSt->DebounceSt	148	Covered	T2,T7,T42
StableSt->IdleSt	206	Covered	T2,T7,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T42
0	1	Covered	T2,T7,T42
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T12
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T42,T31
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T42
DetectSt	-	-	-	-	1	-	-	Covered	T35,T227,T243
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T12
DetectSt	-	-	-	-	0	0	-	Covered	T2,T7,T12
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T12
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	896	0	0
CntIncr_A	5852696	50403	0	0
CntNoWrap_A	5852696	5184793	0	0
DetectStDropOut_A	5852696	64	0	0
DetectedOut_A	5852696	14382	0	0
DetectedPulseOut_A	5852696	346	0	0
DisabledIdleSt_A	5852696	4845946	0	0
DisabledNoDetection_A	5852696	4847689	0	0
EnterDebounceSt_A	5852696	482	0	0
EnterDetectSt_A	5852696	415	0	0
EnterStableSt_A	5852696	346	0	0
PulseIsPulse_A	5852696	346	0	0
StayInStableSt	5852696	13984	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	292	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	896	0	0
T2	23644	4	0	0
T3	1479	0	0	0
T6	1105	0	0	0
T7	13717	7	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T12	0	12	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	10	0	0
T30	0	4	0	0
T31	0	19	0	0
T32	0	8	0	0
T42	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T89	0	4	0	0
T241	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	50403	0	0
T2	23644	152	0	0
T3	1479	0	0	0
T6	1105	0	0	0
T7	13717	235	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T12	0	354	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	734	0	0
T30	0	138	0	0
T31	0	1262	0	0
T32	0	244	0	0
T42	0	23	0	0
T51	422	0	0	0
T61	405	0	0	0
T89	0	376	0	0
T241	0	908	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5184793	0	0
T1	19470	19027	0	0
T2	23644	23177	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13293	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	64	0	0
T35	16925	9	0	0
T46	648	0	0	0
T59	910	0	0	0
T66	497	0	0	0
T185	524	0	0	0
T186	445	0	0	0
T187	427	0	0	0
T188	402	0	0	0
T189	507	0	0	0
T190	420	0	0	0
T227	0	8	0	0
T243	0	1	0	0
T244	0	9	0	0
T245	0	9	0	0
T246	0	8	0	0
T247	0	7	0	0
T248	0	4	0	0
T249	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	14382	0	0
T2	23644	76	0	0
T3	1479	0	0	0
T6	1105	0	0	0
T7	13717	165	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T12	0	343	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	191	0	0
T30	0	120	0	0
T31	0	342	0	0
T32	0	181	0	0
T51	422	0	0	0
T61	405	0	0	0
T89	0	159	0	0
T117	0	38	0	0
T241	0	202	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	346	0	0
T2	23644	2	0	0
T3	1479	0	0	0
T6	1105	0	0	0
T7	13717	3	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T12	0	6	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	8	0	0
T32	0	4	0	0
T51	422	0	0	0
T61	405	0	0	0
T89	0	2	0	0
T117	0	1	0	0
T241	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4845946	0	0
T1	19470	19027	0	0
T2	23644	20144	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	11701	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4847689	0	0
T1	19470	19034	0	0
T2	23644	20144	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	11702	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	482	0	0
T2	23644	2	0	0
T3	1479	0	0	0
T6	1105	0	0	0
T7	13717	4	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T12	0	6	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	6	0	0
T30	0	2	0	0
T31	0	11	0	0
T32	0	4	0	0
T42	0	1	0	0
T51	422	0	0	0
T61	405	0	0	0
T89	0	2	0	0
T241	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	415	0	0
T2	23644	2	0	0
T3	1479	0	0	0
T6	1105	0	0	0
T7	13717	3	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T12	0	6	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	8	0	0
T32	0	4	0	0
T35	0	9	0	0
T51	422	0	0	0
T61	405	0	0	0
T89	0	2	0	0
T241	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	346	0	0
T2	23644	2	0	0
T3	1479	0	0	0
T6	1105	0	0	0
T7	13717	3	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T12	0	6	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	8	0	0
T32	0	4	0	0
T51	422	0	0	0
T61	405	0	0	0
T89	0	2	0	0
T117	0	1	0	0
T241	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	346	0	0
T2	23644	2	0	0
T3	1479	0	0	0
T6	1105	0	0	0
T7	13717	3	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T12	0	6	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	8	0	0
T32	0	4	0	0
T51	422	0	0	0
T61	405	0	0	0
T89	0	2	0	0
T117	0	1	0	0
T241	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	13984	0	0
T2	23644	74	0	0
T3	1479	0	0	0
T6	1105	0	0	0
T7	13717	161	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T12	0	337	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	187	0	0
T30	0	118	0	0
T31	0	334	0	0
T32	0	173	0	0
T51	422	0	0	0
T61	405	0	0	0
T89	0	155	0	0
T117	0	37	0	0
T241	0	194	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	292	0	0
T2	23644	2	0	0
T3	1479	0	0	0
T6	1105	0	0	0
T7	13717	2	0	0
T8	1527	0	0	0
T9	1304	0	0	0
T12	0	6	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	8	0	0
T51	422	0	0	0
T61	405	0	0	0
T77	0	3	0	0
T117	0	1	0	0
T118	0	4	0	0
T179	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T5,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T7
0	1	Covered	T1,T7,T43
1	0	Covered	T1,T7,T26

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T42,T12
0	1	Covered	T5,T42,T12
1	0	Covered	T26,T85,T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T26,T42
1	-	Covered	T5,T42,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T7
DetectSt	168	Covered	T1,T5,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T5,T26,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T7
DebounceSt->IdleSt	163	Covered	T45,T240,T54
DetectSt->IdleSt	186	Covered	T1,T7,T26
DetectSt->StableSt	191	Covered	T5,T26,T42
IdleSt->DebounceSt	148	Covered	T1,T5,T7
StableSt->IdleSt	206	Covered	T5,T26,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T7
0	1	Covered	T1,T5,T7
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T240,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T7
DetectSt	-	-	-	-	1	-	-	Covered	T1,T7,T26
DetectSt	-	-	-	-	0	1	-	Covered	T5,T26,T42
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T7
StableSt	-	-	-	-	-	-	1	Covered	T5,T26,T42
StableSt	-	-	-	-	-	-	0	Covered	T5,T42,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	3200	0	0
CntIncr_A	5852696	121201	0	0
CntNoWrap_A	5852696	5182489	0	0
DetectStDropOut_A	5852696	423	0	0
DetectedOut_A	5852696	78741	0	0
DetectedPulseOut_A	5852696	898	0	0
DisabledIdleSt_A	5852696	4693099	0	0
DisabledNoDetection_A	5852696	4695292	0	0
EnterDebounceSt_A	5852696	1622	0	0
EnterDetectSt_A	5852696	1579	0	0
EnterStableSt_A	5852696	898	0	0
PulseIsPulse_A	5852696	898	0	0
StayInStableSt	5852696	77712	0	0
gen_high_event_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	756	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3200	0	0
T1	19470	10	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	20	0	0
T6	1105	0	0	0
T7	13717	64	0	0
T12	0	26	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	18	0	0
T30	0	42	0	0
T42	0	44	0	0
T43	0	48	0	0
T44	0	26	0	0
T45	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	121201	0	0
T1	19470	277	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	650	0	0
T6	1105	0	0	0
T7	13717	2153	0	0
T12	0	728	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	374	0	0
T30	0	1638	0	0
T42	0	1144	0	0
T43	0	1009	0	0
T44	0	682	0	0
T45	0	749	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5182489	0	0
T1	19470	19017	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6756	0	0
T6	1105	704	0	0
T7	13717	13236	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	423	0	0
T1	19470	1	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	15	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T43	0	24	0	0
T44	0	13	0	0
T80	0	16	0	0
T89	0	8	0	0
T92	0	10	0	0
T158	0	10	0	0
T241	0	14	0	0
T250	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	78741	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T5	7177	1280	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	1090	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	3	0	0
T30	0	1135	0	0
T32	0	1235	0	0
T42	0	1304	0	0
T51	422	0	0	0
T61	405	0	0	0
T93	0	481	0	0
T117	0	452	0	0
T118	0	2342	0	0
T242	0	1342	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	898	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T5	7177	10	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	13	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	3	0	0
T30	0	21	0	0
T32	0	15	0	0
T42	0	22	0	0
T51	422	0	0	0
T61	405	0	0	0
T93	0	8	0	0
T117	0	9	0	0
T118	0	15	0	0
T242	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4693099	0	0
T1	19470	16049	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	2027	0	0
T6	1105	704	0	0
T7	13717	9739	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4695292	0	0
T1	19470	16055	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	2027	0	0
T6	1105	705	0	0
T7	13717	9742	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1622	0	0
T1	19470	5	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	10	0	0
T6	1105	0	0	0
T7	13717	32	0	0
T12	0	13	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	9	0	0
T30	0	21	0	0
T42	0	22	0	0
T43	0	24	0	0
T44	0	13	0	0
T45	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1579	0	0
T1	19470	5	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	10	0	0
T6	1105	0	0	0
T7	13717	32	0	0
T12	0	13	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	9	0	0
T30	0	21	0	0
T42	0	22	0	0
T43	0	24	0	0
T44	0	13	0	0
T89	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	898	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T5	7177	10	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	13	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	3	0	0
T30	0	21	0	0
T32	0	15	0	0
T42	0	22	0	0
T51	422	0	0	0
T61	405	0	0	0
T93	0	8	0	0
T117	0	9	0	0
T118	0	15	0	0
T242	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	898	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T5	7177	10	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	13	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	3	0	0
T30	0	21	0	0
T32	0	15	0	0
T42	0	22	0	0
T51	422	0	0	0
T61	405	0	0	0
T93	0	8	0	0
T117	0	9	0	0
T118	0	15	0	0
T242	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	77712	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T5	7177	1270	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	1075	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T30	0	1110	0	0
T32	0	1213	0	0
T42	0	1282	0	0
T51	422	0	0	0
T61	405	0	0	0
T93	0	473	0	0
T117	0	442	0	0
T118	0	2319	0	0
T242	0	1328	0	0
T251	0	2859	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	756	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T5	7177	10	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	11	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T30	0	17	0	0
T32	0	8	0	0
T42	0	22	0	0
T51	422	0	0	0
T61	405	0	0	0
T93	0	8	0	0
T117	0	8	0	0
T118	0	7	0	0
T242	0	14	0	0
T251	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T5,T2,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T5,T2,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T5,T2,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T26
1	0	Covered	T1,T5,T2
1	1	Covered	T5,T2,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T12
0	1	Covered	T78,T50,T252
1	0	Covered	T54,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T12
0	1	Covered	T5,T2,T12
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T2,T12
1	-	Covered	T5,T2,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T2,T12
DetectSt	168	Covered	T5,T2,T12
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T5,T2,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T2,T12
DebounceSt->IdleSt	163	Covered	T12,T33,T253
DetectSt->IdleSt	186	Covered	T78,T50,T252
DetectSt->StableSt	191	Covered	T5,T2,T12
IdleSt->DebounceSt	148	Covered	T5,T2,T12
StableSt->IdleSt	206	Covered	T5,T2,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T2,T12
0	1	Covered	T5,T2,T12
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T2,T12
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T2,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T2,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T33,T253
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T2,T12
DetectSt	-	-	-	-	1	-	-	Covered	T78,T50,T252
DetectSt	-	-	-	-	0	1	-	Covered	T5,T2,T12
DetectSt	-	-	-	-	0	0	-	Covered	T5,T2,T12
StableSt	-	-	-	-	-	-	1	Covered	T5,T2,T12
StableSt	-	-	-	-	-	-	0	Covered	T5,T2,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	753	0	0
CntIncr_A	5852696	41568	0	0
CntNoWrap_A	5852696	5184936	0	0
DetectStDropOut_A	5852696	46	0	0
DetectedOut_A	5852696	15454	0	0
DetectedPulseOut_A	5852696	311	0	0
DisabledIdleSt_A	5852696	4865325	0	0
DisabledNoDetection_A	5852696	4867107	0	0
EnterDebounceSt_A	5852696	392	0	0
EnterDetectSt_A	5852696	361	0	0
EnterStableSt_A	5852696	311	0	0
PulseIsPulse_A	5852696	311	0	0
StayInStableSt	5852696	15111	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	278	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	753	0	0
T2	23644	12	0	0
T3	1479	0	0	0
T5	7177	10	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	5	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	10	0	0
T30	0	8	0	0
T31	0	10	0	0
T32	0	6	0	0
T35	0	4	0	0
T51	422	0	0	0
T61	405	0	0	0
T118	0	8	0	0
T179	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	41568	0	0
T2	23644	504	0	0
T3	1479	0	0	0
T5	7177	200	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	145	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	830	0	0
T30	0	336	0	0
T31	0	815	0	0
T32	0	201	0	0
T35	0	160	0	0
T51	422	0	0	0
T61	405	0	0	0
T118	0	244	0	0
T179	0	168	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5184936	0	0
T1	19470	19027	0	0
T2	23644	23169	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6766	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	46	0	0
T47	737	0	0	0
T50	0	2	0	0
T78	13057	2	0	0
T91	6447	0	0	0
T104	0	7	0	0
T107	11016	0	0	0
T158	7909	0	0	0
T227	10235	0	0	0
T228	491	0	0	0
T229	862	0	0	0
T243	0	15	0	0
T245	0	3	0	0
T247	0	2	0	0
T252	0	4	0	0
T253	8336	0	0	0
T254	0	4	0	0
T255	0	3	0	0
T256	0	4	0	0
T257	421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	15454	0	0
T2	23644	183	0	0
T3	1479	0	0	0
T5	7177	405	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	107	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	121	0	0
T30	0	177	0	0
T31	0	63	0	0
T32	0	124	0	0
T35	0	142	0	0
T51	422	0	0	0
T61	405	0	0	0
T118	0	230	0	0
T179	0	147	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	311	0	0
T2	23644	6	0	0
T3	1479	0	0	0
T5	7177	5	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	2	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	5	0	0
T30	0	4	0	0
T31	0	5	0	0
T32	0	3	0	0
T35	0	2	0	0
T51	422	0	0	0
T61	405	0	0	0
T118	0	4	0	0
T179	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4865325	0	0
T1	19470	19027	0	0
T2	23644	20144	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	5496	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4867107	0	0
T1	19470	19034	0	0
T2	23644	20144	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	5497	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	392	0	0
T2	23644	6	0	0
T3	1479	0	0	0
T5	7177	5	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	3	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	5	0	0
T30	0	4	0	0
T31	0	5	0	0
T32	0	3	0	0
T35	0	2	0	0
T51	422	0	0	0
T61	405	0	0	0
T118	0	4	0	0
T179	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	361	0	0
T2	23644	6	0	0
T3	1479	0	0	0
T5	7177	5	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	2	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	5	0	0
T30	0	4	0	0
T31	0	5	0	0
T32	0	3	0	0
T35	0	2	0	0
T51	422	0	0	0
T61	405	0	0	0
T118	0	4	0	0
T179	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	311	0	0
T2	23644	6	0	0
T3	1479	0	0	0
T5	7177	5	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	2	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	5	0	0
T30	0	4	0	0
T31	0	5	0	0
T32	0	3	0	0
T35	0	2	0	0
T51	422	0	0	0
T61	405	0	0	0
T118	0	4	0	0
T179	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	311	0	0
T2	23644	6	0	0
T3	1479	0	0	0
T5	7177	5	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	2	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	5	0	0
T30	0	4	0	0
T31	0	5	0	0
T32	0	3	0	0
T35	0	2	0	0
T51	422	0	0	0
T61	405	0	0	0
T118	0	4	0	0
T179	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	15111	0	0
T2	23644	177	0	0
T3	1479	0	0	0
T5	7177	400	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	105	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	116	0	0
T30	0	171	0	0
T31	0	58	0	0
T32	0	121	0	0
T35	0	140	0	0
T51	422	0	0	0
T61	405	0	0	0
T118	0	225	0	0
T179	0	144	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	278	0	0
T2	23644	6	0	0
T3	1479	0	0	0
T5	7177	5	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	2	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	5	0	0
T30	0	2	0	0
T31	0	5	0	0
T32	0	3	0	0
T35	0	2	0	0
T51	422	0	0	0
T61	405	0	0	0
T118	0	3	0	0
T179	0	3	0	0