Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T5,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T7
0	1	Covered	T5,T7,T43
1	0	Covered	T5,T7,T107

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T26,T42
0	1	Covered	T1,T26,T42
1	0	Covered	T84,T54,T258

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T26,T42
1	-	Covered	T1,T26,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T7
DetectSt	168	Covered	T1,T5,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T26,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T7
DebounceSt->IdleSt	163	Covered	T45,T240,T54
DetectSt->IdleSt	186	Covered	T5,T7,T43
DetectSt->StableSt	191	Covered	T1,T26,T42
IdleSt->DebounceSt	148	Covered	T1,T5,T7
StableSt->IdleSt	206	Covered	T1,T26,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T7
0	1	Covered	T1,T5,T7
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T240,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T7
DetectSt	-	-	-	-	1	-	-	Covered	T5,T7,T43
DetectSt	-	-	-	-	0	1	-	Covered	T1,T26,T42
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T26,T42
StableSt	-	-	-	-	-	-	0	Covered	T1,T26,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	3043	0	0
CntIncr_A	5852696	104890	0	0
CntNoWrap_A	5852696	5182646	0	0
DetectStDropOut_A	5852696	399	0	0
DetectedOut_A	5852696	88638	0	0
DetectedPulseOut_A	5852696	968	0	0
DisabledIdleSt_A	5852696	4687333	0	0
DisabledNoDetection_A	5852696	4689514	0	0
EnterDebounceSt_A	5852696	1536	0	0
EnterDetectSt_A	5852696	1507	0	0
EnterStableSt_A	5852696	968	0	0
PulseIsPulse_A	5852696	968	0	0
StayInStableSt	5852696	87527	0	0
gen_high_event_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	811	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	3043	0	0
T1	19470	28	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	52	0	0
T6	1105	0	0	0
T7	13717	64	0	0
T12	0	16	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	50	0	0
T30	0	10	0	0
T42	0	18	0	0
T43	0	26	0	0
T44	0	58	0	0
T45	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	104890	0	0
T1	19470	644	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	1693	0	0
T6	1105	0	0	0
T7	13717	2153	0	0
T12	0	520	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	925	0	0
T30	0	405	0	0
T42	0	378	0	0
T43	0	539	0	0
T44	0	1547	0	0
T45	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5182646	0	0
T1	19470	18999	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6724	0	0
T6	1105	704	0	0
T7	13717	13236	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	399	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T5	7177	19	0	0
T6	1105	0	0	0
T7	13717	15	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T43	0	13	0	0
T44	0	29	0	0
T51	422	0	0	0
T61	405	0	0	0
T92	0	12	0	0
T94	0	15	0	0
T95	0	12	0	0
T96	0	13	0	0
T97	0	5	0	0
T107	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	88638	0	0
T1	19470	2070	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	785	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	1466	0	0
T30	0	61	0	0
T32	0	1434	0	0
T42	0	240	0	0
T80	0	1484	0	0
T89	0	1396	0	0
T117	0	997	0	0
T241	0	6732	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	968	0	0
T1	19470	14	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	8	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	25	0	0
T30	0	5	0	0
T32	0	10	0	0
T42	0	9	0	0
T80	0	6	0	0
T89	0	10	0	0
T117	0	17	0	0
T241	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4687333	0	0
T1	19470	14108	0	0
T2	23644	23181	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	3314	0	0
T6	1105	704	0	0
T7	13717	9739	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4689514	0	0
T1	19470	14108	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	3314	0	0
T6	1105	705	0	0
T7	13717	9742	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1536	0	0
T1	19470	14	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	26	0	0
T6	1105	0	0	0
T7	13717	32	0	0
T12	0	8	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	25	0	0
T30	0	5	0	0
T42	0	9	0	0
T43	0	13	0	0
T44	0	29	0	0
T45	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	1507	0	0
T1	19470	14	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	26	0	0
T6	1105	0	0	0
T7	13717	32	0	0
T12	0	8	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	25	0	0
T30	0	5	0	0
T42	0	9	0	0
T43	0	13	0	0
T44	0	29	0	0
T89	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	968	0	0
T1	19470	14	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	8	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	25	0	0
T30	0	5	0	0
T32	0	10	0	0
T42	0	9	0	0
T80	0	6	0	0
T89	0	10	0	0
T117	0	17	0	0
T241	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	968	0	0
T1	19470	14	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	8	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	25	0	0
T30	0	5	0	0
T32	0	10	0	0
T42	0	9	0	0
T80	0	6	0	0
T89	0	10	0	0
T117	0	17	0	0
T241	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	87527	0	0
T1	19470	2050	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	774	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	1438	0	0
T30	0	56	0	0
T32	0	1423	0	0
T42	0	231	0	0
T80	0	1478	0	0
T89	0	1384	0	0
T117	0	978	0	0
T241	0	6710	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	811	0	0
T1	19470	8	0	0
T2	23644	0	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	5	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	22	0	0
T30	0	5	0	0
T32	0	9	0	0
T42	0	9	0	0
T80	0	6	0	0
T89	0	8	0	0
T117	0	15	0	0
T241	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T2,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T26
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T2,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T26
0	1	Covered	T35,T78,T227
1	0	Covered	T54,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T26
0	1	Covered	T1,T2,T12
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T26
1	-	Covered	T1,T2,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T26
DetectSt	168	Covered	T1,T2,T26
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T2,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T26
DebounceSt->IdleSt	163	Covered	T2,T26,T29
DetectSt->IdleSt	186	Covered	T35,T78,T227
DetectSt->StableSt	191	Covered	T1,T2,T26
IdleSt->DebounceSt	148	Covered	T1,T2,T26
StableSt->IdleSt	206	Covered	T1,T2,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T26
0	1	Covered	T1,T2,T26
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T26
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T26,T29
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T26
DetectSt	-	-	-	-	1	-	-	Covered	T35,T78,T227
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T26
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T26
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5852696	934	0	0
CntIncr_A	5852696	50939	0	0
CntNoWrap_A	5852696	5184755	0	0
DetectStDropOut_A	5852696	81	0	0
DetectedOut_A	5852696	19076	0	0
DetectedPulseOut_A	5852696	362	0	0
DisabledIdleSt_A	5852696	4846147	0	0
DisabledNoDetection_A	5852696	4847900	0	0
EnterDebounceSt_A	5852696	488	0	0
EnterDetectSt_A	5852696	447	0	0
EnterStableSt_A	5852696	362	0	0
PulseIsPulse_A	5852696	362	0	0
StayInStableSt	5852696	18677	0	0
gen_high_level_sva.HighLevelEvent_A	5852696	5188108	0	0
gen_not_sticky_sva.StableStDropOut_A	5852696	323	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	934	0	0
T1	19470	10	0	0
T2	23644	5	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	6	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	7	0	0
T29	0	10	0	0
T31	0	4	0	0
T32	0	5	0	0
T35	0	11	0	0
T89	0	4	0	0
T241	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	50939	0	0
T1	19470	200	0	0
T2	23644	237	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	141	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	200	0	0
T29	0	618	0	0
T31	0	196	0	0
T32	0	101	0	0
T35	0	853	0	0
T89	0	378	0	0
T241	0	1065	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5184755	0	0
T1	19470	19017	0	0
T2	23644	23176	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	81	0	0
T35	16925	5	0	0
T46	648	0	0	0
T59	910	0	0	0
T66	497	0	0	0
T75	0	9	0	0
T78	0	5	0	0
T185	524	0	0	0
T186	445	0	0	0
T187	427	0	0	0
T188	402	0	0	0
T189	507	0	0	0
T190	420	0	0	0
T227	0	2	0	0
T252	0	11	0	0
T255	0	1	0	0
T259	0	1	0	0
T260	0	2	0	0
T261	0	6	0	0
T262	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	19076	0	0
T1	19470	372	0	0
T2	23644	10	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	208	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	127	0	0
T29	0	307	0	0
T31	0	155	0	0
T32	0	139	0	0
T80	0	479	0	0
T89	0	160	0	0
T241	0	332	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	362	0	0
T1	19470	5	0	0
T2	23644	2	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	3	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	3	0	0
T29	0	4	0	0
T31	0	2	0	0
T32	0	2	0	0
T80	0	4	0	0
T89	0	2	0	0
T241	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4846147	0	0
T1	19470	16963	0	0
T2	23644	20144	0	0
T3	1479	277	0	0
T4	413	12	0	0
T5	7177	6776	0	0
T6	1105	704	0	0
T7	13717	13300	0	0
T13	505	104	0	0
T14	493	92	0	0
T15	644	243	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	4847900	0	0
T1	19470	16964	0	0
T2	23644	20144	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	488	0	0
T1	19470	5	0	0
T2	23644	3	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	3	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	4	0	0
T29	0	6	0	0
T31	0	2	0	0
T32	0	3	0	0
T35	0	6	0	0
T89	0	2	0	0
T241	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	447	0	0
T1	19470	5	0	0
T2	23644	2	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	3	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	3	0	0
T29	0	4	0	0
T31	0	2	0	0
T32	0	2	0	0
T35	0	6	0	0
T89	0	2	0	0
T241	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	362	0	0
T1	19470	5	0	0
T2	23644	2	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	3	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	3	0	0
T29	0	4	0	0
T31	0	2	0	0
T32	0	2	0	0
T80	0	4	0	0
T89	0	2	0	0
T241	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	362	0	0
T1	19470	5	0	0
T2	23644	2	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	3	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	3	0	0
T29	0	4	0	0
T31	0	2	0	0
T32	0	2	0	0
T80	0	4	0	0
T89	0	2	0	0
T241	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	18677	0	0
T1	19470	367	0	0
T2	23644	8	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	205	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T26	0	121	0	0
T29	0	303	0	0
T31	0	153	0	0
T32	0	137	0	0
T80	0	475	0	0
T89	0	158	0	0
T241	0	327	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	5188108	0	0
T1	19470	19034	0	0
T2	23644	23191	0	0
T3	1479	279	0	0
T4	413	13	0	0
T5	7177	6777	0	0
T6	1105	705	0	0
T7	13717	13304	0	0
T13	505	105	0	0
T14	493	93	0	0
T15	644	244	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5852696	323	0	0
T1	19470	5	0	0
T2	23644	2	0	0
T3	1479	0	0	0
T4	413	0	0	0
T5	7177	0	0	0
T6	1105	0	0	0
T7	13717	0	0	0
T12	0	3	0	0
T13	505	0	0	0
T14	493	0	0	0
T15	644	0	0	0
T29	0	4	0	0
T31	0	2	0	0
T32	0	2	0	0
T80	0	3	0	0
T89	0	2	0	0
T117	0	2	0	0
T241	0	5	0	0