Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1190383868	11910	0	0
auto_block_debounce_ctl_rd_A	1190383868	2002	0	0
auto_block_out_ctl_rd_A	1190383868	2990	0	0
com_det_ctl_0_rd_A	1190383868	3199	0	0
com_det_ctl_1_rd_A	1190383868	3462	0	0
com_det_ctl_2_rd_A	1190383868	3487	0	0
com_det_ctl_3_rd_A	1190383868	3549	0	0
com_out_ctl_0_rd_A	1190383868	4231	0	0
com_out_ctl_1_rd_A	1190383868	4049	0	0
com_out_ctl_2_rd_A	1190383868	4183	0	0
com_out_ctl_3_rd_A	1190383868	4175	0	0
com_pre_det_ctl_0_rd_A	1190383868	1333	0	0
com_pre_det_ctl_1_rd_A	1190383868	1525	0	0
com_pre_det_ctl_2_rd_A	1190383868	1373	0	0
com_pre_det_ctl_3_rd_A	1190383868	1378	0	0
com_pre_sel_ctl_0_rd_A	1190383868	4283	0	0
com_pre_sel_ctl_1_rd_A	1190383868	4150	0	0
com_pre_sel_ctl_2_rd_A	1190383868	4337	0	0
com_pre_sel_ctl_3_rd_A	1190383868	4247	0	0
com_sel_ctl_0_rd_A	1190383868	4366	0	0
com_sel_ctl_1_rd_A	1190383868	4237	0	0
com_sel_ctl_2_rd_A	1190383868	4603	0	0
com_sel_ctl_3_rd_A	1190383868	4276	0	0
ec_rst_ctl_rd_A	1190383868	2334	0	0
intr_enable_rd_A	1190383868	1748	0	0
key_intr_ctl_rd_A	1190383868	3985	0	0
key_intr_debounce_ctl_rd_A	1190383868	1371	0	0
key_invert_ctl_rd_A	1190383868	6808	0	0
pin_allowed_ctl_rd_A	1190383868	6563	0	0
pin_out_ctl_rd_A	1190383868	5151	0	0
pin_out_value_rd_A	1190383868	4908	0	0
regwen_rd_A	1190383868	1469	0	0
ulp_ac_debounce_ctl_rd_A	1190383868	1628	0	0
ulp_ctl_rd_A	1190383868	1615	0	0
ulp_lid_debounce_ctl_rd_A	1190383868	1561	0	0
ulp_pwrb_debounce_ctl_rd_A	1190383868	1559	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	11910	0	0
T21	118624	0	0	0
T31	147182	0	0	0
T34	396028	22	0	0
T35	0	6	0	0
T39	0	13	0	0
T50	0	9	0	0
T64	35027	0	0	0
T70	65845	0	0	0
T73	0	13	0	0
T77	0	17	0	0
T89	178704	0	0	0
T133	0	15	0	0
T151	54306	0	0	0
T152	397751	0	0	0
T153	48806	0	0	0
T154	179257	0	0	0
T157	0	4	0	0
T199	0	23	0	0
T287	0	2	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	2002	0	0
T11	224487	0	0	0
T12	139743	0	0	0
T20	121637	0	0	0
T25	365592	15	0	0
T30	291028	0	0	0
T35	0	49	0	0
T42	340490	0	0	0
T44	658909	0	0	0
T47	0	9	0	0
T48	0	12	0	0
T50	0	34	0	0
T52	93571	0	0	0
T53	28705	0	0	0
T75	0	18	0	0
T274	99071	0	0	0
T288	0	12	0	0
T289	0	17	0	0
T290	0	4	0	0
T291	0	15	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	2990	0	0
T11	224487	0	0	0
T12	139743	0	0	0
T20	121637	0	0	0
T24	373295	9	0	0
T25	365592	16	0	0
T30	291028	0	0	0
T35	0	33	0	0
T42	340490	0	0	0
T44	658909	0	0	0
T47	0	11	0	0
T48	0	7	0	0
T50	0	26	0	0
T52	93571	0	0	0
T53	28705	0	0	0
T288	0	6	0	0
T289	0	19	0	0
T290	0	11	0	0
T291	0	16	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	3199	0	0
T1	788546	76	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	50	0	0
T35	0	46	0	0
T50	0	27	0	0
T80	0	35	0	0
T117	0	40	0	0
T118	0	83	0	0
T158	0	42	0	0
T227	0	81	0	0
T292	0	36	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	3462	0	0
T1	788546	76	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	29	0	0
T35	0	71	0	0
T50	0	21	0	0
T80	0	49	0	0
T117	0	49	0	0
T118	0	78	0	0
T158	0	44	0	0
T227	0	56	0	0
T292	0	37	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	3487	0	0
T1	788546	54	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	72	0	0
T35	0	91	0	0
T50	0	41	0	0
T80	0	38	0	0
T117	0	36	0	0
T118	0	82	0	0
T158	0	31	0	0
T227	0	63	0	0
T292	0	42	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	3549	0	0
T1	788546	64	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	23	0	0
T35	0	82	0	0
T50	0	33	0	0
T80	0	49	0	0
T117	0	51	0	0
T118	0	78	0	0
T158	0	45	0	0
T227	0	59	0	0
T292	0	30	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	4231	0	0
T1	788546	61	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	40	0	0
T35	0	74	0	0
T50	0	40	0	0
T80	0	46	0	0
T117	0	59	0	0
T118	0	85	0	0
T158	0	46	0	0
T227	0	66	0	0
T292	0	28	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	4049	0	0
T1	788546	40	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	66	0	0
T35	0	60	0	0
T50	0	35	0	0
T80	0	55	0	0
T117	0	25	0	0
T118	0	64	0	0
T158	0	53	0	0
T227	0	65	0	0
T292	0	23	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	4183	0	0
T1	788546	35	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	32	0	0
T35	0	68	0	0
T50	0	31	0	0
T80	0	45	0	0
T117	0	67	0	0
T118	0	110	0	0
T158	0	36	0	0
T227	0	64	0	0
T292	0	40	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	4175	0	0
T1	788546	60	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	42	0	0
T35	0	76	0	0
T50	0	47	0	0
T80	0	39	0	0
T117	0	55	0	0
T118	0	66	0	0
T158	0	52	0	0
T227	0	63	0	0
T292	0	36	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	1333	0	0
T35	829821	14	0	0
T46	84184	0	0	0
T50	0	11	0	0
T59	209201	0	0	0
T66	62133	0	0	0
T114	0	14	0	0
T128	0	13	0	0
T134	0	11	0	0
T148	0	21	0	0
T185	73429	0	0	0
T186	193816	0	0	0
T187	51303	0	0	0
T188	195028	0	0	0
T189	60920	0	0	0
T190	100967	0	0	0
T293	0	16	0	0
T294	0	40	0	0
T295	0	7	0	0
T296	0	4	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	1525	0	0
T35	829821	18	0	0
T46	84184	0	0	0
T50	0	11	0	0
T59	209201	0	0	0
T66	62133	0	0	0
T114	0	30	0	0
T128	0	5	0	0
T134	0	26	0	0
T185	73429	0	0	0
T186	193816	0	0	0
T187	51303	0	0	0
T188	195028	0	0	0
T189	60920	0	0	0
T190	100967	0	0	0
T293	0	11	0	0
T294	0	16	0	0
T295	0	11	0	0
T296	0	19	0	0
T297	0	6	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	1373	0	0
T35	829821	20	0	0
T46	84184	0	0	0
T50	0	18	0	0
T59	209201	0	0	0
T66	62133	0	0	0
T114	0	21	0	0
T128	0	19	0	0
T134	0	6	0	0
T185	73429	0	0	0
T186	193816	0	0	0
T187	51303	0	0	0
T188	195028	0	0	0
T189	60920	0	0	0
T190	100967	0	0	0
T293	0	5	0	0
T294	0	37	0	0
T295	0	18	0	0
T296	0	20	0	0
T297	0	11	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	1378	0	0
T35	829821	22	0	0
T46	84184	0	0	0
T50	0	26	0	0
T59	209201	0	0	0
T66	62133	0	0	0
T114	0	25	0	0
T128	0	7	0	0
T134	0	21	0	0
T185	73429	0	0	0
T186	193816	0	0	0
T187	51303	0	0	0
T188	195028	0	0	0
T189	60920	0	0	0
T190	100967	0	0	0
T293	0	10	0	0
T294	0	40	0	0
T295	0	1	0	0
T296	0	20	0	0
T297	0	8	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	4283	0	0
T1	788546	52	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	48	0	0
T35	0	96	0	0
T50	0	31	0	0
T80	0	40	0	0
T117	0	48	0	0
T118	0	90	0	0
T158	0	50	0	0
T227	0	49	0	0
T292	0	41	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	4150	0	0
T1	788546	69	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	28	0	0
T35	0	83	0	0
T50	0	39	0	0
T80	0	31	0	0
T117	0	38	0	0
T118	0	83	0	0
T158	0	56	0	0
T227	0	75	0	0
T292	0	33	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	4337	0	0
T1	788546	52	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	51	0	0
T35	0	78	0	0
T50	0	38	0	0
T80	0	47	0	0
T117	0	50	0	0
T118	0	82	0	0
T158	0	36	0	0
T227	0	103	0	0
T292	0	20	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	4247	0	0
T1	788546	68	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	39	0	0
T35	0	86	0	0
T50	0	39	0	0
T80	0	43	0	0
T117	0	32	0	0
T118	0	63	0	0
T158	0	43	0	0
T227	0	69	0	0
T292	0	30	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	4366	0	0
T1	788546	58	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	30	0	0
T35	0	80	0	0
T50	0	33	0	0
T80	0	50	0	0
T117	0	54	0	0
T118	0	58	0	0
T158	0	39	0	0
T227	0	77	0	0
T292	0	49	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	4237	0	0
T1	788546	52	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	40	0	0
T35	0	75	0	0
T50	0	46	0	0
T80	0	47	0	0
T117	0	43	0	0
T118	0	96	0	0
T158	0	29	0	0
T227	0	80	0	0
T292	0	40	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	4603	0	0
T1	788546	49	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	58	0	0
T35	0	73	0	0
T50	0	22	0	0
T80	0	56	0	0
T117	0	36	0	0
T118	0	69	0	0
T158	0	37	0	0
T227	0	61	0	0
T292	0	31	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	4276	0	0
T1	788546	49	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	59	0	0
T35	0	73	0	0
T50	0	21	0	0
T80	0	44	0	0
T117	0	52	0	0
T118	0	69	0	0
T158	0	54	0	0
T227	0	62	0	0
T292	0	30	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	2334	0	0
T1	788546	35	0	0
T2	112312	0	0	0
T3	335332	0	0	0
T4	33093	0	0	0
T5	538309	0	0	0
T6	14733	0	0	0
T7	342939	0	0	0
T13	60705	0	0	0
T14	237061	0	0	0
T15	322296	0	0	0
T31	0	43	0	0
T35	0	27	0	0
T45	0	1	0	0
T50	0	27	0	0
T80	0	3	0	0
T117	0	11	0	0
T118	0	40	0	0
T158	0	2	0	0
T298	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	1748	0	0
T35	829821	70	0	0
T46	84184	0	0	0
T50	0	26	0	0
T59	209201	0	0	0
T66	62133	0	0	0
T114	0	41	0	0
T128	0	6	0	0
T134	0	33	0	0
T185	73429	0	0	0
T186	193816	0	0	0
T187	51303	0	0	0
T188	195028	0	0	0
T189	60920	0	0	0
T190	100967	0	0	0
T293	0	22	0	0
T294	0	35	0	0
T295	0	15	0	0
T296	0	67	0	0
T297	0	33	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	3985	0	0
T35	829821	21	0	0
T46	84184	0	0	0
T50	0	28	0	0
T59	209201	0	0	0
T66	62133	0	0	0
T72	0	6	0	0
T75	0	5	0	0
T134	0	8	0	0
T135	0	2	0	0
T155	0	8	0	0
T184	0	7	0	0
T185	73429	0	0	0
T186	193816	0	0	0
T187	51303	0	0	0
T188	195028	0	0	0
T189	60920	0	0	0
T190	100967	0	0	0
T294	0	35	0	0
T299	0	5	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	1371	0	0
T35	829821	21	0	0
T46	84184	0	0	0
T50	0	20	0	0
T59	209201	0	0	0
T66	62133	0	0	0
T114	0	10	0	0
T128	0	11	0	0
T134	0	10	0	0
T185	73429	0	0	0
T186	193816	0	0	0
T187	51303	0	0	0
T188	195028	0	0	0
T189	60920	0	0	0
T190	100967	0	0	0
T293	0	10	0	0
T294	0	35	0	0
T295	0	1	0	0
T296	0	24	0	0
T297	0	9	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	6808	0	0
T7	342939	0	0	0
T8	276494	0	0	0
T9	229617	0	0	0
T14	237061	79	0	0
T15	322296	0	0	0
T20	0	62	0	0
T35	0	143	0	0
T50	0	77	0	0
T51	202728	0	0	0
T55	276161	0	0	0
T58	0	73	0	0
T61	50672	0	0	0
T62	106878	0	0	0
T63	51162	0	0	0
T64	0	77	0	0
T65	0	77	0	0
T67	0	59	0	0
T300	0	85	0	0
T301	0	34	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	6563	0	0
T11	224487	0	0	0
T12	139743	0	0	0
T20	121637	0	0	0
T22	30839	54	0	0
T24	373295	0	0	0
T25	365592	0	0	0
T35	0	10	0	0
T42	340490	0	0	0
T50	0	17	0	0
T52	93571	0	0	0
T53	28705	0	0	0
T56	268068	0	0	0
T106	0	54	0	0
T134	0	82	0	0
T189	0	62	0	0
T283	0	56	0	0
T289	0	69	0	0
T302	0	94	0	0
T303	0	85	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	5151	0	0
T11	224487	0	0	0
T12	139743	0	0	0
T20	121637	0	0	0
T22	30839	45	0	0
T24	373295	0	0	0
T25	365592	0	0	0
T35	0	6	0	0
T42	340490	0	0	0
T50	0	23	0	0
T52	93571	0	0	0
T53	28705	0	0	0
T56	268068	0	0	0
T106	0	58	0	0
T134	0	59	0	0
T189	0	76	0	0
T283	0	47	0	0
T289	0	42	0	0
T302	0	91	0	0
T303	0	57	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	4908	0	0
T11	224487	0	0	0
T12	139743	0	0	0
T20	121637	0	0	0
T22	30839	79	0	0
T24	373295	0	0	0
T25	365592	0	0	0
T35	0	11	0	0
T42	340490	0	0	0
T50	0	10	0	0
T52	93571	0	0	0
T53	28705	0	0	0
T56	268068	0	0	0
T106	0	70	0	0
T134	0	54	0	0
T189	0	59	0	0
T283	0	78	0	0
T289	0	71	0	0
T302	0	58	0	0
T303	0	88	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	1469	0	0
T35	829821	21	0	0
T46	84184	0	0	0
T50	0	19	0	0
T59	209201	0	0	0
T66	62133	0	0	0
T114	0	21	0	0
T128	0	12	0	0
T134	0	7	0	0
T185	73429	0	0	0
T186	193816	0	0	0
T187	51303	0	0	0
T188	195028	0	0	0
T189	60920	0	0	0
T190	100967	0	0	0
T293	0	12	0	0
T294	0	23	0	0
T295	0	4	0	0
T296	0	19	0	0
T297	0	2	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	1628	0	0
T8	276494	20	0	0
T9	229617	0	0	0
T10	21971	0	0	0
T22	30839	0	0	0
T26	147535	0	0	0
T43	589910	0	0	0
T50	0	13	0	0
T55	276161	0	0	0
T57	51961	0	0	0
T58	0	7	0	0
T62	106878	0	0	0
T63	51162	0	0	0
T74	0	4	0	0
T75	0	1	0	0
T119	0	9	0	0
T134	0	7	0	0
T304	0	4	0	0
T305	0	3	0	0
T306	0	2	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	1615	0	0
T8	276494	13	0	0
T9	229617	0	0	0
T10	21971	0	0	0
T22	30839	0	0	0
T26	147535	0	0	0
T35	0	8	0	0
T43	589910	0	0	0
T50	0	29	0	0
T55	276161	0	0	0
T57	51961	0	0	0
T58	0	3	0	0
T62	106878	0	0	0
T63	51162	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T304	0	1	0	0
T305	0	6	0	0
T306	0	4	0	0
T307	0	10	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	1561	0	0
T8	276494	2	0	0
T9	229617	0	0	0
T10	21971	0	0	0
T22	30839	0	0	0
T26	147535	0	0	0
T35	0	4	0	0
T43	589910	0	0	0
T50	0	25	0	0
T55	276161	0	0	0
T57	51961	0	0	0
T58	0	7	0	0
T62	106878	0	0	0
T63	51162	0	0	0
T74	0	4	0	0
T75	0	6	0	0
T134	0	21	0	0
T304	0	7	0	0
T306	0	1	0	0
T307	0	1	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190383868	1559	0	0
T8	276494	4	0	0
T9	229617	0	0	0
T10	21971	0	0	0
T22	30839	0	0	0
T26	147535	0	0	0
T35	0	16	0	0
T43	589910	0	0	0
T50	0	18	0	0
T55	276161	0	0	0
T57	51961	0	0	0
T58	0	2	0	0
T62	106878	0	0	0
T63	51162	0	0	0
T74	0	2	0	0
T75	0	2	0	0
T134	0	2	0	0
T304	0	6	0	0
T306	0	3	0	0
T307	0	9	0	0