Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl_keyintr
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_keyintr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_keyintr 100.00 100.00



Module Instance : tb.dut.u_sysrst_ctrl_keyintr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.84 93.82 93.54 91.67 92.50 97.70


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_keyfsm[0].u_sysrst_ctrl_detect_h2l 97.18 95.65 95.24 100.00 95.00 100.00
gen_keyfsm[0].u_sysrst_ctrl_detect_l2h 89.69 91.30 90.48 83.33 90.00 93.33
gen_keyfsm[1].u_sysrst_ctrl_detect_h2l 97.18 95.65 95.24 100.00 95.00 100.00
gen_keyfsm[1].u_sysrst_ctrl_detect_l2h 97.18 95.65 95.24 100.00 95.00 100.00
gen_keyfsm[2].u_sysrst_ctrl_detect_h2l 85.00 89.13 90.48 66.67 85.00 93.75
gen_keyfsm[2].u_sysrst_ctrl_detect_l2h 97.18 95.65 95.24 100.00 95.00 100.00
gen_keyfsm[3].u_sysrst_ctrl_detect_h2l 97.18 95.65 95.24 100.00 95.00 100.00
gen_keyfsm[3].u_sysrst_ctrl_detect_l2h 89.69 91.30 90.48 83.33 90.00 93.33
gen_keyfsm[4].u_sysrst_ctrl_detect_h2l 85.00 89.13 90.48 66.67 85.00 93.75
gen_keyfsm[4].u_sysrst_ctrl_detect_l2h 97.18 95.65 95.24 100.00 95.00 100.00
gen_keyfsm[5].u_sysrst_ctrl_detect_h2l 97.18 95.65 95.24 100.00 95.00 100.00
gen_keyfsm[5].u_sysrst_ctrl_detect_l2h 97.18 95.65 95.24 100.00 95.00 100.00
gen_keyfsm[6].u_sysrst_ctrl_detect_h2l 97.18 95.65 95.24 100.00 95.00 100.00
gen_keyfsm[6].u_sysrst_ctrl_detect_l2h 89.69 91.30 90.48 83.33 90.00 93.33


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl_keyintr
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_keyintr.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_keyintr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
30 1 1
39 1 1
48 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%