Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	85.00	89.13	90.48		66.67	85.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	85.00	89.13	90.48		66.67	85.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	89.69	91.30	90.48		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	89.69	91.30	90.48		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	89.69	91.30	90.48		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
85.00	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
85.00	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
89.69	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
89.69	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
89.69	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T2,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T35,T81
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
1	0	Covered	T82,T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T8
1	-	Covered	T1,T2,T8

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
85.00	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
85.00	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T18,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T18,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T18,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T18,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T2,T3
0	1	Covered	T3,T30,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T2,T3
0	1	Covered	T18,T2,T3
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T2,T3
1	-	Covered	T18,T2,T3

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T8,T9
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T9
1	0	Covered	T8,T9,T13
1	1	Covered	T14,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T8,T9
0	1	Covered	T14,T8,T13
1	0	Covered	T8,T13,T48

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T13
0	1	Covered	T8,T9,T13
1	0	Covered	T84,T85,T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T13
1	-	Covered	T8,T9,T13

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T29
1	0	Covered	T5,T6,T21
1	1	Covered	T7,T12,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T29
0	1	Covered	T77,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T29
0	1	Unreachable
1	0	Covered	T7,T12,T29

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
89.69	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
89.69	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
89.69	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T41,T89,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T3,T10,T12
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T11
1	-	Covered	T3,T10,T12

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T21
1	1	Covered	T5,T6,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T29
1	0	Covered	T5,T6,T21
1	1	Covered	T7,T12,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T29
0	1	Covered	T29,T75,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T29
0	1	Unreachable
1	0	Covered	T7,T12,T29

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T29
1	0	Covered	T5,T6,T21
1	1	Covered	T7,T12,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T29
0	1	Covered	T7,T62,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T29
0	1	Unreachable
1	0	Covered	T7,T12,T29

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T2,T3
DetectSt	168	Covered	T18,T2,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T18,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T2,T3
DebounceSt->IdleSt	163	Covered	T2,T12,T38
DetectSt->IdleSt	186	Covered	T3,T7,T30
DetectSt->StableSt	191	Covered	T18,T2,T3
IdleSt->DebounceSt	148	Covered	T18,T2,T3
StableSt->IdleSt	206	Covered	T18,T2,T3

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
85.00	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
85.00	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
89.69	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
89.69	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
89.69	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T2,T3
0	1	Covered	T18,T2,T3
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T12,T38
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T3,T7,T30
DetectSt	-	-	-	-	0	1	-	Covered	T18,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	1	Covered	T18,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T18,T2,T3
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T7,T8
0	1	Covered	T14,T7,T8
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T77,T93,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T14,T8,T13
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T9
DetectSt	-	-	-	-	0	0	-	Covered	T14,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	167330644	18597	0	0
CntIncr_A	167330644	1584178	0	0
CntNoWrap_A	167330644	150380353	0	0
DetectStDropOut_A	167330644	2154	0	0
DetectedOut_A	167330644	1338156	0	0
DetectedPulseOut_A	167330644	5821	0	0
DisabledIdleSt_A	167330644	141197265	0	0
DisabledNoDetection_A	167330644	141254519	0	0
EnterDebounceSt_A	167330644	9540	0	0
EnterDetectSt_A	167330644	9072	0	0
EnterStableSt_A	167330644	5820	0	0
PulseIsPulse_A	167330644	5820	0	0
StayInStableSt	167330644	1331436	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	57922146	52017	0	0
gen_high_event_sva.HighLevelEvent_A	32178970	28934745	0	0
gen_high_level_sva.HighLevelEvent_A	109408498	98378133	0	0
gen_low_level_sva.LowLevelEvent_A	57922146	52082541	0	0
gen_not_sticky_sva.StableStDropOut_A	148023262	4677	0	0
gen_sticky_sva.StableStDropOut_A	19307382	1214925	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167330644	18597	0	0
T1	101992	11	0	0
T2	223029	8	0	0
T3	8646	0	0	0
T7	312060	0	0	0
T8	19947	48	0	0
T9	42012	6	0	0
T10	0	16	0	0
T12	0	8	0	0
T13	0	52	0	0
T14	40816	8	0	0
T15	4016	0	0	0
T16	3392	0	0	0
T17	4056	0	0	0
T18	366336	2	0	0
T19	3654	0	0	0
T20	4428	0	0	0
T30	2199	6	0	0
T35	19093	12	0	0
T36	0	56	0	0
T39	0	3	0	0
T42	993	0	0	0
T47	0	28	0	0
T49	0	50	0	0
T50	2043	0	0	0
T52	0	4	0	0
T53	0	6	0	0
T55	1581	0	0	0
T58	1088	0	0	0
T68	1044	0	0	0
T69	1054	0	0	0
T78	0	2	0	0
T94	0	1	0	0
T95	0	19	0	0
T96	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167330644	1584178	0	0
T1	101992	339	0	0
T2	223029	467	0	0
T3	8646	0	0	0
T7	312060	0	0	0
T8	19947	1298	0	0
T9	42012	249	0	0
T10	0	875	0	0
T12	0	220	0	0
T13	0	1257	0	0
T14	40816	190	0	0
T15	4016	0	0	0
T16	3392	0	0	0
T17	4056	0	0	0
T18	366336	39992	0	0
T19	3654	0	0	0
T20	4428	0	0	0
T30	2199	202	0	0
T35	19093	840	0	0
T36	0	1128	0	0
T39	0	65	0	0
T42	993	0	0	0
T47	0	888	0	0
T49	0	1436	0	0
T50	2043	0	0	0
T52	0	170	0	0
T53	0	147	0	0
T55	1581	0	0	0
T58	1088	0	0	0
T68	1044	0	0	0
T69	1054	0	0	0
T78	0	75	0	0
T94	0	20	0	0
T95	0	773	0	0
T96	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167330644	150380353	0	0
T1	662948	651237	0	0
T4	14430	4004	0	0
T5	10634	208	0	0
T6	13052	2626	0	0
T14	132652	122148	0	0
T15	13052	2626	0	0
T21	12974	2548	0	0
T22	12740	2314	0	0
T23	13104	2678	0	0
T24	16900	6474	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167330644	2154	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T13	0	23	0	0
T14	5102	4	0	0
T30	733	1	0	0
T34	2232	0	0	0
T41	22832	0	0	0
T48	0	16	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T81	303848	1	0	0
T92	0	3	0	0
T97	0	10	0	0
T98	0	30	0	0
T99	0	7	0	0
T100	0	8	0	0
T101	0	5	0	0
T102	0	19	0	0
T103	0	3	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	5	0	0
T107	0	2	0	0
T108	0	5	0	0
T109	0	2	0	0
T110	0	18	0	0
T111	0	1	0	0
T112	415	0	0	0
T113	12850	0	0	0
T114	21469	0	0	0
T115	511	0	0	0
T116	12314	0	0	0
T117	504	0	0	0
T118	486	0	0	0
T119	413	0	0	0
T120	15590	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167330644	1338156	0	0
T1	25498	63	0	0
T2	49562	133	0	0
T3	1572	0	0	0
T7	44580	0	0	0
T8	13298	1932	0	0
T9	21006	117	0	0
T10	0	686	0	0
T12	0	27	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	81408	2	0	0
T19	812	0	0	0
T20	984	0	0	0
T30	733	10	0	0
T34	2232	0	0	0
T35	0	34	0	0
T36	0	1003	0	0
T37	0	51	0	0
T39	0	10	0	0
T47	0	1702	0	0
T49	0	2853	0	0
T50	1362	0	0	0
T52	0	16	0	0
T53	0	22	0	0
T54	0	1971	0	0
T55	1054	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T74	0	1883	0	0
T78	0	5	0	0
T95	0	274	0	0
T96	0	2	0	0
T112	415	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167330644	5821	0	0
T1	25498	5	0	0
T2	49562	3	0	0
T3	1572	0	0	0
T7	44580	0	0	0
T8	13298	24	0	0
T9	21006	3	0	0
T10	0	8	0	0
T12	0	4	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	81408	1	0	0
T19	812	0	0	0
T20	984	0	0	0
T30	733	2	0	0
T34	2232	0	0	0
T35	0	6	0	0
T36	0	28	0	0
T37	0	1	0	0
T39	0	1	0	0
T47	0	14	0	0
T49	0	25	0	0
T50	1362	0	0	0
T52	0	2	0	0
T53	0	3	0	0
T54	0	16	0	0
T55	1054	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T74	0	24	0	0
T78	0	1	0	0
T95	0	9	0	0
T96	0	1	0	0
T112	415	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167330644	141197265	0	0
T1	662948	631646	0	0
T4	14430	4004	0	0
T5	10634	208	0	0
T6	13052	2626	0	0
T14	132652	111484	0	0
T15	13052	2626	0	0
T21	12974	2548	0	0
T22	12740	2314	0	0
T23	13104	2678	0	0
T24	16900	6474	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167330644	141254519	0	0
T1	662948	631866	0	0
T4	14430	4030	0	0
T5	10634	234	0	0
T6	13052	2652	0	0
T14	132652	111506	0	0
T15	13052	2652	0	0
T21	12974	2574	0	0
T22	12740	2340	0	0
T23	13104	2704	0	0
T24	16900	6500	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167330644	9540	0	0
T1	101992	6	0	0
T2	223029	5	0	0
T3	8646	0	0	0
T7	312060	0	0	0
T8	19947	24	0	0
T9	42012	3	0	0
T10	0	8	0	0
T12	0	4	0	0
T13	0	26	0	0
T14	40816	4	0	0
T15	4016	0	0	0
T16	3392	0	0	0
T17	4056	0	0	0
T18	366336	1	0	0
T19	3654	0	0	0
T20	4428	0	0	0
T30	2199	3	0	0
T35	19093	6	0	0
T36	0	28	0	0
T39	0	2	0	0
T42	993	0	0	0
T47	0	14	0	0
T49	0	25	0	0
T50	2043	0	0	0
T52	0	2	0	0
T53	0	3	0	0
T55	1581	0	0	0
T58	1088	0	0	0
T68	1044	0	0	0
T69	1054	0	0	0
T78	0	1	0	0
T94	0	1	0	0
T95	0	10	0	0
T96	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167330644	9072	0	0
T1	101992	5	0	0
T2	223029	3	0	0
T3	8646	0	0	0
T7	312060	0	0	0
T8	19947	24	0	0
T9	42012	3	0	0
T10	0	8	0	0
T12	0	4	0	0
T13	0	26	0	0
T14	40816	4	0	0
T15	4016	0	0	0
T16	3392	0	0	0
T17	4056	0	0	0
T18	366336	1	0	0
T19	3654	0	0	0
T20	4428	0	0	0
T30	2199	3	0	0
T35	19093	6	0	0
T36	0	28	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	993	0	0	0
T47	0	14	0	0
T49	0	25	0	0
T50	2043	0	0	0
T52	0	2	0	0
T53	0	3	0	0
T55	1581	0	0	0
T58	1088	0	0	0
T68	1044	0	0	0
T69	1054	0	0	0
T78	0	1	0	0
T95	0	9	0	0
T96	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167330644	5820	0	0
T1	25498	5	0	0
T2	49562	3	0	0
T3	1572	0	0	0
T7	44580	0	0	0
T8	13298	24	0	0
T9	21006	3	0	0
T10	0	8	0	0
T12	0	4	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	81408	1	0	0
T19	812	0	0	0
T20	984	0	0	0
T30	733	2	0	0
T34	2232	0	0	0
T35	0	6	0	0
T36	0	28	0	0
T37	0	1	0	0
T39	0	1	0	0
T47	0	14	0	0
T49	0	25	0	0
T50	1362	0	0	0
T52	0	2	0	0
T53	0	3	0	0
T54	0	16	0	0
T55	1054	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T74	0	24	0	0
T78	0	1	0	0
T95	0	9	0	0
T96	0	1	0	0
T112	415	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167330644	5820	0	0
T1	25498	5	0	0
T2	49562	3	0	0
T3	1572	0	0	0
T7	44580	0	0	0
T8	13298	24	0	0
T9	21006	3	0	0
T10	0	8	0	0
T12	0	4	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	81408	1	0	0
T19	812	0	0	0
T20	984	0	0	0
T30	733	2	0	0
T34	2232	0	0	0
T35	0	6	0	0
T36	0	28	0	0
T37	0	1	0	0
T39	0	1	0	0
T47	0	14	0	0
T49	0	25	0	0
T50	1362	0	0	0
T52	0	2	0	0
T53	0	3	0	0
T54	0	16	0	0
T55	1054	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T74	0	24	0	0
T78	0	1	0	0
T95	0	9	0	0
T96	0	1	0	0
T112	415	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	167330644	1331436	0	0
T1	25498	58	0	0
T2	49562	130	0	0
T3	1572	0	0	0
T7	44580	0	0	0
T8	13298	1908	0	0
T9	21006	114	0	0
T10	0	678	0	0
T12	0	23	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	81408	1	0	0
T19	812	0	0	0
T20	984	0	0	0
T30	733	8	0	0
T34	2232	0	0	0
T35	0	28	0	0
T36	0	971	0	0
T37	0	50	0	0
T39	0	9	0	0
T47	0	1688	0	0
T49	0	2827	0	0
T50	1362	0	0	0
T52	0	14	0	0
T53	0	19	0	0
T54	0	1953	0	0
T55	1054	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T74	0	1855	0	0
T78	0	4	0	0
T95	0	265	0	0
T96	0	1	0	0
T112	415	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57922146	52017	0	0
T1	229482	80	0	0
T2	0	25	0	0
T3	0	4	0	0
T4	555	3	0	0
T5	2454	5	0	0
T6	4518	45	0	0
T14	45918	162	0	0
T15	4518	42	0	0
T16	3392	22	0	0
T17	1521	30	0	0
T19	0	1	0	0
T20	0	7	0	0
T21	4491	60	0	0
T22	4410	58	0	0
T23	4536	45	0	0
T24	5850	8	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32178970	28934745	0	0
T1	127490	125295	0	0
T4	2775	775	0	0
T5	2045	45	0	0
T6	2510	510	0	0
T14	25510	23510	0	0
T15	2510	510	0	0
T21	2495	495	0	0
T22	2450	450	0	0
T23	2520	520	0	0
T24	3250	1250	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109408498	98378133	0	0
T1	433466	426003	0	0
T4	9435	2635	0	0
T5	6953	153	0	0
T6	8534	1734	0	0
T14	86734	79934	0	0
T15	8534	1734	0	0
T21	8483	1683	0	0
T22	8330	1530	0	0
T23	8568	1768	0	0
T24	11050	4250	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57922146	52082541	0	0
T1	229482	225531	0	0
T4	4995	1395	0	0
T5	3681	81	0	0
T6	4518	918	0	0
T14	45918	42318	0	0
T15	4518	918	0	0
T21	4491	891	0	0
T22	4410	810	0	0
T23	4536	936	0	0
T24	5850	2250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148023262	4677	0	0
T1	25498	5	0	0
T2	49562	3	0	0
T3	1572	0	0	0
T7	44580	0	0	0
T8	13298	24	0	0
T9	21006	3	0	0
T10	0	8	0	0
T12	0	4	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	81408	1	0	0
T19	812	0	0	0
T20	984	0	0	0
T30	733	2	0	0
T34	2232	0	0	0
T35	0	6	0	0
T36	0	24	0	0
T37	0	1	0	0
T39	0	1	0	0
T47	0	14	0	0
T49	0	24	0	0
T50	1362	0	0	0
T52	0	2	0	0
T53	0	3	0	0
T54	0	14	0	0
T55	1054	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T74	0	20	0	0
T78	0	1	0	0
T95	0	9	0	0
T96	0	1	0	0
T112	415	0	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19307382	1214925	0	0
T7	133740	43630	0	0
T8	19947	0	0	0
T9	63018	0	0	0
T12	0	843	0	0
T29	0	221	0	0
T30	2199	0	0	0
T34	6696	0	0	0
T50	2043	0	0	0
T55	1581	0	0	0
T58	1632	0	0	0
T62	0	247	0	0
T68	1566	0	0	0
T69	1581	0	0	0
T75	0	360	0	0
T76	0	321	0	0
T77	0	1156	0	0
T78	0	886	0	0
T79	0	509	0	0
T80	0	384	0	0
T103	0	236	0	0
T121	0	193	0	0
T122	0	26	0	0
T123	0	97	0	0