Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T8,T9
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T9
1	0	Covered	T9,T13,T48
1	1	Covered	T14,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T8,T9
0	1	Covered	T14,T13,T48
1	0	Covered	T13,T48,T242

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T47
0	1	Covered	T8,T9,T47
1	0	Covered	T85,T86,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T47
1	-	Covered	T8,T9,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T8,T9
DetectSt	168	Covered	T14,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T9,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T8,T9
DebounceSt->IdleSt	163	Covered	T56,T57,T243
DetectSt->IdleSt	186	Covered	T14,T13,T48
DetectSt->StableSt	191	Covered	T8,T9,T47
IdleSt->DebounceSt	148	Covered	T14,T8,T9
StableSt->IdleSt	206	Covered	T8,T9,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T8,T9
0	1	Covered	T14,T8,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T14,T8,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T57,T243
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T14,T13,T48
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T47
DetectSt	-	-	-	-	0	0	-	Covered	T14,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T47
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T47
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	3216	0	0
CntIncr_A	6435794	118010	0	0
CntNoWrap_A	6435794	5781359	0	0
DetectStDropOut_A	6435794	435	0	0
DetectedOut_A	6435794	83141	0	0
DetectedPulseOut_A	6435794	832	0	0
DisabledIdleSt_A	6435794	5303045	0	0
DisabledNoDetection_A	6435794	5305188	0	0
EnterDebounceSt_A	6435794	1617	0	0
EnterDetectSt_A	6435794	1599	0	0
EnterStableSt_A	6435794	832	0	0
PulseIsPulse_A	6435794	832	0	0
StayInStableSt	6435794	82170	0	0
gen_high_event_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	689	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	3216	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	0	34	0	0
T9	0	6	0	0
T13	0	52	0	0
T14	5102	8	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T36	0	52	0	0
T47	0	24	0	0
T48	0	50	0	0
T49	0	44	0	0
T54	0	32	0	0
T74	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	118010	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	0	731	0	0
T9	0	249	0	0
T13	0	1257	0	0
T14	5102	190	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T36	0	988	0	0
T47	0	708	0	0
T48	0	7635	0	0
T49	0	1232	0	0
T54	0	960	0	0
T74	0	1464	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5781359	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4693	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	435	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T13	0	23	0	0
T14	5102	4	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T48	0	16	0	0
T85	0	4	0	0
T97	0	10	0	0
T98	0	30	0	0
T100	0	8	0	0
T101	0	5	0	0
T102	0	19	0	0
T244	0	22	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	83141	0	0
T8	6649	1590	0	0
T9	21006	117	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	924	0	0
T47	0	1584	0	0
T49	0	2677	0	0
T50	681	0	0	0
T54	0	1971	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T74	0	1883	0	0
T112	415	0	0	0
T245	0	2044	0	0
T246	0	1831	0	0
T247	0	484	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	832	0	0
T8	6649	17	0	0
T9	21006	3	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	26	0	0
T47	0	12	0	0
T49	0	22	0	0
T50	681	0	0	0
T54	0	16	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T74	0	24	0	0
T112	415	0	0	0
T245	0	9	0	0
T246	0	26	0	0
T247	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5303045	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	2014	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5305188	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	2014	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	1617	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	0	17	0	0
T9	0	3	0	0
T13	0	26	0	0
T14	5102	4	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T36	0	26	0	0
T47	0	12	0	0
T48	0	25	0	0
T49	0	22	0	0
T54	0	16	0	0
T74	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	1599	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	0	17	0	0
T9	0	3	0	0
T13	0	26	0	0
T14	5102	4	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T36	0	26	0	0
T47	0	12	0	0
T48	0	25	0	0
T49	0	22	0	0
T54	0	16	0	0
T74	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	832	0	0
T8	6649	17	0	0
T9	21006	3	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	26	0	0
T47	0	12	0	0
T49	0	22	0	0
T50	681	0	0	0
T54	0	16	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T74	0	24	0	0
T112	415	0	0	0
T245	0	9	0	0
T246	0	26	0	0
T247	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	832	0	0
T8	6649	17	0	0
T9	21006	3	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	26	0	0
T47	0	12	0	0
T49	0	22	0	0
T50	681	0	0	0
T54	0	16	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T74	0	24	0	0
T112	415	0	0	0
T245	0	9	0	0
T246	0	26	0	0
T247	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	82170	0	0
T8	6649	1573	0	0
T9	21006	114	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	894	0	0
T47	0	1572	0	0
T49	0	2654	0	0
T50	681	0	0	0
T54	0	1953	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T74	0	1855	0	0
T112	415	0	0	0
T245	0	2027	0	0
T246	0	1803	0	0
T247	0	467	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	689	0	0
T8	6649	17	0	0
T9	21006	3	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	22	0	0
T47	0	12	0	0
T49	0	21	0	0
T50	681	0	0	0
T54	0	14	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T74	0	20	0	0
T112	415	0	0	0
T245	0	1	0	0
T246	0	24	0	0
T247	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T2,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T81,T99,T103
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T8
1	-	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T8
DetectSt	168	Covered	T1,T2,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T8
DebounceSt->IdleSt	163	Covered	T1,T2,T94
DetectSt->IdleSt	186	Covered	T81,T99,T103
DetectSt->StableSt	191	Covered	T1,T2,T8
IdleSt->DebounceSt	148	Covered	T1,T2,T8
StableSt->IdleSt	206	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T2,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	1	-	-	Covered	T81,T99,T103
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	1052	0	0
CntIncr_A	6435794	52648	0	0
CntNoWrap_A	6435794	5783523	0	0
DetectStDropOut_A	6435794	63	0	0
DetectedOut_A	6435794	17996	0	0
DetectedPulseOut_A	6435794	423	0	0
DisabledIdleSt_A	6435794	5372405	0	0
DisabledNoDetection_A	6435794	5373990	0	0
EnterDebounceSt_A	6435794	563	0	0
EnterDetectSt_A	6435794	490	0	0
EnterStableSt_A	6435794	423	0	0
PulseIsPulse_A	6435794	423	0	0
StayInStableSt	6435794	17527	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	374	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	1052	0	0
T1	25498	11	0	0
T2	24781	5	0	0
T3	786	0	0	0
T8	0	14	0	0
T10	0	14	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	12	0	0
T36	0	4	0	0
T47	0	4	0	0
T49	0	6	0	0
T94	0	1	0	0
T95	0	19	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	52648	0	0
T1	25498	339	0	0
T2	24781	331	0	0
T3	786	0	0	0
T8	0	567	0	0
T10	0	826	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	840	0	0
T36	0	140	0	0
T47	0	180	0	0
T49	0	204	0	0
T94	0	20	0	0
T95	0	773	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5783523	0	0
T1	25498	25038	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	63	0	0
T41	22832	0	0	0
T81	303848	1	0	0
T92	0	3	0	0
T99	0	7	0	0
T103	0	3	0	0
T105	0	1	0	0
T106	0	5	0	0
T107	0	2	0	0
T108	0	5	0	0
T109	0	2	0	0
T110	0	18	0	0
T113	12850	0	0	0
T114	21469	0	0	0
T115	511	0	0	0
T116	12314	0	0	0
T117	504	0	0	0
T118	486	0	0	0
T119	413	0	0	0
T120	15590	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	17996	0	0
T1	25498	63	0	0
T2	24781	122	0	0
T3	786	0	0	0
T8	0	342	0	0
T10	0	684	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	34	0	0
T36	0	79	0	0
T37	0	51	0	0
T47	0	118	0	0
T49	0	176	0	0
T95	0	274	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	423	0	0
T1	25498	5	0	0
T2	24781	2	0	0
T3	786	0	0	0
T8	0	7	0	0
T10	0	7	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	6	0	0
T36	0	2	0	0
T37	0	1	0	0
T47	0	2	0	0
T49	0	3	0	0
T95	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5372405	0	0
T1	25498	20142	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5373990	0	0
T1	25498	20142	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	563	0	0
T1	25498	6	0	0
T2	24781	3	0	0
T3	786	0	0	0
T8	0	7	0	0
T10	0	7	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	6	0	0
T36	0	2	0	0
T47	0	2	0	0
T49	0	3	0	0
T94	0	1	0	0
T95	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	490	0	0
T1	25498	5	0	0
T2	24781	2	0	0
T3	786	0	0	0
T8	0	7	0	0
T10	0	7	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	6	0	0
T36	0	2	0	0
T37	0	1	0	0
T47	0	2	0	0
T49	0	3	0	0
T95	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	423	0	0
T1	25498	5	0	0
T2	24781	2	0	0
T3	786	0	0	0
T8	0	7	0	0
T10	0	7	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	6	0	0
T36	0	2	0	0
T37	0	1	0	0
T47	0	2	0	0
T49	0	3	0	0
T95	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	423	0	0
T1	25498	5	0	0
T2	24781	2	0	0
T3	786	0	0	0
T8	0	7	0	0
T10	0	7	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	6	0	0
T36	0	2	0	0
T37	0	1	0	0
T47	0	2	0	0
T49	0	3	0	0
T95	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	17527	0	0
T1	25498	58	0	0
T2	24781	120	0	0
T3	786	0	0	0
T8	0	335	0	0
T10	0	677	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	28	0	0
T36	0	77	0	0
T37	0	50	0	0
T47	0	116	0	0
T49	0	173	0	0
T95	0	265	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	374	0	0
T1	25498	5	0	0
T2	24781	2	0	0
T3	786	0	0	0
T8	0	7	0	0
T10	0	7	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	6	0	0
T36	0	2	0	0
T37	0	1	0	0
T47	0	2	0	0
T49	0	3	0	0
T95	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T8,T9
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T9
1	0	Covered	T8,T9,T13
1	1	Covered	T14,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T8,T9
0	1	Covered	T14,T8,T13
1	0	Covered	T8,T13,T47

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T48,T36
0	1	Covered	T9,T48,T36
1	0	Covered	T248,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T48,T36
1	-	Covered	T9,T48,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T8,T9
DetectSt	168	Covered	T14,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T48,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T8,T9
DebounceSt->IdleSt	163	Covered	T56,T57,T243
DetectSt->IdleSt	186	Covered	T14,T8,T13
DetectSt->StableSt	191	Covered	T9,T48,T36
IdleSt->DebounceSt	148	Covered	T14,T8,T9
StableSt->IdleSt	206	Covered	T9,T48,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T8,T9
0	1	Covered	T14,T8,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T14,T8,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T57,T243
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T14,T8,T13
DetectSt	-	-	-	-	0	1	-	Covered	T9,T48,T36
DetectSt	-	-	-	-	0	0	-	Covered	T14,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T9,T48,T36
StableSt	-	-	-	-	-	-	0	Covered	T9,T48,T36
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	3085	0	0
CntIncr_A	6435794	111779	0	0
CntNoWrap_A	6435794	5781490	0	0
DetectStDropOut_A	6435794	483	0	0
DetectedOut_A	6435794	74648	0	0
DetectedPulseOut_A	6435794	837	0	0
DisabledIdleSt_A	6435794	5310392	0	0
DisabledNoDetection_A	6435794	5312590	0	0
EnterDebounceSt_A	6435794	1556	0	0
EnterDetectSt_A	6435794	1529	0	0
EnterStableSt_A	6435794	837	0	0
PulseIsPulse_A	6435794	837	0	0
StayInStableSt	6435794	73728	0	0
gen_high_event_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	751	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	3085	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	0	18	0	0
T9	0	16	0	0
T13	0	18	0	0
T14	5102	22	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T36	0	46	0	0
T47	0	56	0	0
T48	0	34	0	0
T49	0	22	0	0
T54	0	26	0	0
T74	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	111779	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	0	454	0	0
T9	0	632	0	0
T13	0	429	0	0
T14	5102	526	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T36	0	1081	0	0
T47	0	1693	0	0
T48	0	5151	0	0
T49	0	781	0	0
T54	0	873	0	0
T74	0	450	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5781490	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4679	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	483	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	0	7	0	0
T13	0	7	0	0
T14	5102	11	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T47	0	16	0	0
T54	0	5	0	0
T97	0	27	0	0
T98	0	30	0	0
T100	0	21	0	0
T245	0	7	0	0
T246	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	74648	0	0
T9	21006	648	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	1575	0	0
T48	0	3940	0	0
T49	0	572	0	0
T58	544	0	0	0
T60	494	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T70	522	0	0	0
T74	0	518	0	0
T84	0	1049	0	0
T112	415	0	0	0
T116	0	732	0	0
T210	422	0	0	0
T242	0	386	0	0
T247	0	539	0	0
T249	0	883	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	837	0	0
T9	21006	8	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	23	0	0
T48	0	17	0	0
T49	0	11	0	0
T58	544	0	0	0
T60	494	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T70	522	0	0	0
T74	0	9	0	0
T84	0	14	0	0
T112	415	0	0	0
T116	0	9	0	0
T210	422	0	0	0
T242	0	11	0	0
T247	0	16	0	0
T249	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5310392	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	2015	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5312590	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	2015	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	1556	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	0	9	0	0
T9	0	8	0	0
T13	0	9	0	0
T14	5102	11	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T36	0	23	0	0
T47	0	28	0	0
T48	0	17	0	0
T49	0	11	0	0
T54	0	13	0	0
T74	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	1529	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	0	9	0	0
T9	0	8	0	0
T13	0	9	0	0
T14	5102	11	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T36	0	23	0	0
T47	0	28	0	0
T48	0	17	0	0
T49	0	11	0	0
T54	0	13	0	0
T74	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	837	0	0
T9	21006	8	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	23	0	0
T48	0	17	0	0
T49	0	11	0	0
T58	544	0	0	0
T60	494	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T70	522	0	0	0
T74	0	9	0	0
T84	0	14	0	0
T112	415	0	0	0
T116	0	9	0	0
T210	422	0	0	0
T242	0	11	0	0
T247	0	16	0	0
T249	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	837	0	0
T9	21006	8	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	23	0	0
T48	0	17	0	0
T49	0	11	0	0
T58	544	0	0	0
T60	494	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T70	522	0	0	0
T74	0	9	0	0
T84	0	14	0	0
T112	415	0	0	0
T116	0	9	0	0
T210	422	0	0	0
T242	0	11	0	0
T247	0	16	0	0
T249	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	73728	0	0
T9	21006	639	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	1549	0	0
T48	0	3923	0	0
T49	0	560	0	0
T58	544	0	0	0
T60	494	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T70	522	0	0	0
T74	0	508	0	0
T84	0	1033	0	0
T112	415	0	0	0
T116	0	723	0	0
T210	422	0	0	0
T242	0	375	0	0
T247	0	522	0	0
T249	0	867	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	751	0	0
T9	21006	7	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	20	0	0
T48	0	17	0	0
T49	0	10	0	0
T58	544	0	0	0
T60	494	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T70	522	0	0	0
T74	0	8	0	0
T84	0	12	0	0
T112	415	0	0	0
T116	0	9	0	0
T210	422	0	0	0
T242	0	11	0	0
T247	0	15	0	0
T249	0	14	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T2,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T9
0	1	Covered	T250,T103,T251
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T9
0	1	Covered	T1,T2,T9
1	0	Covered	T56,T252

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T9
1	-	Covered	T1,T2,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T9
DetectSt	168	Covered	T1,T2,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T9
DebounceSt->IdleSt	163	Covered	T10,T48,T35
DetectSt->IdleSt	186	Covered	T41,T250,T103
DetectSt->StableSt	191	Covered	T1,T2,T9
IdleSt->DebounceSt	148	Covered	T1,T2,T9
StableSt->IdleSt	206	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T9
0	1	Covered	T1,T2,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T48,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T9
DetectSt	-	-	-	-	1	-	-	Covered	T250,T103,T251
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T9
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	842	0	0
CntIncr_A	6435794	45919	0	0
CntNoWrap_A	6435794	5783733	0	0
DetectStDropOut_A	6435794	32	0	0
DetectedOut_A	6435794	15683	0	0
DetectedPulseOut_A	6435794	368	0	0
DisabledIdleSt_A	6435794	5397647	0	0
DisabledNoDetection_A	6435794	5399370	0	0
EnterDebounceSt_A	6435794	440	0	0
EnterDetectSt_A	6435794	404	0	0
EnterStableSt_A	6435794	367	0	0
PulseIsPulse_A	6435794	367	0	0
StayInStableSt	6435794	15290	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	338	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	842	0	0
T1	25498	8	0	0
T2	24781	8	0	0
T3	786	0	0	0
T9	0	2	0	0
T10	0	13	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	13	0	0
T36	0	8	0	0
T37	0	2	0	0
T48	0	3	0	0
T49	0	2	0	0
T95	0	19	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	45919	0	0
T1	25498	200	0	0
T2	24781	704	0	0
T3	786	0	0	0
T9	0	71	0	0
T10	0	1360	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	655	0	0
T36	0	220	0	0
T37	0	131	0	0
T48	0	607	0	0
T49	0	80	0	0
T95	0	971	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5783733	0	0
T1	25498	25041	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	32	0	0
T57	0	1	0	0
T101	14358	0	0	0
T103	0	1	0	0
T109	0	3	0	0
T122	17177	0	0	0
T123	48516	0	0	0
T174	0	3	0	0
T250	16496	4	0	0
T251	0	4	0	0
T253	0	2	0	0
T254	0	4	0	0
T255	0	9	0	0
T256	0	1	0	0
T257	402	0	0	0
T258	427	0	0	0
T259	545	0	0	0
T260	522	0	0	0
T261	494	0	0	0
T262	733	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	15683	0	0
T1	25498	103	0	0
T2	24781	28	0	0
T3	786	0	0	0
T9	0	71	0	0
T10	0	36	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	291	0	0
T36	0	215	0	0
T37	0	17	0	0
T48	0	58	0	0
T49	0	47	0	0
T95	0	76	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	368	0	0
T1	25498	4	0	0
T2	24781	4	0	0
T3	786	0	0	0
T9	0	1	0	0
T10	0	6	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	6	0	0
T36	0	4	0	0
T37	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T95	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5397647	0	0
T1	25498	20142	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5399370	0	0
T1	25498	20142	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	440	0	0
T1	25498	4	0	0
T2	24781	4	0	0
T3	786	0	0	0
T9	0	1	0	0
T10	0	7	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	7	0	0
T36	0	4	0	0
T37	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T95	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	404	0	0
T1	25498	4	0	0
T2	24781	4	0	0
T3	786	0	0	0
T9	0	1	0	0
T10	0	6	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	6	0	0
T36	0	4	0	0
T37	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T95	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	367	0	0
T1	25498	4	0	0
T2	24781	4	0	0
T3	786	0	0	0
T9	0	1	0	0
T10	0	6	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	6	0	0
T36	0	4	0	0
T37	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T95	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	367	0	0
T1	25498	4	0	0
T2	24781	4	0	0
T3	786	0	0	0
T9	0	1	0	0
T10	0	6	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	6	0	0
T36	0	4	0	0
T37	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T95	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	15290	0	0
T1	25498	99	0	0
T2	24781	24	0	0
T3	786	0	0	0
T9	0	70	0	0
T10	0	30	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	285	0	0
T36	0	211	0	0
T37	0	16	0	0
T48	0	57	0	0
T49	0	46	0	0
T95	0	67	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	338	0	0
T1	25498	4	0	0
T2	24781	4	0	0
T3	786	0	0	0
T9	0	1	0	0
T10	0	6	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	6	0	0
T36	0	4	0	0
T37	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T95	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T8,T9
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T9
1	0	Covered	T8,T9,T13
1	1	Covered	T14,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T8,T9
0	1	Covered	T14,T8,T13
1	0	Covered	T8,T13,T48

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T36,T49
0	1	Covered	T9,T36,T49
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T36,T49
1	-	Covered	T9,T36,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T8,T9
DetectSt	168	Covered	T14,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T36,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T8,T9
DebounceSt->IdleSt	163	Covered	T56,T57,T243
DetectSt->IdleSt	186	Covered	T14,T8,T13
DetectSt->StableSt	191	Covered	T9,T36,T49
IdleSt->DebounceSt	148	Covered	T14,T8,T9
StableSt->IdleSt	206	Covered	T9,T36,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T8,T9
0	1	Covered	T14,T8,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T14,T8,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T57,T243
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T14,T8,T13
DetectSt	-	-	-	-	0	1	-	Covered	T9,T36,T49
DetectSt	-	-	-	-	0	0	-	Covered	T14,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T9,T36,T49
StableSt	-	-	-	-	-	-	0	Covered	T9,T36,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	3114	0	0
CntIncr_A	6435794	115245	0	0
CntNoWrap_A	6435794	5781461	0	0
DetectStDropOut_A	6435794	458	0	0
DetectedOut_A	6435794	64200	0	0
DetectedPulseOut_A	6435794	771	0	0
DisabledIdleSt_A	6435794	5320761	0	0
DisabledNoDetection_A	6435794	5322951	0	0
EnterDebounceSt_A	6435794	1573	0	0
EnterDetectSt_A	6435794	1542	0	0
EnterStableSt_A	6435794	771	0	0
PulseIsPulse_A	6435794	771	0	0
StayInStableSt	6435794	63338	0	0
gen_high_event_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	679	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	3114	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	0	44	0	0
T9	0	26	0	0
T13	0	44	0	0
T14	5102	28	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T36	0	8	0	0
T47	0	28	0	0
T48	0	22	0	0
T49	0	32	0	0
T54	0	54	0	0
T74	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	115245	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	0	1131	0	0
T9	0	1222	0	0
T13	0	1059	0	0
T14	5102	665	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T36	0	132	0	0
T47	0	835	0	0
T48	0	3360	0	0
T49	0	1152	0	0
T54	0	1829	0	0
T74	0	1797	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5781461	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4673	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	458	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	0	14	0	0
T13	0	19	0	0
T14	5102	14	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T47	0	9	0	0
T48	0	5	0	0
T54	0	17	0	0
T84	0	1	0	0
T97	0	12	0	0
T98	0	28	0	0
T246	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	64200	0	0
T9	21006	1835	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	68	0	0
T49	0	1028	0	0
T58	544	0	0	0
T60	494	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T70	522	0	0	0
T101	0	308	0	0
T112	415	0	0	0
T116	0	2296	0	0
T210	422	0	0	0
T242	0	320	0	0
T247	0	1473	0	0
T263	0	2070	0	0
T264	0	2296	0	0
T265	0	1625	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	771	0	0
T9	21006	13	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	4	0	0
T49	0	16	0	0
T58	544	0	0	0
T60	494	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T70	522	0	0	0
T101	0	9	0	0
T112	415	0	0	0
T116	0	28	0	0
T210	422	0	0	0
T242	0	11	0	0
T247	0	27	0	0
T263	0	32	0	0
T264	0	26	0	0
T265	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5320761	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	2016	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5322951	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	2016	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	1573	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	0	22	0	0
T9	0	13	0	0
T13	0	22	0	0
T14	5102	14	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T36	0	4	0	0
T47	0	14	0	0
T48	0	11	0	0
T49	0	16	0	0
T54	0	27	0	0
T74	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	1542	0	0
T2	24781	0	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	0	22	0	0
T9	0	13	0	0
T13	0	22	0	0
T14	5102	14	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T36	0	4	0	0
T47	0	14	0	0
T48	0	11	0	0
T49	0	16	0	0
T54	0	27	0	0
T74	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	771	0	0
T9	21006	13	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	4	0	0
T49	0	16	0	0
T58	544	0	0	0
T60	494	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T70	522	0	0	0
T101	0	9	0	0
T112	415	0	0	0
T116	0	28	0	0
T210	422	0	0	0
T242	0	11	0	0
T247	0	27	0	0
T263	0	32	0	0
T264	0	26	0	0
T265	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	771	0	0
T9	21006	13	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	4	0	0
T49	0	16	0	0
T58	544	0	0	0
T60	494	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T70	522	0	0	0
T101	0	9	0	0
T112	415	0	0	0
T116	0	28	0	0
T210	422	0	0	0
T242	0	11	0	0
T247	0	27	0	0
T263	0	32	0	0
T264	0	26	0	0
T265	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	63338	0	0
T9	21006	1818	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	64	0	0
T49	0	1009	0	0
T58	544	0	0	0
T60	494	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T70	522	0	0	0
T101	0	298	0	0
T112	415	0	0	0
T116	0	2268	0	0
T210	422	0	0	0
T242	0	309	0	0
T247	0	1443	0	0
T263	0	2037	0	0
T264	0	2265	0	0
T265	0	1596	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	679	0	0
T9	21006	9	0	0
T10	37590	0	0	0
T34	2232	0	0	0
T36	0	4	0	0
T49	0	13	0	0
T58	544	0	0	0
T60	494	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T70	522	0	0	0
T101	0	8	0	0
T112	415	0	0	0
T116	0	28	0	0
T210	422	0	0	0
T242	0	11	0	0
T247	0	24	0	0
T263	0	31	0	0
T264	0	21	0	0
T265	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T2,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T9
0	1	Covered	T1,T35,T120
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T2,T9,T10
1	0	Covered	T82,T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T10
1	-	Covered	T2,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T9
DetectSt	168	Covered	T1,T2,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T9
DebounceSt->IdleSt	163	Covered	T10,T12,T35
DetectSt->IdleSt	186	Covered	T1,T35,T120
DetectSt->StableSt	191	Covered	T2,T9,T10
IdleSt->DebounceSt	148	Covered	T1,T2,T9
StableSt->IdleSt	206	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T9
0	1	Covered	T1,T2,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T12,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T9
DetectSt	-	-	-	-	1	-	-	Covered	T1,T35,T120
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T9
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	839	0	0
CntIncr_A	6435794	50147	0	0
CntNoWrap_A	6435794	5783736	0	0
DetectStDropOut_A	6435794	105	0	0
DetectedOut_A	6435794	11689	0	0
DetectedPulseOut_A	6435794	292	0	0
DisabledIdleSt_A	6435794	5401653	0	0
DisabledNoDetection_A	6435794	5403353	0	0
EnterDebounceSt_A	6435794	438	0	0
EnterDetectSt_A	6435794	402	0	0
EnterStableSt_A	6435794	292	0	0
PulseIsPulse_A	6435794	292	0	0
StayInStableSt	6435794	11379	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	271	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	839	0	0
T1	25498	6	0	0
T2	24781	12	0	0
T3	786	0	0	0
T9	0	6	0	0
T10	0	24	0	0
T12	0	3	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	23	0	0
T49	0	4	0	0
T95	0	10	0	0
T181	0	7	0	0
T266	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	50147	0	0
T1	25498	227	0	0
T2	24781	1014	0	0
T3	786	0	0	0
T9	0	231	0	0
T10	0	2191	0	0
T12	0	170	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	1678	0	0
T49	0	98	0	0
T95	0	325	0	0
T181	0	589	0	0
T266	0	708	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5783736	0	0
T1	25498	25043	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	105	0	0
T1	25498	3	0	0
T2	24781	0	0	0
T3	786	0	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	11	0	0
T89	0	4	0	0
T92	0	2	0	0
T103	0	1	0	0
T120	0	7	0	0
T123	0	8	0	0
T146	0	3	0	0
T193	0	2	0	0
T267	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	11689	0	0
T2	24781	87	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	194	0	0
T10	0	390	0	0
T12	0	13	0	0
T20	492	0	0	0
T30	733	0	0	0
T49	0	155	0	0
T50	681	0	0	0
T55	527	0	0	0
T68	522	0	0	0
T95	0	235	0	0
T143	0	105	0	0
T181	0	114	0	0
T242	0	57	0	0
T266	0	312	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	292	0	0
T2	24781	6	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	3	0	0
T10	0	11	0	0
T12	0	1	0	0
T20	492	0	0	0
T30	733	0	0	0
T49	0	2	0	0
T50	681	0	0	0
T55	527	0	0	0
T68	522	0	0	0
T95	0	5	0	0
T143	0	2	0	0
T181	0	3	0	0
T242	0	1	0	0
T266	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5401653	0	0
T1	25498	20142	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5403353	0	0
T1	25498	20142	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	438	0	0
T1	25498	3	0	0
T2	24781	6	0	0
T3	786	0	0	0
T9	0	3	0	0
T10	0	13	0	0
T12	0	2	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	12	0	0
T49	0	2	0	0
T95	0	5	0	0
T181	0	4	0	0
T266	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	402	0	0
T1	25498	3	0	0
T2	24781	6	0	0
T3	786	0	0	0
T9	0	3	0	0
T10	0	11	0	0
T12	0	1	0	0
T14	5102	0	0	0
T15	502	0	0	0
T16	424	0	0	0
T17	507	0	0	0
T18	40704	0	0	0
T19	406	0	0	0
T20	492	0	0	0
T35	0	11	0	0
T49	0	2	0	0
T95	0	5	0	0
T181	0	3	0	0
T266	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	292	0	0
T2	24781	6	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	3	0	0
T10	0	11	0	0
T12	0	1	0	0
T20	492	0	0	0
T30	733	0	0	0
T49	0	2	0	0
T50	681	0	0	0
T55	527	0	0	0
T68	522	0	0	0
T95	0	5	0	0
T143	0	2	0	0
T181	0	3	0	0
T242	0	1	0	0
T266	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	292	0	0
T2	24781	6	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	3	0	0
T10	0	11	0	0
T12	0	1	0	0
T20	492	0	0	0
T30	733	0	0	0
T49	0	2	0	0
T50	681	0	0	0
T55	527	0	0	0
T68	522	0	0	0
T95	0	5	0	0
T143	0	2	0	0
T181	0	3	0	0
T242	0	1	0	0
T266	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	11379	0	0
T2	24781	81	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	191	0	0
T10	0	379	0	0
T12	0	12	0	0
T20	492	0	0	0
T30	733	0	0	0
T49	0	153	0	0
T50	681	0	0	0
T55	527	0	0	0
T68	522	0	0	0
T95	0	230	0	0
T143	0	103	0	0
T181	0	111	0	0
T242	0	56	0	0
T266	0	308	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	271	0	0
T2	24781	6	0	0
T3	786	0	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	3	0	0
T10	0	11	0	0
T12	0	1	0	0
T20	492	0	0	0
T30	733	0	0	0
T49	0	2	0	0
T50	681	0	0	0
T55	527	0	0	0
T68	522	0	0	0
T95	0	5	0	0
T143	0	2	0	0
T181	0	3	0	0
T242	0	1	0	0
T266	0	4	0	0