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Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 100.00 100.00 95.24 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 100.00 100.00 95.24 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

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Module Instances:
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Line No.TotalCoveredPercent
TOTAL4343100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
79 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
MISSING_ELSE
205 1 1
206 1 1
209 1 1
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
TotalCoveredPercent
Conditions1919100.00
Logical1919100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT14,T8,T9
1CoveredT4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT14,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT14,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT14,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT14,T8,T9
10CoveredT8,T9,T13
11CoveredT14,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT14,T8,T9
01CoveredT14,T47,T54
10CoveredT8,T48,T47

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT9,T13,T36
01CoveredT9,T13,T36
10CoveredT84,T85,T268

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT9,T13,T36
1-CoveredT9,T13,T36

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T14,T8,T9
DetectSt 168 Covered T14,T8,T9
IdleSt 163 Covered T4,T5,T6
StableSt 191 Covered T9,T13,T36


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T14,T8,T9
DebounceSt->IdleSt 163 Covered T56,T57,T243
DetectSt->IdleSt 186 Covered T14,T8,T48
DetectSt->StableSt 191 Covered T9,T13,T36
IdleSt->DebounceSt 148 Covered T14,T8,T9
StableSt->IdleSt 206 Covered T9,T13,T36



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 92 3 3 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 12 11 91.67
IF 219 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTests
1 - Covered T14,T8,T9
0 1 Covered T14,T8,T9
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T14,T8,T9
0 Covered T4,T5,T6


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
IdleSt 1 - - - - - - Covered T14,T8,T9
IdleSt 0 - - - - - - Covered T14,T8,T9
DebounceSt - 1 - - - - - Covered T56,T57
DebounceSt - 0 1 1 - - - Covered T14,T8,T9
DebounceSt - 0 1 0 - - - Covered T56,T57,T243
DebounceSt - 0 0 - - - - Covered T14,T8,T9
DetectSt - - - - 1 - - Covered T14,T8,T48
DetectSt - - - - 0 1 - Covered T9,T13,T36
DetectSt - - - - 0 0 - Covered T14,T8,T9
StableSt - - - - - - 1 Covered T9,T13,T36
StableSt - - - - - - 0 Covered T9,T13,T36
default - - - - - - - Not Covered


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 6435794 3256 0 0
CntIncr_A 6435794 112748 0 0
CntNoWrap_A 6435794 5781319 0 0
DetectStDropOut_A 6435794 435 0 0
DetectedOut_A 6435794 82409 0 0
DetectedPulseOut_A 6435794 956 0 0
DisabledIdleSt_A 6435794 5304542 0 0
DisabledNoDetection_A 6435794 5306682 0 0
EnterDebounceSt_A 6435794 1640 0 0
EnterDetectSt_A 6435794 1617 0 0
EnterStableSt_A 6435794 956 0 0
PulseIsPulse_A 6435794 956 0 0
StayInStableSt 6435794 81312 0 0
gen_high_event_sva.HighLevelEvent_A 6435794 5786949 0 0
gen_high_level_sva.HighLevelEvent_A 6435794 5786949 0 0
gen_not_sticky_sva.StableStDropOut_A 6435794 785 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 3256 0 0
T2 24781 0 0 0
T3 786 0 0 0
T7 44580 0 0 0
T8 0 14 0 0
T9 0 44 0 0
T13 0 6 0 0
T14 5102 20 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T36 0 62 0 0
T47 0 10 0 0
T48 0 8 0 0
T49 0 42 0 0
T54 0 36 0 0
T74 0 60 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 112748 0 0
T2 24781 0 0 0
T3 786 0 0 0
T7 44580 0 0 0
T8 0 360 0 0
T9 0 1540 0 0
T13 0 132 0 0
T14 5102 473 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T36 0 1395 0 0
T47 0 299 0 0
T48 0 1222 0 0
T49 0 1386 0 0
T54 0 1213 0 0
T74 0 1740 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 5781319 0 0
T1 25498 25049 0 0
T4 555 154 0 0
T5 409 8 0 0
T6 502 101 0 0
T14 5102 4681 0 0
T15 502 101 0 0
T21 499 98 0 0
T22 490 89 0 0
T23 504 103 0 0
T24 650 249 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 435 0 0
T2 24781 0 0 0
T3 786 0 0 0
T7 44580 0 0 0
T14 5102 10 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T47 0 4 0 0
T54 0 7 0 0
T84 0 9 0 0
T97 0 28 0 0
T98 0 28 0 0
T244 0 9 0 0
T269 0 8 0 0
T270 0 1 0 0
T271 0 24 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 82409 0 0
T9 21006 3352 0 0
T10 37590 0 0 0
T13 0 285 0 0
T34 2232 0 0 0
T36 0 890 0 0
T49 0 1903 0 0
T58 544 0 0 0
T60 494 0 0 0
T68 522 0 0 0
T69 527 0 0 0
T70 522 0 0 0
T74 0 2209 0 0
T84 0 5 0 0
T112 415 0 0 0
T116 0 3522 0 0
T210 422 0 0 0
T242 0 1531 0 0
T247 0 409 0 0
T249 0 1158 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 956 0 0
T9 21006 22 0 0
T10 37590 0 0 0
T13 0 3 0 0
T34 2232 0 0 0
T36 0 31 0 0
T49 0 21 0 0
T58 544 0 0 0
T60 494 0 0 0
T68 522 0 0 0
T69 527 0 0 0
T70 522 0 0 0
T74 0 30 0 0
T84 0 5 0 0
T112 415 0 0 0
T116 0 27 0 0
T210 422 0 0 0
T242 0 26 0 0
T247 0 15 0 0
T249 0 28 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 5304542 0 0
T1 25498 25049 0 0
T4 555 154 0 0
T5 409 8 0 0
T6 502 101 0 0
T14 5102 2017 0 0
T15 502 101 0 0
T21 499 98 0 0
T22 490 89 0 0
T23 504 103 0 0
T24 650 249 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 5306682 0 0
T1 25498 25059 0 0
T4 555 155 0 0
T5 409 9 0 0
T6 502 102 0 0
T14 5102 2017 0 0
T15 502 102 0 0
T21 499 99 0 0
T22 490 90 0 0
T23 504 104 0 0
T24 650 250 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 1640 0 0
T2 24781 0 0 0
T3 786 0 0 0
T7 44580 0 0 0
T8 0 7 0 0
T9 0 22 0 0
T13 0 3 0 0
T14 5102 10 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T36 0 31 0 0
T47 0 5 0 0
T48 0 4 0 0
T49 0 21 0 0
T54 0 18 0 0
T74 0 30 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 1617 0 0
T2 24781 0 0 0
T3 786 0 0 0
T7 44580 0 0 0
T8 0 7 0 0
T9 0 22 0 0
T13 0 3 0 0
T14 5102 10 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T36 0 31 0 0
T47 0 5 0 0
T48 0 4 0 0
T49 0 21 0 0
T54 0 18 0 0
T74 0 30 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 956 0 0
T9 21006 22 0 0
T10 37590 0 0 0
T13 0 3 0 0
T34 2232 0 0 0
T36 0 31 0 0
T49 0 21 0 0
T58 544 0 0 0
T60 494 0 0 0
T68 522 0 0 0
T69 527 0 0 0
T70 522 0 0 0
T74 0 30 0 0
T84 0 5 0 0
T112 415 0 0 0
T116 0 27 0 0
T210 422 0 0 0
T242 0 26 0 0
T247 0 15 0 0
T249 0 28 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 956 0 0
T9 21006 22 0 0
T10 37590 0 0 0
T13 0 3 0 0
T34 2232 0 0 0
T36 0 31 0 0
T49 0 21 0 0
T58 544 0 0 0
T60 494 0 0 0
T68 522 0 0 0
T69 527 0 0 0
T70 522 0 0 0
T74 0 30 0 0
T84 0 5 0 0
T112 415 0 0 0
T116 0 27 0 0
T210 422 0 0 0
T242 0 26 0 0
T247 0 15 0 0
T249 0 28 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 81312 0 0
T9 21006 3325 0 0
T10 37590 0 0 0
T13 0 281 0 0
T34 2232 0 0 0
T36 0 855 0 0
T49 0 1881 0 0
T58 544 0 0 0
T60 494 0 0 0
T68 522 0 0 0
T69 527 0 0 0
T70 522 0 0 0
T74 0 2174 0 0
T100 0 2146 0 0
T112 415 0 0 0
T116 0 3495 0 0
T210 422 0 0 0
T242 0 1505 0 0
T247 0 392 0 0
T249 0 1129 0 0

gen_high_event_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 5786949 0 0
T1 25498 25059 0 0
T4 555 155 0 0
T5 409 9 0 0
T6 502 102 0 0
T14 5102 4702 0 0
T15 502 102 0 0
T21 499 99 0 0
T22 490 90 0 0
T23 504 104 0 0
T24 650 250 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 5786949 0 0
T1 25498 25059 0 0
T4 555 155 0 0
T5 409 9 0 0
T6 502 102 0 0
T14 5102 4702 0 0
T15 502 102 0 0
T21 499 99 0 0
T22 490 90 0 0
T23 504 104 0 0
T24 650 250 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 785 0 0
T9 21006 17 0 0
T10 37590 0 0 0
T13 0 2 0 0
T34 2232 0 0 0
T36 0 27 0 0
T49 0 20 0 0
T58 544 0 0 0
T60 494 0 0 0
T68 522 0 0 0
T69 527 0 0 0
T70 522 0 0 0
T74 0 25 0 0
T100 0 6 0 0
T112 415 0 0 0
T116 0 27 0 0
T210 422 0 0 0
T242 0 26 0 0
T247 0 13 0 0
T249 0 27 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions212095.24
Logical212095.24
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T14,T2
1CoveredT4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T14,T2
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT4,T5,T6 VC_COV_UNR
1CoveredT1,T2,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T8
10CoveredT1,T14,T2
11CoveredT1,T2,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T9
01CoveredT10,T143,T114
10CoveredT56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T9
01CoveredT1,T2,T9
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT1,T2,T9
1-CoveredT1,T2,T9

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T1,T2,T9
DetectSt 168 Covered T1,T2,T9
IdleSt 163 Covered T4,T5,T6
StableSt 191 Covered T1,T2,T9


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T1,T2,T9
DebounceSt->IdleSt 163 Covered T37,T266,T249
DetectSt->IdleSt 186 Covered T10,T143,T114
DetectSt->StableSt 191 Covered T1,T2,T9
IdleSt->DebounceSt 148 Covered T1,T2,T9
StableSt->IdleSt 206 Covered T1,T2,T9



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 21 21 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 11 11 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T9
0 1 Covered T1,T2,T9
0 0 Excluded T4,T5,T6 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T9
0 Covered T4,T5,T6


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T1,T2,T9
IdleSt 0 - - - - - - Covered T4,T5,T6
DebounceSt - 1 - - - - - Covered T56,T57
DebounceSt - 0 1 1 - - - Covered T1,T2,T9
DebounceSt - 0 1 0 - - - Covered T37,T266,T249
DebounceSt - 0 0 - - - - Covered T1,T2,T9
DetectSt - - - - 1 - - Covered T10,T143,T114
DetectSt - - - - 0 1 - Covered T1,T2,T9
DetectSt - - - - 0 0 - Covered T1,T2,T9
StableSt - - - - - - 1 Covered T1,T2,T9
StableSt - - - - - - 0 Covered T1,T2,T9
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 6435794 1006 0 0
CntIncr_A 6435794 54294 0 0
CntNoWrap_A 6435794 5783569 0 0
DetectStDropOut_A 6435794 90 0 0
DetectedOut_A 6435794 18117 0 0
DetectedPulseOut_A 6435794 386 0 0
DisabledIdleSt_A 6435794 5374632 0 0
DisabledNoDetection_A 6435794 5376266 0 0
EnterDebounceSt_A 6435794 527 0 0
EnterDetectSt_A 6435794 480 0 0
EnterStableSt_A 6435794 386 0 0
PulseIsPulse_A 6435794 386 0 0
StayInStableSt 6435794 17688 0 0
gen_high_level_sva.HighLevelEvent_A 6435794 5786949 0 0
gen_not_sticky_sva.StableStDropOut_A 6435794 341 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 1006 0 0
T1 25498 12 0 0
T2 24781 4 0 0
T3 786 0 0 0
T9 0 10 0 0
T10 0 4 0 0
T12 0 2 0 0
T13 0 2 0 0
T14 5102 0 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T35 0 8 0 0
T36 0 6 0 0
T49 0 10 0 0
T95 0 6 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 54294 0 0
T1 25498 378 0 0
T2 24781 198 0 0
T3 786 0 0 0
T9 0 445 0 0
T10 0 430 0 0
T12 0 100 0 0
T13 0 48 0 0
T14 5102 0 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T35 0 536 0 0
T36 0 162 0 0
T49 0 240 0 0
T95 0 234 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 5783569 0 0
T1 25498 25037 0 0
T4 555 154 0 0
T5 409 8 0 0
T6 502 101 0 0
T14 5102 4701 0 0
T15 502 101 0 0
T21 499 98 0 0
T22 490 89 0 0
T23 504 103 0 0
T24 650 249 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 90 0 0
T10 37590 2 0 0
T11 638 0 0 0
T12 13125 0 0 0
T59 789 0 0 0
T60 494 0 0 0
T70 522 0 0 0
T71 523 0 0 0
T89 0 8 0 0
T92 0 6 0 0
T114 0 5 0 0
T123 0 4 0 0
T143 0 10 0 0
T147 0 1 0 0
T164 423 0 0 0
T210 422 0 0 0
T211 424 0 0 0
T251 0 13 0 0
T272 0 1 0 0
T273 0 1 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 18117 0 0
T1 25498 77 0 0
T2 24781 169 0 0
T3 786 0 0 0
T9 0 262 0 0
T12 0 6 0 0
T13 0 78 0 0
T14 5102 0 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T35 0 46 0 0
T36 0 162 0 0
T49 0 395 0 0
T95 0 103 0 0
T181 0 315 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 386 0 0
T1 25498 6 0 0
T2 24781 2 0 0
T3 786 0 0 0
T9 0 5 0 0
T12 0 1 0 0
T13 0 1 0 0
T14 5102 0 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T35 0 4 0 0
T36 0 3 0 0
T49 0 5 0 0
T95 0 3 0 0
T181 0 4 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 5374632 0 0
T1 25498 20142 0 0
T4 555 154 0 0
T5 409 8 0 0
T6 502 101 0 0
T14 5102 4701 0 0
T15 502 101 0 0
T21 499 98 0 0
T22 490 89 0 0
T23 504 103 0 0
T24 650 249 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 5376266 0 0
T1 25498 20142 0 0
T4 555 155 0 0
T5 409 9 0 0
T6 502 102 0 0
T14 5102 4702 0 0
T15 502 102 0 0
T21 499 99 0 0
T22 490 90 0 0
T23 504 104 0 0
T24 650 250 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 527 0 0
T1 25498 6 0 0
T2 24781 2 0 0
T3 786 0 0 0
T9 0 5 0 0
T10 0 2 0 0
T12 0 1 0 0
T13 0 1 0 0
T14 5102 0 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T35 0 4 0 0
T36 0 3 0 0
T49 0 5 0 0
T95 0 3 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 480 0 0
T1 25498 6 0 0
T2 24781 2 0 0
T3 786 0 0 0
T9 0 5 0 0
T10 0 2 0 0
T12 0 1 0 0
T13 0 1 0 0
T14 5102 0 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T35 0 4 0 0
T36 0 3 0 0
T49 0 5 0 0
T95 0 3 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 386 0 0
T1 25498 6 0 0
T2 24781 2 0 0
T3 786 0 0 0
T9 0 5 0 0
T12 0 1 0 0
T13 0 1 0 0
T14 5102 0 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T35 0 4 0 0
T36 0 3 0 0
T49 0 5 0 0
T95 0 3 0 0
T181 0 4 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 386 0 0
T1 25498 6 0 0
T2 24781 2 0 0
T3 786 0 0 0
T9 0 5 0 0
T12 0 1 0 0
T13 0 1 0 0
T14 5102 0 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T35 0 4 0 0
T36 0 3 0 0
T49 0 5 0 0
T95 0 3 0 0
T181 0 4 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 17688 0 0
T1 25498 71 0 0
T2 24781 167 0 0
T3 786 0 0 0
T9 0 255 0 0
T12 0 5 0 0
T13 0 77 0 0
T14 5102 0 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T35 0 42 0 0
T36 0 159 0 0
T49 0 390 0 0
T95 0 100 0 0
T181 0 311 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 5786949 0 0
T1 25498 25059 0 0
T4 555 155 0 0
T5 409 9 0 0
T6 502 102 0 0
T14 5102 4702 0 0
T15 502 102 0 0
T21 499 99 0 0
T22 490 90 0 0
T23 504 104 0 0
T24 650 250 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6435794 341 0 0
T1 25498 6 0 0
T2 24781 2 0 0
T3 786 0 0 0
T9 0 3 0 0
T12 0 1 0 0
T13 0 1 0 0
T14 5102 0 0 0
T15 502 0 0 0
T16 424 0 0 0
T17 507 0 0 0
T18 40704 0 0 0
T19 406 0 0 0
T20 492 0 0 0
T35 0 4 0 0
T36 0 3 0 0
T49 0 5 0 0
T95 0 3 0 0
T181 0 4 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%