Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T21,T28,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T21,T28,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T28,T23,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T28,T23
1	0	Covered	T1,T5,T15
1	1	Covered	T21,T28,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T23,T33
0	1	Covered	T28,T86,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T23,T33
0	1	Covered	T28,T23,T33
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T23,T33
1	-	Covered	T28,T23,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T28,T23
DetectSt	168	Covered	T28,T23,T33
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T28,T23,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T23,T33
DebounceSt->IdleSt	163	Covered	T21,T43,T73
DetectSt->IdleSt	186	Covered	T28,T86,T87
DetectSt->StableSt	191	Covered	T28,T23,T33
IdleSt->DebounceSt	148	Covered	T21,T28,T23
StableSt->IdleSt	206	Covered	T28,T23,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T28,T23
0	1	Covered	T21,T28,T23
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T23,T33
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T28,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T21
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T23,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T73,T94,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T28,T23
DetectSt	-	-	-	-	1	-	-	Covered	T28,T86,T87
DetectSt	-	-	-	-	0	1	-	Covered	T28,T23,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T23,T33
StableSt	-	-	-	-	-	-	0	Covered	T28,T23,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	321	0	0
CntIncr_A	6449837	163062	0	0
CntNoWrap_A	6449837	5829340	0	0
DetectStDropOut_A	6449837	3	0	0
DetectedOut_A	6449837	989	0	0
DetectedPulseOut_A	6449837	145	0	0
DisabledIdleSt_A	6449837	5658898	0	0
DisabledNoDetection_A	6449837	5661127	0	0
EnterDebounceSt_A	6449837	176	0	0
EnterDetectSt_A	6449837	148	0	0
EnterStableSt_A	6449837	145	0	0
PulseIsPulse_A	6449837	145	0	0
StayInStableSt	6449837	844	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6449837	6521	0	0
gen_low_level_sva.LowLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	144	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	321	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	1	0	0
T23	0	2	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	6	0	0
T33	0	2	0	0
T38	0	4	0	0
T41	0	4	0	0
T42	0	2	0	0
T43	0	4	0	0
T44	0	4	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T73	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	163062	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	20	0	0
T23	0	81	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	229	0	0
T33	0	83	0	0
T38	0	24	0	0
T41	0	85	0	0
T42	0	54	0	0
T43	0	8469	0	0
T44	0	65	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T73	0	65	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5829340	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	3	0	0
T9	547	0	0	0
T10	21225	0	0	0
T26	506	0	0	0
T27	504	0	0	0
T28	769	1	0	0
T47	429	0	0	0
T48	421	0	0	0
T55	423	0	0	0
T56	820	0	0	0
T57	409	0	0	0
T86	0	1	0	0
T87	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	989	0	0
T9	547	0	0	0
T10	21225	0	0	0
T23	0	2	0	0
T26	506	0	0	0
T27	504	0	0	0
T28	769	13	0	0
T33	0	4	0	0
T38	0	14	0	0
T41	0	10	0	0
T42	0	11	0	0
T43	0	20	0	0
T44	0	9	0	0
T47	429	0	0	0
T48	421	0	0	0
T55	423	0	0	0
T56	820	0	0	0
T57	409	0	0	0
T90	0	18	0	0
T91	0	16	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	145	0	0
T9	547	0	0	0
T10	21225	0	0	0
T23	0	1	0	0
T26	506	0	0	0
T27	504	0	0	0
T28	769	2	0	0
T33	0	1	0	0
T38	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T47	429	0	0	0
T48	421	0	0	0
T55	423	0	0	0
T56	820	0	0	0
T57	409	0	0	0
T90	0	2	0	0
T91	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5658898	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5661127	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	176	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	1	0	0
T23	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	3	0	0
T33	0	1	0	0
T38	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	148	0	0
T9	547	0	0	0
T10	21225	0	0	0
T23	0	1	0	0
T26	506	0	0	0
T27	504	0	0	0
T28	769	3	0	0
T33	0	1	0	0
T38	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T47	429	0	0	0
T48	421	0	0	0
T55	423	0	0	0
T56	820	0	0	0
T57	409	0	0	0
T90	0	2	0	0
T91	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	145	0	0
T9	547	0	0	0
T10	21225	0	0	0
T23	0	1	0	0
T26	506	0	0	0
T27	504	0	0	0
T28	769	2	0	0
T33	0	1	0	0
T38	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T47	429	0	0	0
T48	421	0	0	0
T55	423	0	0	0
T56	820	0	0	0
T57	409	0	0	0
T90	0	2	0	0
T91	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	145	0	0
T9	547	0	0	0
T10	21225	0	0	0
T23	0	1	0	0
T26	506	0	0	0
T27	504	0	0	0
T28	769	2	0	0
T33	0	1	0	0
T38	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T47	429	0	0	0
T48	421	0	0	0
T55	423	0	0	0
T56	820	0	0	0
T57	409	0	0	0
T90	0	2	0	0
T91	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	844	0	0
T9	547	0	0	0
T10	21225	0	0	0
T23	0	1	0	0
T26	506	0	0	0
T27	504	0	0	0
T28	769	11	0	0
T33	0	3	0	0
T38	0	12	0	0
T41	0	8	0	0
T42	0	10	0	0
T43	0	18	0	0
T44	0	7	0	0
T47	429	0	0	0
T48	421	0	0	0
T55	423	0	0	0
T56	820	0	0	0
T57	409	0	0	0
T90	0	16	0	0
T91	0	14	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	6521	0	0
T1	36814	23	0	0
T2	1117	1	0	0
T3	33204	29	0	0
T5	6265	27	0	0
T6	16495	30	0	0
T7	0	12	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	29	0	0
T16	502	5	0	0
T17	9843	26	0	0
T21	0	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	144	0	0
T9	547	0	0	0
T10	21225	0	0	0
T23	0	1	0	0
T26	506	0	0	0
T27	504	0	0	0
T28	769	2	0	0
T33	0	1	0	0
T38	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T47	429	0	0	0
T48	421	0	0	0
T55	423	0	0	0
T56	820	0	0	0
T57	409	0	0	0
T90	0	2	0	0
T91	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T21,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T1,T5,T15
1	1	Covered	T21,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T40
0	1	Covered	T22,T71,T72
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T40
0	1	Unreachable
1	0	Covered	T22,T23,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T22,T23
DetectSt	168	Covered	T22,T23,T40
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T22,T23,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T23,T40
DebounceSt->IdleSt	163	Covered	T21,T30,T40
DetectSt->IdleSt	186	Covered	T22,T71,T72
DetectSt->StableSt	191	Covered	T22,T23,T40
IdleSt->DebounceSt	148	Covered	T21,T22,T23
StableSt->IdleSt	206	Covered	T22,T23,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T22,T23
0	1	Covered	T21,T22,T23
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T40
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T23,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T30,T40,T61
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T22,T71,T72
DetectSt	-	-	-	-	0	1	-	Covered	T22,T23,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T23,T40
StableSt	-	-	-	-	-	-	0	Covered	T22,T23,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	159	0	0
CntIncr_A	6449837	16105	0	0
CntNoWrap_A	6449837	5829502	0	0
DetectStDropOut_A	6449837	12	0	0
DetectedOut_A	6449837	97193	0	0
DetectedPulseOut_A	6449837	45	0	0
DisabledIdleSt_A	6449837	5651839	0	0
DisabledNoDetection_A	6449837	5654120	0	0
EnterDebounceSt_A	6449837	104	0	0
EnterDetectSt_A	6449837	57	0	0
EnterStableSt_A	6449837	45	0	0
PulseIsPulse_A	6449837	45	0	0
StayInStableSt	6449837	97148	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6449837	6521	0	0
gen_low_level_sva.LowLevelEvent_A	6449837	5831944	0	0
gen_sticky_sva.StableStDropOut_A	6449837	7461	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	159	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	1	0	0
T22	0	10	0	0
T23	0	2	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T30	0	2	0	0
T40	0	3	0	0
T43	0	2	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T50	0	4	0	0
T60	0	2	0	0
T61	0	3	0	0
T62	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	16105	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	19	0	0
T22	0	60	0	0
T23	0	69	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T30	0	50	0	0
T40	0	91	0	0
T43	0	95	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T50	0	188	0	0
T60	0	75	0	0
T61	0	32	0	0
T62	0	150	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5829502	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	12	0	0
T22	6357	4	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T98	406	0	0	0
T99	411	0	0	0
T101	0	2	0	0
T102	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	97193	0	0
T22	6357	1	0	0
T23	15192	71	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	16	0	0
T43	0	453	0	0
T50	0	125	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	106	0	0
T61	0	49	0	0
T62	0	390	0	0
T68	0	248	0	0
T95	0	83	0	0
T98	406	0	0	0
T99	411	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	45	0	0
T22	6357	1	0	0
T23	15192	1	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T50	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T68	0	1	0	0
T95	0	2	0	0
T98	406	0	0	0
T99	411	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5651839	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5654120	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	104	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	2	0	0
T22	0	5	0	0
T23	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T30	0	2	0	0
T40	0	2	0	0
T43	0	1	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T50	0	2	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	57	0	0
T22	6357	5	0	0
T23	15192	1	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T50	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T68	0	1	0	0
T95	0	2	0	0
T98	406	0	0	0
T99	411	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	45	0	0
T22	6357	1	0	0
T23	15192	1	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T50	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T68	0	1	0	0
T95	0	2	0	0
T98	406	0	0	0
T99	411	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	45	0	0
T22	6357	1	0	0
T23	15192	1	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T50	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T68	0	1	0	0
T95	0	2	0	0
T98	406	0	0	0
T99	411	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	97148	0	0
T23	15192	70	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	15	0	0
T43	0	452	0	0
T50	0	123	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	105	0	0
T61	0	48	0	0
T62	0	388	0	0
T68	0	247	0	0
T95	0	81	0	0
T96	0	1042	0	0
T98	406	0	0	0
T99	411	0	0	0
T103	433	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	6521	0	0
T1	36814	23	0	0
T2	1117	1	0	0
T3	33204	29	0	0
T5	6265	27	0	0
T6	16495	30	0	0
T7	0	12	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	29	0	0
T16	502	5	0	0
T17	9843	26	0	0
T21	0	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	7461	0	0
T22	6357	169	0	0
T23	15192	40	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	91	0	0
T43	0	210	0	0
T50	0	446	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	207	0	0
T61	0	307	0	0
T62	0	357	0	0
T68	0	67	0	0
T95	0	529	0	0
T98	406	0	0	0
T99	411	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T16,T2,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T16,T2,T21
1	1	Covered	T16,T2,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T21,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T40,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T16,T2,T24
1	1	Covered	T21,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T40,T43
0	1	Covered	T22,T40,T43
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T40,T43
0	1	Unreachable
1	0	Covered	T22,T40,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T22,T23
DetectSt	168	Covered	T22,T40,T43
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T22,T40,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T40,T43
DebounceSt->IdleSt	163	Covered	T21,T23,T30
DetectSt->IdleSt	186	Covered	T22,T40,T43
DetectSt->StableSt	191	Covered	T22,T40,T43
IdleSt->DebounceSt	148	Covered	T21,T22,T23
StableSt->IdleSt	206	Covered	T22,T40,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T22,T23
0	1	Covered	T21,T22,T23
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T40,T43
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T16,T2,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T40,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T30,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T22,T40,T43
DetectSt	-	-	-	-	0	1	-	Covered	T22,T40,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T40,T43
StableSt	-	-	-	-	-	-	0	Covered	T22,T40,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	167	0	0
CntIncr_A	6449837	47906	0	0
CntNoWrap_A	6449837	5829494	0	0
DetectStDropOut_A	6449837	13	0	0
DetectedOut_A	6449837	7000	0	0
DetectedPulseOut_A	6449837	40	0	0
DisabledIdleSt_A	6449837	5651839	0	0
DisabledNoDetection_A	6449837	5654120	0	0
EnterDebounceSt_A	6449837	116	0	0
EnterDetectSt_A	6449837	53	0	0
EnterStableSt_A	6449837	40	0	0
PulseIsPulse_A	6449837	40	0	0
StayInStableSt	6449837	6960	0	0
gen_high_level_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_sticky_sva.StableStDropOut_A	6449837	109448	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	167	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	1	0	0
T22	0	6	0	0
T23	0	2	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T30	0	2	0	0
T40	0	4	0	0
T43	0	6	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T50	0	3	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	47906	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	19	0	0
T22	0	87	0	0
T23	0	110	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T30	0	116	0	0
T40	0	154	0	0
T43	0	228	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T50	0	246	0	0
T60	0	48	0	0
T61	0	67	0	0
T62	0	140	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5829494	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	13	0	0
T22	6357	2	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	1	0	0
T43	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T98	406	0	0	0
T99	411	0	0	0
T104	0	1	0	0
T105	0	4	0	0
T106	0	1	0	0
T107	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	7000	0	0
T22	6357	62	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	33	0	0
T43	0	155	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	105	0	0
T61	0	290	0	0
T62	0	565	0	0
T68	0	122	0	0
T95	0	342	0	0
T96	0	319	0	0
T97	0	82	0	0
T98	406	0	0	0
T99	411	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	40	0	0
T22	6357	1	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T68	0	1	0	0
T95	0	1	0	0
T96	0	2	0	0
T97	0	1	0	0
T98	406	0	0	0
T99	411	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5651839	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5654120	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	116	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	2	0	0
T22	0	3	0	0
T23	0	2	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T30	0	2	0	0
T40	0	2	0	0
T43	0	3	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T50	0	3	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	53	0	0
T22	6357	3	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	2	0	0
T43	0	3	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T68	0	1	0	0
T95	0	1	0	0
T96	0	2	0	0
T97	0	1	0	0
T98	406	0	0	0
T99	411	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	40	0	0
T22	6357	1	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T68	0	1	0	0
T95	0	1	0	0
T96	0	2	0	0
T97	0	1	0	0
T98	406	0	0	0
T99	411	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	40	0	0
T22	6357	1	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T68	0	1	0	0
T95	0	1	0	0
T96	0	2	0	0
T97	0	1	0	0
T98	406	0	0	0
T99	411	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	6960	0	0
T22	6357	61	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	32	0	0
T43	0	154	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	104	0	0
T61	0	289	0	0
T62	0	563	0	0
T68	0	121	0	0
T95	0	341	0	0
T96	0	317	0	0
T97	0	81	0	0
T98	406	0	0	0
T99	411	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	109448	0	0
T22	6357	461	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	30	0	0
T43	0	247	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	232	0	0
T61	0	104	0	0
T62	0	204	0	0
T68	0	250	0	0
T95	0	105	0	0
T96	0	1012	0	0
T97	0	32	0	0
T98	406	0	0	0
T99	411	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T21,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T1,T5,T15
1	1	Covered	T21,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T30
0	1	Covered	T68,T69,T70
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T30
0	1	Unreachable
1	0	Covered	T22,T23,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T22,T23
DetectSt	168	Covered	T22,T23,T30
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T22,T23,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T23,T30
DebounceSt->IdleSt	163	Covered	T21,T40,T43
DetectSt->IdleSt	186	Covered	T68,T69,T70
DetectSt->StableSt	191	Covered	T22,T23,T30
IdleSt->DebounceSt	148	Covered	T21,T22,T23
StableSt->IdleSt	206	Covered	T22,T23,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T22,T23
0	1	Covered	T21,T22,T23
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T30
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T23,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T43,T62
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T68,T69,T70
DetectSt	-	-	-	-	0	1	-	Covered	T22,T23,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T23,T30
StableSt	-	-	-	-	-	-	0	Covered	T22,T23,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	165	0	0
CntIncr_A	6449837	6841	0	0
CntNoWrap_A	6449837	5829496	0	0
DetectStDropOut_A	6449837	16	0	0
DetectedOut_A	6449837	16746	0	0
DetectedPulseOut_A	6449837	48	0	0
DisabledIdleSt_A	6449837	5651839	0	0
DisabledNoDetection_A	6449837	5654120	0	0
EnterDebounceSt_A	6449837	103	0	0
EnterDetectSt_A	6449837	64	0	0
EnterStableSt_A	6449837	48	0	0
PulseIsPulse_A	6449837	48	0	0
StayInStableSt	6449837	16698	0	0
gen_high_event_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_high_level_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_sticky_sva.StableStDropOut_A	6449837	150057	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	165	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	1	0	0
T22	0	2	0	0
T23	0	2	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T30	0	2	0	0
T40	0	3	0	0
T43	0	5	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T50	0	4	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	6841	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	21	0	0
T22	0	99	0	0
T23	0	62	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T30	0	10	0	0
T40	0	126	0	0
T43	0	275	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T50	0	188	0	0
T60	0	98	0	0
T61	0	66	0	0
T62	0	308	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5829496	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	16	0	0
T68	11558	3	0	0
T69	0	1	0	0
T70	0	3	0	0
T100	703	0	0	0
T108	0	3	0	0
T109	0	3	0	0
T110	0	2	0	0
T111	0	1	0	0
T112	746	0	0	0
T113	426	0	0	0
T114	11544	0	0	0
T115	761	0	0	0
T116	424	0	0	0
T117	510	0	0	0
T118	458	0	0	0
T119	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	16746	0	0
T22	6357	773	0	0
T23	15192	75	0	0
T30	2499	18	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	28	0	0
T50	0	361	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	260	0	0
T61	0	324	0	0
T62	0	36	0	0
T68	0	19	0	0
T94	0	12	0	0
T98	406	0	0	0
T99	411	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	48	0	0
T22	6357	1	0	0
T23	15192	1	0	0
T30	2499	1	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	1	0	0
T50	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T68	0	1	0	0
T94	0	1	0	0
T98	406	0	0	0
T99	411	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5651839	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5654120	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	103	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T30	0	1	0	0
T40	0	2	0	0
T43	0	5	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T50	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	64	0	0
T22	6357	1	0	0
T23	15192	1	0	0
T30	2499	1	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	1	0	0
T50	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T68	0	4	0	0
T94	0	1	0	0
T98	406	0	0	0
T99	411	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	48	0	0
T22	6357	1	0	0
T23	15192	1	0	0
T30	2499	1	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	1	0	0
T50	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T68	0	1	0	0
T94	0	1	0	0
T98	406	0	0	0
T99	411	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	48	0	0
T22	6357	1	0	0
T23	15192	1	0	0
T30	2499	1	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	1	0	0
T50	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T68	0	1	0	0
T94	0	1	0	0
T98	406	0	0	0
T99	411	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	16698	0	0
T22	6357	772	0	0
T23	15192	74	0	0
T30	2499	17	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	27	0	0
T50	0	359	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	259	0	0
T61	0	323	0	0
T62	0	35	0	0
T68	0	18	0	0
T94	0	11	0	0
T98	406	0	0	0
T99	411	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	150057	0	0
T22	6357	53	0	0
T23	15192	46	0	0
T30	2499	168	0	0
T36	534	0	0	0
T37	501	0	0	0
T40	0	79	0	0
T50	0	241	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T60	0	38	0	0
T61	0	78	0	0
T62	0	359	0	0
T68	0	57	0	0
T94	0	105	0	0
T98	406	0	0	0
T99	411	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T21,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T21,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T9
1	0	Covered	T4,T1,T5
1	1	Covered	T2,T21,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T11
0	1	Covered	T2,T120,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T11
1	-	Covered	T2,T120,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T21,T9
DetectSt	168	Covered	T2,T9,T11
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T11
DebounceSt->IdleSt	163	Covered	T21,T33,T121
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T9,T11
IdleSt->DebounceSt	148	Covered	T2,T21,T9
StableSt->IdleSt	206	Covered	T2,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T21,T9
0	1	Covered	T2,T21,T9
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T11
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T21,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T33
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T21,T9
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T120,T33
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	69	0	0
CntIncr_A	6449837	167444	0	0
CntNoWrap_A	6449837	5829592	0	0
DetectStDropOut_A	6449837	0	0	0
DetectedOut_A	6449837	3299	0	0
DetectedPulseOut_A	6449837	33	0	0
DisabledIdleSt_A	6449837	5114630	0	0
DisabledNoDetection_A	6449837	5116859	0	0
EnterDebounceSt_A	6449837	37	0	0
EnterDetectSt_A	6449837	33	0	0
EnterStableSt_A	6449837	33	0	0
PulseIsPulse_A	6449837	33	0	0
StayInStableSt	6449837	3244	0	0
gen_high_level_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	69	0	0
T2	1117	2	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T17	9843	0	0	0
T21	7102	1	0	0
T23	0	2	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	2	0	0
T33	0	3	0	0
T38	0	2	0	0
T45	494	0	0	0
T120	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	167444	0	0
T2	1117	80	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	45	0	0
T11	0	54635	0	0
T12	0	70	0	0
T17	9843	0	0	0
T21	7102	25	0	0
T23	0	50	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	16201	0	0
T33	0	73	0	0
T38	0	30	0	0
T45	494	0	0	0
T120	0	124	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5829592	0	0
T1	36814	36318	0	0
T2	1117	714	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	3299	0	0
T2	1117	161	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	41	0	0
T11	0	58	0	0
T12	0	125	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	98	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	43	0	0
T33	0	83	0	0
T38	0	40	0	0
T44	0	340	0	0
T45	494	0	0	0
T120	0	141	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	33	0	0
T2	1117	1	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T44	0	1	0	0
T45	494	0	0	0
T120	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5114630	0	0
T1	36814	36318	0	0
T2	1117	3	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5116859	0	0
T1	36814	36332	0	0
T2	1117	3	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	37	0	0
T2	1117	1	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T17	9843	0	0	0
T21	7102	1	0	0
T23	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T38	0	1	0	0
T45	494	0	0	0
T120	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	33	0	0
T2	1117	1	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T44	0	1	0	0
T45	494	0	0	0
T120	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	33	0	0
T2	1117	1	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T44	0	1	0	0
T45	494	0	0	0
T120	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	33	0	0
T2	1117	1	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T44	0	1	0	0
T45	494	0	0	0
T120	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	3244	0	0
T2	1117	160	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	39	0	0
T11	0	56	0	0
T12	0	123	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	96	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	41	0	0
T33	0	82	0	0
T38	0	39	0	0
T44	0	338	0	0
T45	494	0	0	0
T120	0	138	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	11	0	0
T2	1117	1	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T24	492	0	0	0
T25	493	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T45	494	0	0	0
T120	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T21,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T21,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T9,T11
1	0	Covered	T1,T15,T16
1	1	Covered	T21,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T12
0	1	Covered	T128
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T12
0	1	Covered	T9,T12,T22
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T12
1	-	Covered	T9,T12,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T9,T11
DetectSt	168	Covered	T9,T11,T12
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T9,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T12
DebounceSt->IdleSt	163	Covered	T21,T11,T129
DetectSt->IdleSt	186	Covered	T128
DetectSt->StableSt	191	Covered	T9,T11,T12
IdleSt->DebounceSt	148	Covered	T21,T9,T11
StableSt->IdleSt	206	Covered	T9,T12,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T9,T11
0	1	Covered	T21,T9,T11
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T129,T108
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T128
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T12,T22
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	128	0	0
CntIncr_A	6449837	272678	0	0
CntNoWrap_A	6449837	5829533	0	0
DetectStDropOut_A	6449837	1	0	0
DetectedOut_A	6449837	74705	0	0
DetectedPulseOut_A	6449837	59	0	0
DisabledIdleSt_A	6449837	5168402	0	0
DisabledNoDetection_A	6449837	5170626	0	0
EnterDebounceSt_A	6449837	68	0	0
EnterDetectSt_A	6449837	60	0	0
EnterStableSt_A	6449837	59	0	0
PulseIsPulse_A	6449837	59	0	0
StayInStableSt	6449837	74620	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6449837	2379	0	0
gen_low_level_sva.LowLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	128	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	2	0	0
T11	0	3	0	0
T12	0	2	0	0
T21	7102	1	0	0
T22	0	4	0	0
T23	0	2	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T32	0	2	0	0
T33	0	8	0	0
T36	0	2	0	0
T37	0	2	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	272678	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	45	0	0
T11	0	54654	0	0
T12	0	70	0	0
T21	7102	26	0	0
T22	0	76	0	0
T23	0	50	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T32	0	16201	0	0
T33	0	146	0	0
T36	0	27	0	0
T37	0	18	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5829533	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	1	0	0
T69	1586	0	0	0
T128	2328	1	0	0
T130	408	0	0	0
T131	625	0	0	0
T132	987	0	0	0
T133	496	0	0	0
T134	11463	0	0	0
T135	481	0	0	0
T136	521	0	0	0
T137	4870	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	74705	0	0
T9	547	6	0	0
T10	21225	0	0	0
T11	66940	64	0	0
T12	3688	265	0	0
T22	0	95	0	0
T23	0	73	0	0
T31	27577	0	0	0
T32	0	69853	0	0
T33	0	215	0	0
T34	0	62	0	0
T35	515	0	0	0
T36	0	44	0	0
T37	0	41	0	0
T39	8559	0	0	0
T57	409	0	0	0
T138	427	0	0	0
T139	421	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	59	0	0
T9	547	1	0	0
T10	21225	0	0	0
T11	66940	1	0	0
T12	3688	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T31	27577	0	0	0
T32	0	1	0	0
T33	0	4	0	0
T34	0	1	0	0
T35	515	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	8559	0	0	0
T57	409	0	0	0
T138	427	0	0	0
T139	421	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5168402	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5170626	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	68	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T21	7102	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T32	0	1	0	0
T33	0	4	0	0
T36	0	1	0	0
T37	0	1	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	60	0	0
T9	547	1	0	0
T10	21225	0	0	0
T11	66940	1	0	0
T12	3688	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T31	27577	0	0	0
T32	0	1	0	0
T33	0	4	0	0
T34	0	1	0	0
T35	515	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	8559	0	0	0
T57	409	0	0	0
T138	427	0	0	0
T139	421	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	59	0	0
T9	547	1	0	0
T10	21225	0	0	0
T11	66940	1	0	0
T12	3688	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T31	27577	0	0	0
T32	0	1	0	0
T33	0	4	0	0
T34	0	1	0	0
T35	515	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	8559	0	0	0
T57	409	0	0	0
T138	427	0	0	0
T139	421	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	59	0	0
T9	547	1	0	0
T10	21225	0	0	0
T11	66940	1	0	0
T12	3688	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T31	27577	0	0	0
T32	0	1	0	0
T33	0	4	0	0
T34	0	1	0	0
T35	515	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	8559	0	0	0
T57	409	0	0	0
T138	427	0	0	0
T139	421	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	74620	0	0
T9	547	5	0	0
T10	21225	0	0	0
T11	66940	62	0	0
T12	3688	264	0	0
T22	0	92	0	0
T23	0	72	0	0
T31	27577	0	0	0
T32	0	69852	0	0
T33	0	209	0	0
T34	0	61	0	0
T35	515	0	0	0
T36	0	42	0	0
T37	0	39	0	0
T39	8559	0	0	0
T57	409	0	0	0
T138	427	0	0	0
T139	421	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	2379	0	0
T2	1117	2	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T9	0	1	0	0
T16	502	4	0	0
T17	9843	0	0	0
T21	7102	3	0	0
T24	492	5	0	0
T25	493	3	0	0
T26	0	5	0	0
T27	0	5	0	0
T45	494	5	0	0
T47	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	33	0	0
T9	547	1	0	0
T10	21225	0	0	0
T11	66940	0	0	0
T12	3688	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T31	27577	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	515	0	0	0
T39	8559	0	0	0
T43	0	1	0	0
T57	409	0	0	0
T138	427	0	0	0
T139	421	0	0	0
T140	0	2	0	0
T141	0	1	0	0