Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T21,T22,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T21,T22,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T9,T11
1	0	Covered	T4,T1,T5
1	1	Covered	T21,T22,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T37,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T37,T38
0	1	Covered	T38,T65,T142
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T37,T38
1	-	Covered	T38,T65,T142

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T22,T37
DetectSt	168	Covered	T22,T37,T38
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T22,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T37,T38
DebounceSt->IdleSt	163	Covered	T21,T38,T121
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T22,T37,T38
IdleSt->DebounceSt	148	Covered	T21,T22,T37
StableSt->IdleSt	206	Covered	T22,T38,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T22,T37
0	1	Covered	T21,T22,T37
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T37,T38
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T22,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T38
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T22,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T22,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T65,T142
StableSt	-	-	-	-	-	-	0	Covered	T22,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	71	0	0
CntIncr_A	6449837	96790	0	0
CntNoWrap_A	6449837	5829590	0	0
DetectStDropOut_A	6449837	0	0	0
DetectedOut_A	6449837	2227	0	0
DetectedPulseOut_A	6449837	34	0	0
DisabledIdleSt_A	6449837	5494357	0	0
DisabledNoDetection_A	6449837	5496591	0	0
EnterDebounceSt_A	6449837	38	0	0
EnterDetectSt_A	6449837	34	0	0
EnterStableSt_A	6449837	34	0	0
PulseIsPulse_A	6449837	34	0	0
StayInStableSt	6449837	2173	0	0
gen_high_level_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	71	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	1	0	0
T22	0	2	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T37	0	2	0	0
T38	0	3	0	0
T43	0	4	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T65	0	2	0	0
T71	0	2	0	0
T123	0	2	0	0
T142	0	2	0	0
T143	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	96790	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	27	0	0
T22	0	38	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T37	0	18	0	0
T38	0	127	0	0
T43	0	178	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T65	0	47	0	0
T71	0	20	0	0
T121	0	20	0	0
T142	0	63	0	0
T143	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5829590	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	2227	0	0
T22	6357	40	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	41	0	0
T38	0	144	0	0
T43	0	179	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T65	0	198	0	0
T71	0	41	0	0
T98	406	0	0	0
T99	411	0	0	0
T123	0	1	0	0
T128	0	83	0	0
T142	0	43	0	0
T143	0	154	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	34	0	0
T22	6357	1	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	1	0	0
T38	0	1	0	0
T43	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T65	0	1	0	0
T71	0	1	0	0
T98	406	0	0	0
T99	411	0	0	0
T123	0	1	0	0
T128	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5494357	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5496591	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	38	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	1	0	0
T22	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T43	0	2	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T65	0	1	0	0
T71	0	1	0	0
T121	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	34	0	0
T22	6357	1	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	1	0	0
T38	0	1	0	0
T43	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T65	0	1	0	0
T71	0	1	0	0
T98	406	0	0	0
T99	411	0	0	0
T123	0	1	0	0
T128	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	34	0	0
T22	6357	1	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	1	0	0
T38	0	1	0	0
T43	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T65	0	1	0	0
T71	0	1	0	0
T98	406	0	0	0
T99	411	0	0	0
T123	0	1	0	0
T128	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	34	0	0
T22	6357	1	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	1	0	0
T38	0	1	0	0
T43	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T65	0	1	0	0
T71	0	1	0	0
T98	406	0	0	0
T99	411	0	0	0
T123	0	1	0	0
T128	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	2173	0	0
T22	6357	38	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	39	0	0
T38	0	143	0	0
T43	0	175	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T65	0	197	0	0
T71	0	40	0	0
T98	406	0	0	0
T99	411	0	0	0
T128	0	80	0	0
T142	0	42	0	0
T143	0	152	0	0
T144	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	14	0	0
T38	12735	1	0	0
T43	301881	0	0	0
T65	0	1	0	0
T71	0	1	0	0
T75	4829	0	0	0
T83	0	1	0	0
T123	0	1	0	0
T125	0	1	0	0
T128	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	419	0	0	0
T148	492	0	0	0
T149	8186	0	0	0
T150	532	0	0	0
T151	493	0	0	0
T152	939	0	0	0
T153	521	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T21,T12,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T21,T12,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T35,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T11,T12
1	0	Covered	T1,T13,T14
1	1	Covered	T21,T12,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T35,T23
0	1	Covered	T23,T65,T128
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T35,T23
0	1	Covered	T12,T35,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T35,T23
1	-	Covered	T12,T35,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T12,T35
DetectSt	168	Covered	T12,T35,T23
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T12,T35,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T35,T23
DebounceSt->IdleSt	163	Covered	T21,T154,T155
DetectSt->IdleSt	186	Covered	T23,T65,T128
DetectSt->StableSt	191	Covered	T12,T35,T23
IdleSt->DebounceSt	148	Covered	T21,T12,T35
StableSt->IdleSt	206	Covered	T12,T35,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T12,T35
0	1	Covered	T21,T12,T35
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T35,T23
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T12,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T35,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T154,T155,T126
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T12,T35
DetectSt	-	-	-	-	1	-	-	Covered	T23,T65,T128
DetectSt	-	-	-	-	0	1	-	Covered	T12,T35,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T35,T23
StableSt	-	-	-	-	-	-	0	Covered	T12,T35,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	139	0	0
CntIncr_A	6449837	287089	0	0
CntNoWrap_A	6449837	5829522	0	0
DetectStDropOut_A	6449837	4	0	0
DetectedOut_A	6449837	121359	0	0
DetectedPulseOut_A	6449837	63	0	0
DisabledIdleSt_A	6449837	4972139	0	0
DisabledNoDetection_A	6449837	4974359	0	0
EnterDebounceSt_A	6449837	72	0	0
EnterDetectSt_A	6449837	67	0	0
EnterStableSt_A	6449837	63	0	0
PulseIsPulse_A	6449837	63	0	0
StayInStableSt	6449837	121271	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6449837	2742	0	0
gen_low_level_sva.LowLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	139	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T12	0	4	0	0
T21	7102	1	0	0
T23	0	4	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T32	0	4	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	8	0	0
T43	0	2	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T140	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	287089	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T12	0	140	0	0
T21	7102	26	0	0
T23	0	100	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T32	0	32402	0	0
T35	0	30	0	0
T36	0	27	0	0
T37	0	18	0	0
T38	0	254	0	0
T43	0	93	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T140	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5829522	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	4	0	0
T23	15192	1	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T65	0	1	0	0
T98	406	0	0	0
T99	411	0	0	0
T103	433	0	0	0
T128	0	1	0	0
T144	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	121359	0	0
T12	3688	280	0	0
T22	6357	0	0	0
T23	15192	41	0	0
T30	2499	0	0	0
T31	27577	0	0	0
T32	0	16284	0	0
T35	515	4	0	0
T36	0	26	0	0
T37	0	14	0	0
T38	0	240	0	0
T39	8559	0	0	0
T43	0	136	0	0
T51	493	0	0	0
T138	427	0	0	0
T139	421	0	0	0
T140	0	193	0	0
T156	0	87	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	63	0	0
T12	3688	2	0	0
T22	6357	0	0	0
T23	15192	1	0	0
T30	2499	0	0	0
T31	27577	0	0	0
T32	0	2	0	0
T35	515	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	4	0	0
T39	8559	0	0	0
T43	0	1	0	0
T51	493	0	0	0
T138	427	0	0	0
T139	421	0	0	0
T140	0	2	0	0
T156	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	4972139	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	4974359	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	72	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T12	0	2	0	0
T21	7102	1	0	0
T23	0	2	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	4	0	0
T43	0	1	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T140	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	67	0	0
T12	3688	2	0	0
T22	6357	0	0	0
T23	15192	2	0	0
T30	2499	0	0	0
T31	27577	0	0	0
T32	0	2	0	0
T35	515	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	4	0	0
T39	8559	0	0	0
T43	0	1	0	0
T51	493	0	0	0
T138	427	0	0	0
T139	421	0	0	0
T140	0	2	0	0
T156	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	63	0	0
T12	3688	2	0	0
T22	6357	0	0	0
T23	15192	1	0	0
T30	2499	0	0	0
T31	27577	0	0	0
T32	0	2	0	0
T35	515	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	4	0	0
T39	8559	0	0	0
T43	0	1	0	0
T51	493	0	0	0
T138	427	0	0	0
T139	421	0	0	0
T140	0	2	0	0
T156	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	63	0	0
T12	3688	2	0	0
T22	6357	0	0	0
T23	15192	1	0	0
T30	2499	0	0	0
T31	27577	0	0	0
T32	0	2	0	0
T35	515	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	4	0	0
T39	8559	0	0	0
T43	0	1	0	0
T51	493	0	0	0
T138	427	0	0	0
T139	421	0	0	0
T140	0	2	0	0
T156	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	121271	0	0
T12	3688	277	0	0
T22	6357	0	0	0
T23	15192	40	0	0
T30	2499	0	0	0
T31	27577	0	0	0
T32	0	16282	0	0
T35	515	3	0	0
T36	0	25	0	0
T37	0	13	0	0
T38	0	234	0	0
T39	8559	0	0	0
T43	0	135	0	0
T51	493	0	0	0
T138	427	0	0	0
T139	421	0	0	0
T140	0	191	0	0
T156	0	85	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	2742	0	0
T2	1117	2	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T13	630	3	0	0
T14	828	4	0	0
T15	29746	0	0	0
T16	502	5	0	0
T17	9843	0	0	0
T21	7102	7	0	0
T24	0	4	0	0
T25	0	5	0	0
T26	0	5	0	0
T45	0	4	0	0
T47	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	38	0	0
T12	3688	1	0	0
T22	6357	0	0	0
T23	15192	1	0	0
T30	2499	0	0	0
T31	27577	0	0	0
T32	0	2	0	0
T35	515	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	8559	0	0	0
T43	0	1	0	0
T51	493	0	0	0
T138	427	0	0	0
T139	421	0	0	0
T140	0	2	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T5,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T21,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T21,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T9
1	0	Covered	T1,T5,T15
1	1	Covered	T2,T21,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T11
0	1	Covered	T2,T12,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T11
1	-	Covered	T2,T12,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T21,T9
DetectSt	168	Covered	T2,T9,T11
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T11
DebounceSt->IdleSt	163	Covered	T21,T22,T158
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T9,T11
IdleSt->DebounceSt	148	Covered	T2,T21,T9
StableSt->IdleSt	206	Covered	T2,T12,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T21,T9
0	1	Covered	T2,T21,T9
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T11
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T21,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T158,T146,T159
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T21,T9
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T12,T23
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	119	0	0
CntIncr_A	6449837	120891	0	0
CntNoWrap_A	6449837	5829542	0	0
DetectStDropOut_A	6449837	0	0	0
DetectedOut_A	6449837	113620	0	0
DetectedPulseOut_A	6449837	57	0	0
DisabledIdleSt_A	6449837	5474808	0	0
DisabledNoDetection_A	6449837	5477043	0	0
EnterDebounceSt_A	6449837	63	0	0
EnterDetectSt_A	6449837	57	0	0
EnterStableSt_A	6449837	57	0	0
PulseIsPulse_A	6449837	57	0	0
StayInStableSt	6449837	113534	0	0
gen_high_level_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	119	0	0
T2	1117	2	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T12	0	4	0	0
T17	9843	0	0	0
T21	7102	1	0	0
T23	0	6	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	6	0	0
T33	0	2	0	0
T36	0	2	0	0
T45	494	0	0	0
T120	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	120891	0	0
T2	1117	80	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	45	0	0
T11	0	19	0	0
T12	0	140	0	0
T17	9843	0	0	0
T21	7102	26	0	0
T22	0	26	0	0
T23	0	187	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	48603	0	0
T36	0	27	0	0
T45	494	0	0	0
T120	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5829542	0	0
T1	36814	36318	0	0
T2	1117	714	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	113620	0	0
T2	1117	43	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	93	0	0
T11	0	64	0	0
T12	0	236	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	502	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	16329	0	0
T33	0	16	0	0
T36	0	97	0	0
T38	0	79	0	0
T45	494	0	0	0
T120	0	207	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	57	0	0
T2	1117	1	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	3	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T45	494	0	0	0
T120	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5474808	0	0
T1	36814	36318	0	0
T2	1117	3	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5477043	0	0
T1	36814	36332	0	0
T2	1117	3	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	63	0	0
T2	1117	1	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T17	9843	0	0	0
T21	7102	1	0	0
T22	0	1	0	0
T23	0	3	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	3	0	0
T36	0	1	0	0
T45	494	0	0	0
T120	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	57	0	0
T2	1117	1	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	3	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T45	494	0	0	0
T120	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	57	0	0
T2	1117	1	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	3	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T45	494	0	0	0
T120	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	57	0	0
T2	1117	1	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	3	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T45	494	0	0	0
T120	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	113534	0	0
T2	1117	42	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	91	0	0
T11	0	62	0	0
T12	0	233	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	498	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	16325	0	0
T33	0	15	0	0
T36	0	95	0	0
T38	0	76	0	0
T45	494	0	0	0
T120	0	205	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	28	0	0
T2	1117	1	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T12	0	1	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	2	0	0
T24	492	0	0	0
T25	493	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T38	0	1	0	0
T45	494	0	0	0
T143	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T21,T22,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T21,T22,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T32,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T9,T11
1	0	Covered	T1,T5,T15
1	1	Covered	T21,T22,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T32,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T32,T34
0	1	Covered	T32,T34,T43
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T32,T34
1	-	Covered	T32,T34,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T22,T32
DetectSt	168	Covered	T22,T32,T34
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T22,T32,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T32,T34
DebounceSt->IdleSt	163	Covered	T21,T32,T155
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T22,T32,T34
IdleSt->DebounceSt	148	Covered	T21,T22,T32
StableSt->IdleSt	206	Covered	T22,T32,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T22,T32
0	1	Covered	T21,T22,T32
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T32,T34
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T22,T32
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T32,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T22,T32
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T22,T32,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T34,T43
StableSt	-	-	-	-	-	-	0	Covered	T22,T32,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	82	0	0
CntIncr_A	6449837	200575	0	0
CntNoWrap_A	6449837	5829579	0	0
DetectStDropOut_A	6449837	0	0	0
DetectedOut_A	6449837	76947	0	0
DetectedPulseOut_A	6449837	39	0	0
DisabledIdleSt_A	6449837	5149927	0	0
DisabledNoDetection_A	6449837	5152159	0	0
EnterDebounceSt_A	6449837	43	0	0
EnterDetectSt_A	6449837	39	0	0
EnterStableSt_A	6449837	39	0	0
PulseIsPulse_A	6449837	39	0	0
StayInStableSt	6449837	76887	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6449837	6189	0	0
gen_low_level_sva.LowLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	82	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	1	0	0
T22	0	2	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T32	0	3	0	0
T34	0	4	0	0
T43	0	4	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T140	0	4	0	0
T141	0	2	0	0
T143	0	2	0	0
T157	0	2	0	0
T160	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	200575	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	26	0	0
T22	0	38	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T32	0	32402	0	0
T34	0	190	0	0
T43	0	178	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T140	0	76	0	0
T141	0	33	0	0
T143	0	57	0	0
T157	0	14072	0	0
T160	0	75	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5829579	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	76947	0	0
T22	6357	100	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T32	0	11952	0	0
T34	0	259	0	0
T36	534	0	0	0
T37	501	0	0	0
T43	0	263	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T98	406	0	0	0
T99	411	0	0	0
T140	0	126	0	0
T141	0	18	0	0
T143	0	140	0	0
T157	0	38	0	0
T160	0	43	0	0
T162	0	122	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	39	0	0
T22	6357	1	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T36	534	0	0	0
T37	501	0	0	0
T43	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T98	406	0	0	0
T99	411	0	0	0
T140	0	2	0	0
T141	0	1	0	0
T143	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5149927	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5152159	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	43	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	1	0	0
T22	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T32	0	2	0	0
T34	0	2	0	0
T43	0	2	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T140	0	2	0	0
T141	0	1	0	0
T143	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	39	0	0
T22	6357	1	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T36	534	0	0	0
T37	501	0	0	0
T43	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T98	406	0	0	0
T99	411	0	0	0
T140	0	2	0	0
T141	0	1	0	0
T143	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	39	0	0
T22	6357	1	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T36	534	0	0	0
T37	501	0	0	0
T43	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T98	406	0	0	0
T99	411	0	0	0
T140	0	2	0	0
T141	0	1	0	0
T143	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	39	0	0
T22	6357	1	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T36	534	0	0	0
T37	501	0	0	0
T43	0	2	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T98	406	0	0	0
T99	411	0	0	0
T140	0	2	0	0
T141	0	1	0	0
T143	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	76887	0	0
T22	6357	98	0	0
T23	15192	0	0	0
T30	2499	0	0	0
T32	0	11951	0	0
T34	0	256	0	0
T36	534	0	0	0
T37	501	0	0	0
T43	0	261	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T98	406	0	0	0
T99	411	0	0	0
T140	0	123	0	0
T141	0	17	0	0
T143	0	139	0	0
T157	0	36	0	0
T160	0	41	0	0
T162	0	120	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	6189	0	0
T1	36814	40	0	0
T2	1117	1	0	0
T3	33204	27	0	0
T5	6265	37	0	0
T6	16495	28	0	0
T7	0	13	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	26	0	0
T16	502	9	0	0
T17	9843	28	0	0
T21	0	32	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	18	0	0
T32	102709	1	0	0
T34	0	1	0	0
T43	0	2	0	0
T50	2275	0	0	0
T58	458	0	0	0
T59	21900	0	0	0
T88	505	0	0	0
T120	994	0	0	0
T128	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T146	0	2	0	0
T163	0	1	0	0
T164	434	0	0	0
T165	1369	0	0	0
T166	402	0	0	0
T167	406	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T5,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T21,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T21,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T9,T11
1	0	Covered	T1,T5,T15
1	1	Covered	T21,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T12
0	1	Covered	T43,T168
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T12
0	1	Covered	T12,T35,T22
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T12
1	-	Covered	T12,T35,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T9,T11
DetectSt	168	Covered	T9,T11,T12
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T9,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T12
DebounceSt->IdleSt	163	Covered	T21,T11,T161
DetectSt->IdleSt	186	Covered	T43,T168
DetectSt->StableSt	191	Covered	T9,T11,T12
IdleSt->DebounceSt	148	Covered	T21,T9,T11
StableSt->IdleSt	206	Covered	T12,T35,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T9,T11
0	1	Covered	T21,T9,T11
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T161,T129
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T43,T168
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T35,T22
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	113	0	0
CntIncr_A	6449837	262763	0	0
CntNoWrap_A	6449837	5829548	0	0
DetectStDropOut_A	6449837	2	0	0
DetectedOut_A	6449837	105550	0	0
DetectedPulseOut_A	6449837	49	0	0
DisabledIdleSt_A	6449837	5216338	0	0
DisabledNoDetection_A	6449837	5218567	0	0
EnterDebounceSt_A	6449837	63	0	0
EnterDetectSt_A	6449837	51	0	0
EnterStableSt_A	6449837	49	0	0
PulseIsPulse_A	6449837	49	0	0
StayInStableSt	6449837	105479	0	0
gen_high_level_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	113	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	2	0	0
T11	0	3	0	0
T12	0	4	0	0
T21	7102	1	0	0
T22	0	2	0	0
T23	0	4	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T33	0	4	0	0
T35	0	2	0	0
T38	0	2	0	0
T43	0	6	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	262763	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	45	0	0
T11	0	54654	0	0
T12	0	140	0	0
T21	7102	25	0	0
T22	0	38	0	0
T23	0	100	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T33	0	62	0	0
T35	0	30	0	0
T38	0	30	0	0
T43	0	263	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5829548	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	2	0	0
T43	301881	1	0	0
T60	2165	0	0	0
T75	4829	0	0	0
T148	492	0	0	0
T149	8186	0	0	0
T150	532	0	0	0
T151	493	0	0	0
T152	939	0	0	0
T153	521	0	0	0
T168	0	1	0	0
T169	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	105550	0	0
T9	547	41	0	0
T10	21225	0	0	0
T11	66940	95	0	0
T12	3688	304	0	0
T22	0	22	0	0
T23	0	144	0	0
T31	27577	0	0	0
T33	0	127	0	0
T35	515	2	0	0
T38	0	125	0	0
T39	8559	0	0	0
T43	0	374	0	0
T57	409	0	0	0
T138	427	0	0	0
T139	421	0	0	0
T157	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	49	0	0
T9	547	1	0	0
T10	21225	0	0	0
T11	66940	1	0	0
T12	3688	2	0	0
T22	0	1	0	0
T23	0	2	0	0
T31	27577	0	0	0
T33	0	2	0	0
T35	515	1	0	0
T38	0	1	0	0
T39	8559	0	0	0
T43	0	2	0	0
T57	409	0	0	0
T138	427	0	0	0
T139	421	0	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5216338	0	0
T1	36814	36318	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5218567	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	63	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T12	0	2	0	0
T21	7102	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T33	0	2	0	0
T35	0	1	0	0
T38	0	1	0	0
T43	0	3	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	51	0	0
T9	547	1	0	0
T10	21225	0	0	0
T11	66940	1	0	0
T12	3688	2	0	0
T22	0	1	0	0
T23	0	2	0	0
T31	27577	0	0	0
T33	0	2	0	0
T35	515	1	0	0
T38	0	1	0	0
T39	8559	0	0	0
T43	0	3	0	0
T57	409	0	0	0
T138	427	0	0	0
T139	421	0	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	49	0	0
T9	547	1	0	0
T10	21225	0	0	0
T11	66940	1	0	0
T12	3688	2	0	0
T22	0	1	0	0
T23	0	2	0	0
T31	27577	0	0	0
T33	0	2	0	0
T35	515	1	0	0
T38	0	1	0	0
T39	8559	0	0	0
T43	0	2	0	0
T57	409	0	0	0
T138	427	0	0	0
T139	421	0	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	49	0	0
T9	547	1	0	0
T10	21225	0	0	0
T11	66940	1	0	0
T12	3688	2	0	0
T22	0	1	0	0
T23	0	2	0	0
T31	27577	0	0	0
T33	0	2	0	0
T35	515	1	0	0
T38	0	1	0	0
T39	8559	0	0	0
T43	0	2	0	0
T57	409	0	0	0
T138	427	0	0	0
T139	421	0	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	105479	0	0
T9	547	39	0	0
T10	21225	0	0	0
T11	66940	93	0	0
T12	3688	301	0	0
T22	0	21	0	0
T23	0	141	0	0
T31	27577	0	0	0
T33	0	125	0	0
T35	515	1	0	0
T38	0	123	0	0
T39	8559	0	0	0
T43	0	371	0	0
T57	409	0	0	0
T138	427	0	0	0
T139	421	0	0	0
T157	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	27	0	0
T12	3688	1	0	0
T22	6357	1	0	0
T23	15192	1	0	0
T30	2499	0	0	0
T31	27577	0	0	0
T33	0	2	0	0
T35	515	1	0	0
T39	8559	0	0	0
T43	0	1	0	0
T51	493	0	0	0
T62	0	1	0	0
T121	0	1	0	0
T138	427	0	0	0
T139	421	0	0	0
T143	0	1	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T21,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T21,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T12,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T9
1	0	Covered	T1,T5,T15
1	1	Covered	T2,T21,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T23
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T23
0	1	Covered	T2,T12,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T12,T23
1	-	Covered	T2,T12,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T21,T12
DetectSt	168	Covered	T2,T12,T23
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T12,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T12,T23
DebounceSt->IdleSt	163	Covered	T21,T23,T121
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T12,T23
IdleSt->DebounceSt	148	Covered	T2,T21,T12
StableSt->IdleSt	206	Covered	T2,T12,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T21,T12
0	1	Covered	T2,T21,T12
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T23
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T21,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T12,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T146,T125
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T21,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T12,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T12,T23
StableSt	-	-	-	-	-	-	0	Covered	T2,T12,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	82	0	0
CntIncr_A	6449837	101690	0	0
CntNoWrap_A	6449837	5829579	0	0
DetectStDropOut_A	6449837	0	0	0
DetectedOut_A	6449837	16771	0	0
DetectedPulseOut_A	6449837	38	0	0
DisabledIdleSt_A	6449837	5319268	0	0
DisabledNoDetection_A	6449837	5321490	0	0
EnterDebounceSt_A	6449837	45	0	0
EnterDetectSt_A	6449837	38	0	0
EnterStableSt_A	6449837	38	0	0
PulseIsPulse_A	6449837	38	0	0
StayInStableSt	6449837	16711	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6449837	5842	0	0
gen_low_level_sva.LowLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	82	0	0
T2	1117	4	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T12	0	2	0	0
T17	9843	0	0	0
T21	7102	1	0	0
T23	0	3	0	0
T24	492	0	0	0
T25	493	0	0	0
T38	0	4	0	0
T43	0	4	0	0
T45	494	0	0	0
T65	0	2	0	0
T157	0	2	0	0
T160	0	2	0	0
T161	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	101690	0	0
T2	1117	160	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T12	0	70	0	0
T17	9843	0	0	0
T21	7102	26	0	0
T23	0	137	0	0
T24	492	0	0	0
T25	493	0	0	0
T38	0	194	0	0
T43	0	170	0	0
T45	494	0	0	0
T65	0	47	0	0
T157	0	14072	0	0
T160	0	75	0	0
T161	0	55002	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5829579	0	0
T1	36814	36318	0	0
T2	1117	712	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	16771	0	0
T2	1117	174	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T12	0	16	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	165	0	0
T24	492	0	0	0
T25	493	0	0	0
T38	0	84	0	0
T43	0	85	0	0
T45	494	0	0	0
T65	0	106	0	0
T129	0	39	0	0
T157	0	14111	0	0
T160	0	42	0	0
T161	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	38	0	0
T2	1117	2	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T12	0	1	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T38	0	2	0	0
T43	0	2	0	0
T45	494	0	0	0
T65	0	1	0	0
T129	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5319268	0	0
T1	36814	36318	0	0
T2	1117	3	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5321490	0	0
T1	36814	36332	0	0
T2	1117	3	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	45	0	0
T2	1117	2	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T12	0	1	0	0
T17	9843	0	0	0
T21	7102	1	0	0
T23	0	2	0	0
T24	492	0	0	0
T25	493	0	0	0
T38	0	2	0	0
T43	0	2	0	0
T45	494	0	0	0
T65	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	38	0	0
T2	1117	2	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T12	0	1	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T38	0	2	0	0
T43	0	2	0	0
T45	494	0	0	0
T65	0	1	0	0
T129	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	38	0	0
T2	1117	2	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T12	0	1	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T38	0	2	0	0
T43	0	2	0	0
T45	494	0	0	0
T65	0	1	0	0
T129	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	38	0	0
T2	1117	2	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T12	0	1	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T38	0	2	0	0
T43	0	2	0	0
T45	494	0	0	0
T65	0	1	0	0
T129	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	16711	0	0
T2	1117	172	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T12	0	15	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	164	0	0
T24	492	0	0	0
T25	493	0	0	0
T38	0	81	0	0
T43	0	82	0	0
T45	494	0	0	0
T65	0	105	0	0
T129	0	37	0	0
T157	0	14109	0	0
T160	0	40	0	0
T161	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5842	0	0
T1	36814	37	0	0
T2	1117	2	0	0
T3	33204	27	0	0
T5	6265	28	0	0
T6	16495	32	0	0
T7	0	13	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	33	0	0
T16	502	7	0	0
T17	9843	27	0	0
T21	0	28	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	16	0	0
T2	1117	2	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T12	0	1	0	0
T17	9843	0	0	0
T21	7102	0	0	0
T23	0	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T45	494	0	0	0
T65	0	1	0	0
T146	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T170	0	1	0	0