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Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.69 95.65 85.71 83.33 95.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.69 95.65 85.71 83.33 95.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.26 93.48 85.71 83.33 90.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.26 93.48 85.71 83.33 90.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T5,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT1,T5,T15
11CoveredT1,T5,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT21,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT4,T1,T5 VC_COV_UNR
1CoveredT21,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT11,T12,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT21,T11,T12
10CoveredT1,T5,T15
11CoveredT21,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT11,T12,T36
01CoveredT12,T32,T140
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT11,T12,T36
01CoveredT12,T36,T33
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT11,T12,T36
1-CoveredT12,T36,T33

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T21,T11,T12
DetectSt 168 Covered T11,T12,T36
IdleSt 163 Covered T4,T1,T5
StableSt 191 Covered T11,T12,T36


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T11,T12,T36
DebounceSt->IdleSt 163 Covered T21,T22,T171
DetectSt->IdleSt 186 Covered T12,T32,T140
DetectSt->StableSt 191 Covered T11,T12,T36
IdleSt->DebounceSt 148 Covered T21,T11,T12
StableSt->IdleSt 206 Covered T12,T36,T33



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T21,T11,T12
0 1 Covered T21,T11,T12
0 0 Excluded T4,T1,T5 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T11,T12,T36
0 Covered T4,T1,T5


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T21,T11,T12
IdleSt 0 - - - - - - Covered T1,T5,T15
DebounceSt - 1 - - - - - Covered T21,T63
DebounceSt - 0 1 1 - - - Covered T11,T12,T36
DebounceSt - 0 1 0 - - - Covered T171,T146,T172
DebounceSt - 0 0 - - - - Covered T21,T11,T12
DetectSt - - - - 1 - - Covered T12,T32,T140
DetectSt - - - - 0 1 - Covered T11,T12,T36
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T12,T36,T33
StableSt - - - - - - 0 Covered T11,T12,T36
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 6449837 135 0 0
CntIncr_A 6449837 249924 0 0
CntNoWrap_A 6449837 5829526 0 0
DetectStDropOut_A 6449837 4 0 0
DetectedOut_A 6449837 201599 0 0
DetectedPulseOut_A 6449837 60 0 0
DisabledIdleSt_A 6449837 4927713 0 0
DisabledNoDetection_A 6449837 4929935 0 0
EnterDebounceSt_A 6449837 73 0 0
EnterDetectSt_A 6449837 64 0 0
EnterStableSt_A 6449837 60 0 0
PulseIsPulse_A 6449837 60 0 0
StayInStableSt 6449837 201513 0 0
gen_high_level_sva.HighLevelEvent_A 6449837 5831944 0 0
gen_not_sticky_sva.StableStDropOut_A 6449837 34 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 135 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T11 0 2 0 0
T12 0 4 0 0
T21 7102 1 0 0
T24 492 0 0 0
T25 493 0 0 0
T26 506 0 0 0
T28 769 0 0 0
T32 0 4 0 0
T33 0 4 0 0
T36 0 2 0 0
T37 0 2 0 0
T38 0 4 0 0
T43 0 4 0 0
T45 494 0 0 0
T46 403 0 0 0
T47 429 0 0 0
T140 0 6 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 249924 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T11 0 19 0 0
T12 0 140 0 0
T21 7102 27 0 0
T22 0 25 0 0
T24 492 0 0 0
T25 493 0 0 0
T26 506 0 0 0
T28 769 0 0 0
T32 0 32402 0 0
T33 0 73 0 0
T36 0 27 0 0
T37 0 18 0 0
T38 0 60 0 0
T43 0 186 0 0
T45 494 0 0 0
T46 403 0 0 0
T47 429 0 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5829526 0 0
T1 36814 36318 0 0
T2 1117 716 0 0
T3 33204 32781 0 0
T4 402 1 0 0
T5 6265 5864 0 0
T13 630 229 0 0
T14 828 427 0 0
T15 29746 29322 0 0
T16 502 101 0 0
T17 9843 9435 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 4 0 0
T12 3688 1 0 0
T22 6357 0 0 0
T23 15192 0 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T32 0 1 0 0
T35 515 0 0 0
T39 8559 0 0 0
T51 493 0 0 0
T138 427 0 0 0
T139 421 0 0 0
T140 0 1 0 0
T173 0 1 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 201599 0 0
T11 66940 63 0 0
T12 3688 130 0 0
T22 6357 0 0 0
T23 15192 0 0 0
T31 27577 0 0 0
T32 0 44 0 0
T33 0 195 0 0
T35 515 0 0 0
T36 0 26 0 0
T37 0 74 0 0
T38 0 84 0 0
T39 8559 0 0 0
T43 0 144 0 0
T51 493 0 0 0
T138 427 0 0 0
T139 421 0 0 0
T140 0 47 0 0
T160 0 161 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 60 0 0
T11 66940 1 0 0
T12 3688 1 0 0
T22 6357 0 0 0
T23 15192 0 0 0
T31 27577 0 0 0
T32 0 1 0 0
T33 0 2 0 0
T35 515 0 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 0 2 0 0
T39 8559 0 0 0
T43 0 2 0 0
T51 493 0 0 0
T138 427 0 0 0
T139 421 0 0 0
T140 0 2 0 0
T160 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 4927713 0 0
T1 36814 36318 0 0
T2 1117 716 0 0
T3 33204 32781 0 0
T4 402 1 0 0
T5 6265 5864 0 0
T13 630 229 0 0
T14 828 427 0 0
T15 29746 29322 0 0
T16 502 101 0 0
T17 9843 9435 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 4929935 0 0
T1 36814 36332 0 0
T2 1117 717 0 0
T3 33204 32785 0 0
T4 402 2 0 0
T5 6265 5865 0 0
T13 630 230 0 0
T14 828 428 0 0
T15 29746 29326 0 0
T16 502 102 0 0
T17 9843 9437 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 73 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T11 0 1 0 0
T12 0 2 0 0
T21 7102 1 0 0
T22 0 1 0 0
T24 492 0 0 0
T25 493 0 0 0
T26 506 0 0 0
T28 769 0 0 0
T32 0 2 0 0
T33 0 2 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 0 2 0 0
T43 0 2 0 0
T45 494 0 0 0
T46 403 0 0 0
T47 429 0 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 64 0 0
T11 66940 1 0 0
T12 3688 2 0 0
T22 6357 0 0 0
T23 15192 0 0 0
T31 27577 0 0 0
T32 0 2 0 0
T33 0 2 0 0
T35 515 0 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 0 2 0 0
T39 8559 0 0 0
T43 0 2 0 0
T51 493 0 0 0
T138 427 0 0 0
T139 421 0 0 0
T140 0 3 0 0
T160 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 60 0 0
T11 66940 1 0 0
T12 3688 1 0 0
T22 6357 0 0 0
T23 15192 0 0 0
T31 27577 0 0 0
T32 0 1 0 0
T33 0 2 0 0
T35 515 0 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 0 2 0 0
T39 8559 0 0 0
T43 0 2 0 0
T51 493 0 0 0
T138 427 0 0 0
T139 421 0 0 0
T140 0 2 0 0
T160 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 60 0 0
T11 66940 1 0 0
T12 3688 1 0 0
T22 6357 0 0 0
T23 15192 0 0 0
T31 27577 0 0 0
T32 0 1 0 0
T33 0 2 0 0
T35 515 0 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 0 2 0 0
T39 8559 0 0 0
T43 0 2 0 0
T51 493 0 0 0
T138 427 0 0 0
T139 421 0 0 0
T140 0 2 0 0
T160 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 201513 0 0
T11 66940 61 0 0
T12 3688 129 0 0
T22 6357 0 0 0
T23 15192 0 0 0
T31 27577 0 0 0
T32 0 42 0 0
T33 0 193 0 0
T35 515 0 0 0
T36 0 25 0 0
T37 0 72 0 0
T38 0 81 0 0
T39 8559 0 0 0
T43 0 141 0 0
T51 493 0 0 0
T138 427 0 0 0
T139 421 0 0 0
T140 0 45 0 0
T160 0 159 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5831944 0 0
T1 36814 36332 0 0
T2 1117 717 0 0
T3 33204 32785 0 0
T4 402 2 0 0
T5 6265 5865 0 0
T13 630 230 0 0
T14 828 428 0 0
T15 29746 29326 0 0
T16 502 102 0 0
T17 9843 9437 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 34 0 0
T12 3688 1 0 0
T22 6357 0 0 0
T23 15192 0 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T33 0 2 0 0
T35 515 0 0 0
T36 0 1 0 0
T38 0 1 0 0
T39 8559 0 0 0
T43 0 1 0 0
T51 493 0 0 0
T65 0 2 0 0
T122 0 1 0 0
T138 427 0 0 0
T139 421 0 0 0
T140 0 2 0 0
T161 0 1 0 0
T162 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211885.71
Logical211885.71
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T5,T15
1CoveredT4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T5,T15
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT21,T12,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT4,T1,T5 VC_COV_UNR
1CoveredT21,T12,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT12,T23,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT21,T11,T12
10CoveredT1,T5,T15
11CoveredT21,T12,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT12,T23,T33
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT12,T23,T33
01CoveredT12,T23,T43
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT12,T23,T33
1-CoveredT12,T23,T43

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T21,T12,T23
DetectSt 168 Covered T12,T23,T33
IdleSt 163 Covered T4,T1,T5
StableSt 191 Covered T12,T23,T33


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T12,T23,T33
DebounceSt->IdleSt 163 Covered T21,T170,T63
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T12,T23,T33
IdleSt->DebounceSt 148 Covered T21,T12,T23
StableSt->IdleSt 206 Covered T12,T23,T33



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T21,T12,T23
0 1 Covered T21,T12,T23
0 0 Excluded T4,T1,T5 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T12,T23,T33
0 Covered T4,T1,T5


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T21,T12,T23
IdleSt 0 - - - - - - Covered T4,T1,T5
DebounceSt - 1 - - - - - Covered T21,T63
DebounceSt - 0 1 1 - - - Covered T12,T23,T33
DebounceSt - 0 1 0 - - - Covered T170
DebounceSt - 0 0 - - - - Covered T21,T12,T23
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T12,T23,T33
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T12,T23,T43
StableSt - - - - - - 0 Covered T12,T23,T33
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 6449837 77 0 0
CntIncr_A 6449837 73185 0 0
CntNoWrap_A 6449837 5829584 0 0
DetectStDropOut_A 6449837 0 0 0
DetectedOut_A 6449837 61966 0 0
DetectedPulseOut_A 6449837 37 0 0
DisabledIdleSt_A 6449837 5465468 0 0
DisabledNoDetection_A 6449837 5467696 0 0
EnterDebounceSt_A 6449837 40 0 0
EnterDetectSt_A 6449837 37 0 0
EnterStableSt_A 6449837 37 0 0
PulseIsPulse_A 6449837 37 0 0
StayInStableSt 6449837 61908 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 6449837 5849 0 0
gen_low_level_sva.LowLevelEvent_A 6449837 5831944 0 0
gen_not_sticky_sva.StableStDropOut_A 6449837 16 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 77 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T12 0 4 0 0
T21 7102 1 0 0
T23 0 4 0 0
T24 492 0 0 0
T25 493 0 0 0
T26 506 0 0 0
T28 769 0 0 0
T33 0 2 0 0
T34 0 2 0 0
T38 0 2 0 0
T43 0 4 0 0
T45 494 0 0 0
T46 403 0 0 0
T47 429 0 0 0
T65 0 4 0 0
T141 0 2 0 0
T157 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 73185 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T12 0 140 0 0
T21 7102 26 0 0
T23 0 100 0 0
T24 492 0 0 0
T25 493 0 0 0
T26 506 0 0 0
T28 769 0 0 0
T33 0 31 0 0
T34 0 95 0 0
T38 0 97 0 0
T43 0 178 0 0
T45 494 0 0 0
T46 403 0 0 0
T47 429 0 0 0
T65 0 94 0 0
T141 0 33 0 0
T157 0 14072 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5829584 0 0
T1 36814 36318 0 0
T2 1117 716 0 0
T3 33204 32781 0 0
T4 402 1 0 0
T5 6265 5864 0 0
T13 630 229 0 0
T14 828 427 0 0
T15 29746 29322 0 0
T16 502 101 0 0
T17 9843 9435 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 61966 0 0
T12 3688 189 0 0
T22 6357 0 0 0
T23 15192 133 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T33 0 87 0 0
T34 0 39 0 0
T35 515 0 0 0
T38 0 147 0 0
T39 8559 0 0 0
T43 0 86 0 0
T51 493 0 0 0
T65 0 81 0 0
T138 427 0 0 0
T139 421 0 0 0
T141 0 18 0 0
T157 0 37 0 0
T174 0 56 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 37 0 0
T12 3688 2 0 0
T22 6357 0 0 0
T23 15192 2 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T33 0 1 0 0
T34 0 1 0 0
T35 515 0 0 0
T38 0 1 0 0
T39 8559 0 0 0
T43 0 2 0 0
T51 493 0 0 0
T65 0 2 0 0
T138 427 0 0 0
T139 421 0 0 0
T141 0 1 0 0
T157 0 1 0 0
T174 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5465468 0 0
T1 36814 36318 0 0
T2 1117 716 0 0
T3 33204 32781 0 0
T4 402 1 0 0
T5 6265 5864 0 0
T13 630 229 0 0
T14 828 427 0 0
T15 29746 29322 0 0
T16 502 101 0 0
T17 9843 9435 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5467696 0 0
T1 36814 36332 0 0
T2 1117 717 0 0
T3 33204 32785 0 0
T4 402 2 0 0
T5 6265 5865 0 0
T13 630 230 0 0
T14 828 428 0 0
T15 29746 29326 0 0
T16 502 102 0 0
T17 9843 9437 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 40 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T12 0 2 0 0
T21 7102 1 0 0
T23 0 2 0 0
T24 492 0 0 0
T25 493 0 0 0
T26 506 0 0 0
T28 769 0 0 0
T33 0 1 0 0
T34 0 1 0 0
T38 0 1 0 0
T43 0 2 0 0
T45 494 0 0 0
T46 403 0 0 0
T47 429 0 0 0
T65 0 2 0 0
T141 0 1 0 0
T157 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 37 0 0
T12 3688 2 0 0
T22 6357 0 0 0
T23 15192 2 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T33 0 1 0 0
T34 0 1 0 0
T35 515 0 0 0
T38 0 1 0 0
T39 8559 0 0 0
T43 0 2 0 0
T51 493 0 0 0
T65 0 2 0 0
T138 427 0 0 0
T139 421 0 0 0
T141 0 1 0 0
T157 0 1 0 0
T174 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 37 0 0
T12 3688 2 0 0
T22 6357 0 0 0
T23 15192 2 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T33 0 1 0 0
T34 0 1 0 0
T35 515 0 0 0
T38 0 1 0 0
T39 8559 0 0 0
T43 0 2 0 0
T51 493 0 0 0
T65 0 2 0 0
T138 427 0 0 0
T139 421 0 0 0
T141 0 1 0 0
T157 0 1 0 0
T174 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 37 0 0
T12 3688 2 0 0
T22 6357 0 0 0
T23 15192 2 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T33 0 1 0 0
T34 0 1 0 0
T35 515 0 0 0
T38 0 1 0 0
T39 8559 0 0 0
T43 0 2 0 0
T51 493 0 0 0
T65 0 2 0 0
T138 427 0 0 0
T139 421 0 0 0
T141 0 1 0 0
T157 0 1 0 0
T174 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 61908 0 0
T12 3688 186 0 0
T22 6357 0 0 0
T23 15192 131 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T33 0 85 0 0
T34 0 37 0 0
T35 515 0 0 0
T38 0 145 0 0
T39 8559 0 0 0
T43 0 83 0 0
T51 493 0 0 0
T65 0 78 0 0
T138 427 0 0 0
T139 421 0 0 0
T141 0 17 0 0
T157 0 35 0 0
T174 0 54 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5849 0 0
T1 36814 31 0 0
T2 1117 2 0 0
T3 33204 34 0 0
T5 6265 24 0 0
T6 16495 30 0 0
T7 0 13 0 0
T13 630 0 0 0
T14 828 0 0 0
T15 29746 28 0 0
T16 502 6 0 0
T17 9843 31 0 0
T21 0 17 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5831944 0 0
T1 36814 36332 0 0
T2 1117 717 0 0
T3 33204 32785 0 0
T4 402 2 0 0
T5 6265 5865 0 0
T13 630 230 0 0
T14 828 428 0 0
T15 29746 29326 0 0
T16 502 102 0 0
T17 9843 9437 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 16 0 0
T12 3688 1 0 0
T22 6357 0 0 0
T23 15192 2 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T35 515 0 0 0
T39 8559 0 0 0
T43 0 1 0 0
T51 493 0 0 0
T65 0 1 0 0
T71 0 1 0 0
T138 427 0 0 0
T139 421 0 0 0
T141 0 1 0 0
T145 0 1 0 0
T146 0 2 0 0
T175 0 2 0 0
T176 0 2 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T5,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT1,T5,T15
11CoveredT1,T5,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT2,T21,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT4,T1,T5 VC_COV_UNR
1CoveredT2,T21,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT2,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT2,T21,T9
10CoveredT1,T5,T15
11CoveredT2,T21,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT2,T9,T11
01CoveredT106
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT2,T9,T11
01CoveredT2,T12,T120
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT2,T9,T11
1-CoveredT2,T12,T120

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T2,T21,T9
DetectSt 168 Covered T2,T9,T11
IdleSt 163 Covered T4,T1,T5
StableSt 191 Covered T2,T9,T11


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T2,T9,T11
DebounceSt->IdleSt 163 Covered T21,T129,T170
DetectSt->IdleSt 186 Covered T106
DetectSt->StableSt 191 Covered T2,T9,T11
IdleSt->DebounceSt 148 Covered T2,T21,T9
StableSt->IdleSt 206 Covered T2,T11,T12



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T2,T21,T9
0 1 Covered T2,T21,T9
0 0 Excluded T4,T1,T5 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T9,T11
0 Covered T4,T1,T5


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T2,T21,T9
IdleSt 0 - - - - - - Covered T1,T5,T15
DebounceSt - 1 - - - - - Covered T21,T63
DebounceSt - 0 1 1 - - - Covered T2,T9,T11
DebounceSt - 0 1 0 - - - Covered T129,T170,T176
DebounceSt - 0 0 - - - - Covered T2,T21,T9
DetectSt - - - - 1 - - Covered T106
DetectSt - - - - 0 1 - Covered T2,T9,T11
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T2,T12,T120
StableSt - - - - - - 0 Covered T2,T9,T11
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 6449837 156 0 0
CntIncr_A 6449837 59436 0 0
CntNoWrap_A 6449837 5829505 0 0
DetectStDropOut_A 6449837 1 0 0
DetectedOut_A 6449837 14955 0 0
DetectedPulseOut_A 6449837 74 0 0
DisabledIdleSt_A 6449837 5702094 0 0
DisabledNoDetection_A 6449837 5704315 0 0
EnterDebounceSt_A 6449837 81 0 0
EnterDetectSt_A 6449837 75 0 0
EnterStableSt_A 6449837 74 0 0
PulseIsPulse_A 6449837 74 0 0
StayInStableSt 6449837 14848 0 0
gen_high_level_sva.HighLevelEvent_A 6449837 5831944 0 0
gen_not_sticky_sva.StableStDropOut_A 6449837 41 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 156 0 0
T2 1117 6 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 2 0 0
T11 0 2 0 0
T12 0 4 0 0
T17 9843 0 0 0
T21 7102 1 0 0
T22 0 2 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 4 0 0
T34 0 6 0 0
T35 0 2 0 0
T45 494 0 0 0
T120 0 6 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 59436 0 0
T2 1117 240 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 45 0 0
T11 0 54635 0 0
T12 0 140 0 0
T17 9843 0 0 0
T21 7102 26 0 0
T22 0 38 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 73 0 0
T34 0 285 0 0
T35 0 30 0 0
T45 494 0 0 0
T120 0 186 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5829505 0 0
T1 36814 36318 0 0
T2 1117 710 0 0
T3 33204 32781 0 0
T4 402 1 0 0
T5 6265 5864 0 0
T13 630 229 0 0
T14 828 427 0 0
T15 29746 29322 0 0
T16 502 101 0 0
T17 9843 9435 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 1 0 0
T63 6617 0 0 0
T106 264586 1 0 0
T177 1022 0 0 0
T178 1817 0 0 0
T179 666 0 0 0
T180 522 0 0 0
T181 738 0 0 0
T182 418 0 0 0
T183 514 0 0 0
T184 640 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 14955 0 0
T2 1117 217 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 42 0 0
T11 0 9949 0 0
T12 0 80 0 0
T17 9843 0 0 0
T21 7102 0 0 0
T22 0 182 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 55 0 0
T34 0 98 0 0
T35 0 75 0 0
T38 0 224 0 0
T45 494 0 0 0
T120 0 235 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 74 0 0
T2 1117 3 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 1 0 0
T11 0 1 0 0
T12 0 2 0 0
T17 9843 0 0 0
T21 7102 0 0 0
T22 0 1 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 2 0 0
T34 0 3 0 0
T35 0 1 0 0
T38 0 2 0 0
T45 494 0 0 0
T120 0 3 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5702094 0 0
T1 36814 36318 0 0
T2 1117 3 0 0
T3 33204 32781 0 0
T4 402 1 0 0
T5 6265 5864 0 0
T13 630 229 0 0
T14 828 427 0 0
T15 29746 29322 0 0
T16 502 101 0 0
T17 9843 9435 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5704315 0 0
T1 36814 36332 0 0
T2 1117 3 0 0
T3 33204 32785 0 0
T4 402 2 0 0
T5 6265 5865 0 0
T13 630 230 0 0
T14 828 428 0 0
T15 29746 29326 0 0
T16 502 102 0 0
T17 9843 9437 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 81 0 0
T2 1117 3 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 1 0 0
T11 0 1 0 0
T12 0 2 0 0
T17 9843 0 0 0
T21 7102 1 0 0
T22 0 1 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 2 0 0
T34 0 3 0 0
T35 0 1 0 0
T45 494 0 0 0
T120 0 3 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 75 0 0
T2 1117 3 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 1 0 0
T11 0 1 0 0
T12 0 2 0 0
T17 9843 0 0 0
T21 7102 0 0 0
T22 0 1 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 2 0 0
T34 0 3 0 0
T35 0 1 0 0
T38 0 2 0 0
T45 494 0 0 0
T120 0 3 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 74 0 0
T2 1117 3 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 1 0 0
T11 0 1 0 0
T12 0 2 0 0
T17 9843 0 0 0
T21 7102 0 0 0
T22 0 1 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 2 0 0
T34 0 3 0 0
T35 0 1 0 0
T38 0 2 0 0
T45 494 0 0 0
T120 0 3 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 74 0 0
T2 1117 3 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 1 0 0
T11 0 1 0 0
T12 0 2 0 0
T17 9843 0 0 0
T21 7102 0 0 0
T22 0 1 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 2 0 0
T34 0 3 0 0
T35 0 1 0 0
T38 0 2 0 0
T45 494 0 0 0
T120 0 3 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 14848 0 0
T2 1117 213 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 40 0 0
T11 0 9947 0 0
T12 0 77 0 0
T17 9843 0 0 0
T21 7102 0 0 0
T22 0 180 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 53 0 0
T34 0 94 0 0
T35 0 73 0 0
T38 0 220 0 0
T45 494 0 0 0
T120 0 231 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5831944 0 0
T1 36814 36332 0 0
T2 1117 717 0 0
T3 33204 32785 0 0
T4 402 2 0 0
T5 6265 5865 0 0
T13 630 230 0 0
T14 828 428 0 0
T15 29746 29326 0 0
T16 502 102 0 0
T17 9843 9437 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 41 0 0
T2 1117 2 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T12 0 1 0 0
T17 9843 0 0 0
T21 7102 0 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 2 0 0
T34 0 2 0 0
T43 0 2 0 0
T45 494 0 0 0
T65 0 2 0 0
T120 0 2 0 0
T140 0 2 0 0
T143 0 1 0 0
T160 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T5,T15
1CoveredT4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T5,T15
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT21,T12,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT4,T1,T5 VC_COV_UNR
1CoveredT21,T12,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT12,T23,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT21,T9,T11
10CoveredT1,T5,T15
11CoveredT21,T12,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT12,T23,T32
01CoveredT142,T163
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT12,T23,T32
01CoveredT12,T23,T43
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT12,T23,T32
1-CoveredT12,T23,T43

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T21,T12,T23
DetectSt 168 Covered T12,T23,T32
IdleSt 163 Covered T4,T1,T5
StableSt 191 Covered T12,T23,T32


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T12,T23,T32
DebounceSt->IdleSt 163 Covered T21,T185,T63
DetectSt->IdleSt 186 Covered T142,T163
DetectSt->StableSt 191 Covered T12,T23,T32
IdleSt->DebounceSt 148 Covered T21,T12,T23
StableSt->IdleSt 206 Covered T12,T23,T43



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T21,T12,T23
0 1 Covered T21,T12,T23
0 0 Excluded T4,T1,T5 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T12,T23,T32
0 Covered T4,T1,T5


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T21,T12,T23
IdleSt 0 - - - - - - Covered T4,T1,T5
DebounceSt - 1 - - - - - Covered T21,T63
DebounceSt - 0 1 1 - - - Covered T12,T23,T32
DebounceSt - 0 1 0 - - - Covered T185
DebounceSt - 0 0 - - - - Covered T21,T12,T23
DetectSt - - - - 1 - - Covered T142,T163
DetectSt - - - - 0 1 - Covered T12,T23,T32
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T12,T23,T43
StableSt - - - - - - 0 Covered T12,T23,T32
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 6449837 69 0 0
CntIncr_A 6449837 18216 0 0
CntNoWrap_A 6449837 5829592 0 0
DetectStDropOut_A 6449837 2 0 0
DetectedOut_A 6449837 57268 0 0
DetectedPulseOut_A 6449837 31 0 0
DisabledIdleSt_A 6449837 5238401 0 0
DisabledNoDetection_A 6449837 5240626 0 0
EnterDebounceSt_A 6449837 36 0 0
EnterDetectSt_A 6449837 33 0 0
EnterStableSt_A 6449837 31 0 0
PulseIsPulse_A 6449837 31 0 0
StayInStableSt 6449837 57219 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 6449837 5800 0 0
gen_low_level_sva.LowLevelEvent_A 6449837 5831944 0 0
gen_not_sticky_sva.StableStDropOut_A 6449837 13 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 69 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T12 0 2 0 0
T21 7102 1 0 0
T23 0 2 0 0
T24 492 0 0 0
T25 493 0 0 0
T26 506 0 0 0
T28 769 0 0 0
T32 0 2 0 0
T43 0 4 0 0
T44 0 2 0 0
T45 494 0 0 0
T46 403 0 0 0
T47 429 0 0 0
T62 0 2 0 0
T129 0 2 0 0
T160 0 2 0 0
T174 0 4 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 18216 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T12 0 70 0 0
T21 7102 25 0 0
T23 0 87 0 0
T24 492 0 0 0
T25 493 0 0 0
T26 506 0 0 0
T28 769 0 0 0
T32 0 16201 0 0
T43 0 178 0 0
T44 0 86 0 0
T45 494 0 0 0
T46 403 0 0 0
T47 429 0 0 0
T62 0 44 0 0
T129 0 69 0 0
T160 0 75 0 0
T174 0 26 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5829592 0 0
T1 36814 36318 0 0
T2 1117 716 0 0
T3 33204 32781 0 0
T4 402 1 0 0
T5 6265 5864 0 0
T13 630 229 0 0
T14 828 427 0 0
T15 29746 29322 0 0
T16 502 101 0 0
T17 9843 9435 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 2 0 0
T71 47896 0 0 0
T122 823 0 0 0
T142 21657 1 0 0
T163 0 1 0 0
T175 7340 0 0 0
T186 37479 0 0 0
T187 492 0 0 0
T188 423 0 0 0
T189 4779 0 0 0
T190 526 0 0 0
T191 404 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 57268 0 0
T12 3688 129 0 0
T22 6357 0 0 0
T23 15192 43 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T32 0 53654 0 0
T35 515 0 0 0
T39 8559 0 0 0
T43 0 173 0 0
T44 0 554 0 0
T51 493 0 0 0
T62 0 11 0 0
T129 0 39 0 0
T138 427 0 0 0
T139 421 0 0 0
T160 0 43 0 0
T162 0 286 0 0
T174 0 82 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 31 0 0
T12 3688 1 0 0
T22 6357 0 0 0
T23 15192 1 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T32 0 1 0 0
T35 515 0 0 0
T39 8559 0 0 0
T43 0 2 0 0
T44 0 1 0 0
T51 493 0 0 0
T62 0 1 0 0
T129 0 1 0 0
T138 427 0 0 0
T139 421 0 0 0
T160 0 1 0 0
T162 0 2 0 0
T174 0 2 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5238401 0 0
T1 36814 36318 0 0
T2 1117 716 0 0
T3 33204 32781 0 0
T4 402 1 0 0
T5 6265 5864 0 0
T13 630 229 0 0
T14 828 427 0 0
T15 29746 29322 0 0
T16 502 101 0 0
T17 9843 9435 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5240626 0 0
T1 36814 36332 0 0
T2 1117 717 0 0
T3 33204 32785 0 0
T4 402 2 0 0
T5 6265 5865 0 0
T13 630 230 0 0
T14 828 428 0 0
T15 29746 29326 0 0
T16 502 102 0 0
T17 9843 9437 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 36 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T12 0 1 0 0
T21 7102 1 0 0
T23 0 1 0 0
T24 492 0 0 0
T25 493 0 0 0
T26 506 0 0 0
T28 769 0 0 0
T32 0 1 0 0
T43 0 2 0 0
T44 0 1 0 0
T45 494 0 0 0
T46 403 0 0 0
T47 429 0 0 0
T62 0 1 0 0
T129 0 1 0 0
T160 0 1 0 0
T174 0 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 33 0 0
T12 3688 1 0 0
T22 6357 0 0 0
T23 15192 1 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T32 0 1 0 0
T35 515 0 0 0
T39 8559 0 0 0
T43 0 2 0 0
T44 0 1 0 0
T51 493 0 0 0
T62 0 1 0 0
T129 0 1 0 0
T138 427 0 0 0
T139 421 0 0 0
T160 0 1 0 0
T162 0 2 0 0
T174 0 2 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 31 0 0
T12 3688 1 0 0
T22 6357 0 0 0
T23 15192 1 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T32 0 1 0 0
T35 515 0 0 0
T39 8559 0 0 0
T43 0 2 0 0
T44 0 1 0 0
T51 493 0 0 0
T62 0 1 0 0
T129 0 1 0 0
T138 427 0 0 0
T139 421 0 0 0
T160 0 1 0 0
T162 0 2 0 0
T174 0 2 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 31 0 0
T12 3688 1 0 0
T22 6357 0 0 0
T23 15192 1 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T32 0 1 0 0
T35 515 0 0 0
T39 8559 0 0 0
T43 0 2 0 0
T44 0 1 0 0
T51 493 0 0 0
T62 0 1 0 0
T129 0 1 0 0
T138 427 0 0 0
T139 421 0 0 0
T160 0 1 0 0
T162 0 2 0 0
T174 0 2 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 57219 0 0
T12 3688 128 0 0
T22 6357 0 0 0
T23 15192 42 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T32 0 53652 0 0
T35 515 0 0 0
T39 8559 0 0 0
T43 0 170 0 0
T44 0 552 0 0
T51 493 0 0 0
T62 0 10 0 0
T129 0 37 0 0
T138 427 0 0 0
T139 421 0 0 0
T160 0 41 0 0
T162 0 283 0 0
T174 0 79 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5800 0 0
T1 36814 27 0 0
T2 1117 2 0 0
T3 33204 34 0 0
T5 6265 24 0 0
T6 16495 29 0 0
T7 0 7 0 0
T13 630 0 0 0
T14 828 0 0 0
T15 29746 27 0 0
T16 502 7 0 0
T17 9843 27 0 0
T21 0 27 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5831944 0 0
T1 36814 36332 0 0
T2 1117 717 0 0
T3 33204 32785 0 0
T4 402 2 0 0
T5 6265 5865 0 0
T13 630 230 0 0
T14 828 428 0 0
T15 29746 29326 0 0
T16 502 102 0 0
T17 9843 9437 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 13 0 0
T12 3688 1 0 0
T22 6357 0 0 0
T23 15192 1 0 0
T30 2499 0 0 0
T31 27577 0 0 0
T35 515 0 0 0
T39 8559 0 0 0
T43 0 1 0 0
T51 493 0 0 0
T62 0 1 0 0
T122 0 1 0 0
T124 0 1 0 0
T128 0 1 0 0
T138 427 0 0 0
T139 421 0 0 0
T142 0 2 0 0
T162 0 1 0 0
T174 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T5,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT1,T5,T15
11CoveredT1,T5,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT2,T21,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT4,T1,T5 VC_COV_UNR
1CoveredT2,T21,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT2,T9,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT2,T21,T9
10CoveredT1,T5,T15
11CoveredT2,T21,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT2,T9,T35
01CoveredT23,T155,T173
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT2,T9,T35
01CoveredT2,T9,T35
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT2,T9,T35
1-CoveredT2,T9,T35

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T2,T21,T9
DetectSt 168 Covered T2,T9,T35
IdleSt 163 Covered T4,T1,T5
StableSt 191 Covered T2,T9,T35


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T2,T9,T35
DebounceSt->IdleSt 163 Covered T21,T22,T23
DetectSt->IdleSt 186 Covered T23,T155,T173
DetectSt->StableSt 191 Covered T2,T9,T35
IdleSt->DebounceSt 148 Covered T2,T21,T9
StableSt->IdleSt 206 Covered T2,T9,T35



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T2,T21,T9
0 1 Covered T2,T21,T9
0 0 Excluded T4,T1,T5 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T9,T35
0 Covered T4,T1,T5


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T2,T21,T9
IdleSt 0 - - - - - - Covered T1,T5,T15
DebounceSt - 1 - - - - - Covered T21,T63
DebounceSt - 0 1 1 - - - Covered T2,T9,T35
DebounceSt - 0 1 0 - - - Covered T23,T144,T192
DebounceSt - 0 0 - - - - Covered T2,T21,T9
DetectSt - - - - 1 - - Covered T23,T155,T173
DetectSt - - - - 0 1 - Covered T2,T9,T35
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T2,T9,T35
StableSt - - - - - - 0 Covered T2,T9,T35
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 6449837 141 0 0
CntIncr_A 6449837 81005 0 0
CntNoWrap_A 6449837 5829520 0 0
DetectStDropOut_A 6449837 3 0 0
DetectedOut_A 6449837 13229 0 0
DetectedPulseOut_A 6449837 64 0 0
DisabledIdleSt_A 6449837 5329769 0 0
DisabledNoDetection_A 6449837 5331991 0 0
EnterDebounceSt_A 6449837 75 0 0
EnterDetectSt_A 6449837 67 0 0
EnterStableSt_A 6449837 64 0 0
PulseIsPulse_A 6449837 64 0 0
StayInStableSt 6449837 13136 0 0
gen_high_level_sva.HighLevelEvent_A 6449837 5831944 0 0
gen_not_sticky_sva.StableStDropOut_A 6449837 35 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 141 0 0
T2 1117 2 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 2 0 0
T17 9843 0 0 0
T21 7102 1 0 0
T23 0 4 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 2 0 0
T34 0 4 0 0
T35 0 2 0 0
T36 0 2 0 0
T38 0 4 0 0
T45 494 0 0 0
T120 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 81005 0 0
T2 1117 80 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 45 0 0
T17 9843 0 0 0
T21 7102 26 0 0
T22 0 25 0 0
T23 0 187 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 42 0 0
T34 0 190 0 0
T35 0 30 0 0
T36 0 27 0 0
T45 494 0 0 0
T120 0 62 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5829520 0 0
T1 36814 36318 0 0
T2 1117 714 0 0
T3 33204 32781 0 0
T4 402 1 0 0
T5 6265 5864 0 0
T13 630 229 0 0
T14 828 427 0 0
T15 29746 29322 0 0
T16 502 101 0 0
T17 9843 9435 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 3 0 0
T23 15192 1 0 0
T30 2499 0 0 0
T36 534 0 0 0
T37 501 0 0 0
T52 504 0 0 0
T53 504 0 0 0
T54 526 0 0 0
T98 406 0 0 0
T99 411 0 0 0
T103 433 0 0 0
T155 0 1 0 0
T173 0 1 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 13229 0 0
T2 1117 172 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 5 0 0
T17 9843 0 0 0
T21 7102 0 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 98 0 0
T34 0 395 0 0
T35 0 3 0 0
T36 0 27 0 0
T38 0 241 0 0
T43 0 259 0 0
T45 494 0 0 0
T120 0 355 0 0
T156 0 87 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 64 0 0
T2 1117 1 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 1 0 0
T17 9843 0 0 0
T21 7102 0 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 1 0 0
T34 0 2 0 0
T35 0 1 0 0
T36 0 1 0 0
T38 0 2 0 0
T43 0 1 0 0
T45 494 0 0 0
T120 0 1 0 0
T156 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5329769 0 0
T1 36814 36318 0 0
T2 1117 3 0 0
T3 33204 32781 0 0
T4 402 1 0 0
T5 6265 5864 0 0
T13 630 229 0 0
T14 828 427 0 0
T15 29746 29322 0 0
T16 502 101 0 0
T17 9843 9435 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5331991 0 0
T1 36814 36332 0 0
T2 1117 3 0 0
T3 33204 32785 0 0
T4 402 2 0 0
T5 6265 5865 0 0
T13 630 230 0 0
T14 828 428 0 0
T15 29746 29326 0 0
T16 502 102 0 0
T17 9843 9437 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 75 0 0
T2 1117 1 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 1 0 0
T17 9843 0 0 0
T21 7102 1 0 0
T22 0 1 0 0
T23 0 3 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 1 0 0
T34 0 2 0 0
T35 0 1 0 0
T36 0 1 0 0
T45 494 0 0 0
T120 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 67 0 0
T2 1117 1 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 1 0 0
T17 9843 0 0 0
T21 7102 0 0 0
T23 0 1 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 1 0 0
T34 0 2 0 0
T35 0 1 0 0
T36 0 1 0 0
T38 0 2 0 0
T43 0 1 0 0
T45 494 0 0 0
T120 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 64 0 0
T2 1117 1 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 1 0 0
T17 9843 0 0 0
T21 7102 0 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 1 0 0
T34 0 2 0 0
T35 0 1 0 0
T36 0 1 0 0
T38 0 2 0 0
T43 0 1 0 0
T45 494 0 0 0
T120 0 1 0 0
T156 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 64 0 0
T2 1117 1 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 1 0 0
T17 9843 0 0 0
T21 7102 0 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 1 0 0
T34 0 2 0 0
T35 0 1 0 0
T36 0 1 0 0
T38 0 2 0 0
T43 0 1 0 0
T45 494 0 0 0
T120 0 1 0 0
T156 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 13136 0 0
T2 1117 171 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 4 0 0
T17 9843 0 0 0
T21 7102 0 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 97 0 0
T34 0 392 0 0
T35 0 2 0 0
T36 0 26 0 0
T38 0 238 0 0
T43 0 257 0 0
T45 494 0 0 0
T120 0 354 0 0
T156 0 85 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5831944 0 0
T1 36814 36332 0 0
T2 1117 717 0 0
T3 33204 32785 0 0
T4 402 2 0 0
T5 6265 5865 0 0
T13 630 230 0 0
T14 828 428 0 0
T15 29746 29326 0 0
T16 502 102 0 0
T17 9843 9437 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 35 0 0
T2 1117 1 0 0
T3 33204 0 0 0
T6 16495 0 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 1 0 0
T17 9843 0 0 0
T21 7102 0 0 0
T24 492 0 0 0
T25 493 0 0 0
T33 0 1 0 0
T34 0 1 0 0
T35 0 1 0 0
T36 0 1 0 0
T38 0 1 0 0
T45 494 0 0 0
T120 0 1 0 0
T141 0 1 0 0
T143 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464393.48
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125322990.62
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211885.71
Logical211885.71
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T5,T15
1CoveredT4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T5,T15
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT21,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT4,T1,T5 VC_COV_UNR
1CoveredT21,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT9,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT21,T9,T11
10CoveredT1,T5,T15
11CoveredT21,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT9,T11,T12
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT9,T11,T12
01CoveredT23,T43,T141
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT9,T11,T12
1-CoveredT23,T43,T141

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T21,T9,T11
DetectSt 168 Covered T9,T11,T12
IdleSt 163 Covered T4,T1,T5
StableSt 191 Covered T9,T11,T12


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T9,T11,T12
DebounceSt->IdleSt 163 Covered T21,T63
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T9,T11,T12
IdleSt->DebounceSt 148 Covered T21,T9,T11
StableSt->IdleSt 206 Covered T12,T23,T33



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T21,T9,T11
0 1 Covered T21,T9,T11
0 0 Excluded T4,T1,T5 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T9,T11,T12
0 Covered T4,T1,T5


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T21,T9,T11
IdleSt 0 - - - - - - Covered T4,T1,T5
DebounceSt - 1 - - - - - Covered T21,T63
DebounceSt - 0 1 1 - - - Covered T9,T11,T12
DebounceSt - 0 1 0 - - - Not Covered
DebounceSt - 0 0 - - - - Covered T21,T9,T11
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T9,T11,T12
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T23,T43,T141
StableSt - - - - - - 0 Covered T9,T11,T12
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 6449837 88 0 0
CntIncr_A 6449837 57234 0 0
CntNoWrap_A 6449837 5829573 0 0
DetectStDropOut_A 6449837 0 0 0
DetectedOut_A 6449837 3027 0 0
DetectedPulseOut_A 6449837 43 0 0
DisabledIdleSt_A 6449837 5171438 0 0
DisabledNoDetection_A 6449837 5173657 0 0
EnterDebounceSt_A 6449837 45 0 0
EnterDetectSt_A 6449837 43 0 0
EnterStableSt_A 6449837 43 0 0
PulseIsPulse_A 6449837 43 0 0
StayInStableSt 6449837 2957 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 6449837 6521 0 0
gen_low_level_sva.LowLevelEvent_A 6449837 5831944 0 0
gen_not_sticky_sva.StableStDropOut_A 6449837 16 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 88 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 2 0 0
T11 0 2 0 0
T12 0 2 0 0
T21 7102 1 0 0
T23 0 4 0 0
T24 492 0 0 0
T25 493 0 0 0
T26 506 0 0 0
T28 769 0 0 0
T33 0 2 0 0
T35 0 2 0 0
T36 0 2 0 0
T43 0 2 0 0
T45 494 0 0 0
T46 403 0 0 0
T47 429 0 0 0
T120 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 57234 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 45 0 0
T11 0 19 0 0
T12 0 70 0 0
T21 7102 26 0 0
T23 0 100 0 0
T24 492 0 0 0
T25 493 0 0 0
T26 506 0 0 0
T28 769 0 0 0
T33 0 42 0 0
T35 0 30 0 0
T36 0 27 0 0
T43 0 93 0 0
T45 494 0 0 0
T46 403 0 0 0
T47 429 0 0 0
T120 0 62 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5829573 0 0
T1 36814 36318 0 0
T2 1117 716 0 0
T3 33204 32781 0 0
T4 402 1 0 0
T5 6265 5864 0 0
T13 630 229 0 0
T14 828 427 0 0
T15 29746 29322 0 0
T16 502 101 0 0
T17 9843 9435 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 3027 0 0
T9 547 42 0 0
T10 21225 0 0 0
T11 66940 63 0 0
T12 3688 461 0 0
T23 0 87 0 0
T31 27577 0 0 0
T33 0 84 0 0
T35 515 41 0 0
T36 0 43 0 0
T39 8559 0 0 0
T43 0 134 0 0
T44 0 43 0 0
T57 409 0 0 0
T120 0 104 0 0
T138 427 0 0 0
T139 421 0 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 43 0 0
T9 547 1 0 0
T10 21225 0 0 0
T11 66940 1 0 0
T12 3688 1 0 0
T23 0 2 0 0
T31 27577 0 0 0
T33 0 1 0 0
T35 515 1 0 0
T36 0 1 0 0
T39 8559 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T57 409 0 0 0
T120 0 1 0 0
T138 427 0 0 0
T139 421 0 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5171438 0 0
T1 36814 36318 0 0
T2 1117 716 0 0
T3 33204 32781 0 0
T4 402 1 0 0
T5 6265 5864 0 0
T13 630 229 0 0
T14 828 427 0 0
T15 29746 29322 0 0
T16 502 101 0 0
T17 9843 9435 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5173657 0 0
T1 36814 36332 0 0
T2 1117 717 0 0
T3 33204 32785 0 0
T4 402 2 0 0
T5 6265 5865 0 0
T13 630 230 0 0
T14 828 428 0 0
T15 29746 29326 0 0
T16 502 102 0 0
T17 9843 9437 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 45 0 0
T7 22466 0 0 0
T8 37851 0 0 0
T9 0 1 0 0
T11 0 1 0 0
T12 0 1 0 0
T21 7102 1 0 0
T23 0 2 0 0
T24 492 0 0 0
T25 493 0 0 0
T26 506 0 0 0
T28 769 0 0 0
T33 0 1 0 0
T35 0 1 0 0
T36 0 1 0 0
T43 0 1 0 0
T45 494 0 0 0
T46 403 0 0 0
T47 429 0 0 0
T120 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 43 0 0
T9 547 1 0 0
T10 21225 0 0 0
T11 66940 1 0 0
T12 3688 1 0 0
T23 0 2 0 0
T31 27577 0 0 0
T33 0 1 0 0
T35 515 1 0 0
T36 0 1 0 0
T39 8559 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T57 409 0 0 0
T120 0 1 0 0
T138 427 0 0 0
T139 421 0 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 43 0 0
T9 547 1 0 0
T10 21225 0 0 0
T11 66940 1 0 0
T12 3688 1 0 0
T23 0 2 0 0
T31 27577 0 0 0
T33 0 1 0 0
T35 515 1 0 0
T36 0 1 0 0
T39 8559 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T57 409 0 0 0
T120 0 1 0 0
T138 427 0 0 0
T139 421 0 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 43 0 0
T9 547 1 0 0
T10 21225 0 0 0
T11 66940 1 0 0
T12 3688 1 0 0
T23 0 2 0 0
T31 27577 0 0 0
T33 0 1 0 0
T35 515 1 0 0
T36 0 1 0 0
T39 8559 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T57 409 0 0 0
T120 0 1 0 0
T138 427 0 0 0
T139 421 0 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 2957 0 0
T9 547 40 0 0
T10 21225 0 0 0
T11 66940 61 0 0
T12 3688 459 0 0
T23 0 84 0 0
T31 27577 0 0 0
T33 0 82 0 0
T35 515 39 0 0
T36 0 41 0 0
T39 8559 0 0 0
T43 0 133 0 0
T44 0 41 0 0
T57 409 0 0 0
T120 0 102 0 0
T138 427 0 0 0
T139 421 0 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 6521 0 0
T1 36814 23 0 0
T2 1117 1 0 0
T3 33204 29 0 0
T5 6265 27 0 0
T6 16495 30 0 0
T7 0 12 0 0
T13 630 0 0 0
T14 828 0 0 0
T15 29746 29 0 0
T16 502 5 0 0
T17 9843 26 0 0
T21 0 25 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 5831944 0 0
T1 36814 36332 0 0
T2 1117 717 0 0
T3 33204 32785 0 0
T4 402 2 0 0
T5 6265 5865 0 0
T13 630 230 0 0
T14 828 428 0 0
T15 29746 29326 0 0
T16 502 102 0 0
T17 9843 9437 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6449837 16 0 0
T23 15192 1 0 0
T30 2499 0 0 0
T36 534 0 0 0
T37 501 0 0 0
T43 0 1 0 0
T52 504 0 0 0
T53 504 0 0 0
T54 526 0 0 0
T98 406 0 0 0
T99 411 0 0 0
T103 433 0 0 0
T124 0 1 0 0
T141 0 1 0 0
T143 0 1 0 0
T146 0 1 0 0
T162 0 2 0 0
T170 0 1 0 0
T175 0 1 0 0
T185 0 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%