Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T5,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T15
0	1	Covered	T17,T3,T21
1	0	Covered	T17,T3,T21

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T15
0	1	Covered	T1,T5,T15
1	0	Covered	T67,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T15
1	-	Covered	T1,T5,T15

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T15
DetectSt	168	Covered	T1,T5,T15
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T5,T15

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T15
DebounceSt->IdleSt	163	Covered	T21,T75,T193
DetectSt->IdleSt	186	Covered	T17,T3,T21
DetectSt->StableSt	191	Covered	T1,T5,T15
IdleSt->DebounceSt	148	Covered	T1,T5,T15
StableSt->IdleSt	206	Covered	T1,T5,T15

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T15
0	1	Covered	T1,T5,T15
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T15
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T15
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T75,T193
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T15
DetectSt	-	-	-	-	1	-	-	Covered	T17,T3,T21
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T15
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T15
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T15
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T15
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	2856	0	0
CntIncr_A	6449837	138865	0	0
CntNoWrap_A	6449837	5826805	0	0
DetectStDropOut_A	6449837	343	0	0
DetectedOut_A	6449837	86932	0	0
DetectedPulseOut_A	6449837	776	0	0
DisabledIdleSt_A	6449837	5316500	0	0
DisabledNoDetection_A	6449837	5318613	0	0
EnterDebounceSt_A	6449837	1448	0	0
EnterDetectSt_A	6449837	1409	0	0
EnterStableSt_A	6449837	776	0	0
PulseIsPulse_A	6449837	776	0	0
StayInStableSt	6449837	86073	0	0
gen_high_event_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_high_level_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	687	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	2856	0	0
T1	36814	42	0	0
T2	1117	0	0	0
T3	33204	48	0	0
T5	6265	42	0	0
T6	16495	30	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	58	0	0
T16	502	0	0	0
T17	9843	24	0	0
T21	0	16	0	0
T31	0	28	0	0
T39	0	8	0	0
T58	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	138865	0	0
T1	36814	1449	0	0
T2	1117	0	0	0
T3	33204	9666	0	0
T5	6265	798	0	0
T6	16495	945	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	8961	0	0
T16	502	0	0	0
T17	9843	931	0	0
T21	0	561	0	0
T31	0	392	0	0
T39	0	346	0	0
T58	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5826805	0	0
T1	36814	36276	0	0
T2	1117	716	0	0
T3	33204	32733	0	0
T4	402	1	0	0
T5	6265	5822	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29264	0	0
T16	502	101	0	0
T17	9843	9411	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	343	0	0
T3	33204	6	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T17	9843	1	0	0
T21	7102	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T45	494	0	0	0
T46	403	0	0	0
T59	0	9	0	0
T66	0	12	0	0
T74	0	12	0	0
T75	0	20	0	0
T76	0	9	0	0
T77	0	9	0	0
T194	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	86932	0	0
T1	36814	2212	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	463	0	0
T6	16495	1394	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	5265	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	325	0	0
T31	0	1663	0	0
T58	0	32	0	0
T88	0	80	0	0
T92	0	2594	0	0
T195	0	1430	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	776	0	0
T1	36814	21	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	21	0	0
T6	16495	15	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	29	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	5	0	0
T31	0	14	0	0
T58	0	1	0	0
T88	0	1	0	0
T92	0	33	0	0
T195	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5316500	0	0
T1	36814	29704	0	0
T2	1117	716	0	0
T3	33204	12460	0	0
T4	402	1	0	0
T5	6265	2729	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	8058	0	0
T16	502	101	0	0
T17	9843	5369	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5318613	0	0
T1	36814	29711	0	0
T2	1117	717	0	0
T3	33204	12463	0	0
T4	402	2	0	0
T5	6265	2729	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	8058	0	0
T16	502	102	0	0
T17	9843	5370	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	1448	0	0
T1	36814	21	0	0
T2	1117	0	0	0
T3	33204	24	0	0
T5	6265	21	0	0
T6	16495	15	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	29	0	0
T16	502	0	0	0
T17	9843	12	0	0
T21	0	9	0	0
T31	0	14	0	0
T39	0	4	0	0
T58	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	1409	0	0
T1	36814	21	0	0
T2	1117	0	0	0
T3	33204	24	0	0
T5	6265	21	0	0
T6	16495	15	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	29	0	0
T16	502	0	0	0
T17	9843	12	0	0
T21	0	7	0	0
T31	0	14	0	0
T39	0	4	0	0
T58	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	776	0	0
T1	36814	21	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	21	0	0
T6	16495	15	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	29	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	5	0	0
T31	0	14	0	0
T58	0	1	0	0
T88	0	1	0	0
T92	0	33	0	0
T195	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	776	0	0
T1	36814	21	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	21	0	0
T6	16495	15	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	29	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	5	0	0
T31	0	14	0	0
T58	0	1	0	0
T88	0	1	0	0
T92	0	33	0	0
T195	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	86073	0	0
T1	36814	2185	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	442	0	0
T6	16495	1377	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	5233	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	320	0	0
T31	0	1642	0	0
T58	0	30	0	0
T88	0	78	0	0
T92	0	2557	0	0
T195	0	1418	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	687	0	0
T1	36814	15	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	21	0	0
T6	16495	13	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	26	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	5	0	0
T31	0	7	0	0
T92	0	29	0	0
T149	0	27	0	0
T195	0	10	0	0
T196	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T15,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T15,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T15,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T15,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T6
0	1	Covered	T8,T23,T78
1	0	Covered	T21,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T6
0	1	Covered	T1,T6,T7
1	0	Covered	T21,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T15,T6
1	-	Covered	T1,T6,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T6
DetectSt	168	Covered	T1,T15,T6
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T15,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T15,T6
DebounceSt->IdleSt	163	Covered	T15,T21,T10
DetectSt->IdleSt	186	Covered	T21,T8,T23
DetectSt->StableSt	191	Covered	T1,T15,T6
IdleSt->DebounceSt	148	Covered	T1,T15,T6
StableSt->IdleSt	206	Covered	T1,T15,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T15,T6
0	1	Covered	T1,T15,T6
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T15,T6
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T15,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T10,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T6
DetectSt	-	-	-	-	1	-	-	Covered	T21,T8,T23
DetectSt	-	-	-	-	0	1	-	Covered	T1,T15,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T15,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T21
StableSt	-	-	-	-	-	-	0	Covered	T1,T15,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	737	0	0
CntIncr_A	6449837	36080	0	0
CntNoWrap_A	6449837	5828924	0	0
DetectStDropOut_A	6449837	55	0	0
DetectedOut_A	6449837	11607	0	0
DetectedPulseOut_A	6449837	284	0	0
DisabledIdleSt_A	6449837	5476135	0	0
DisabledNoDetection_A	6449837	5477711	0	0
EnterDebounceSt_A	6449837	397	0	0
EnterDetectSt_A	6449837	343	0	0
EnterStableSt_A	6449837	284	0	0
PulseIsPulse_A	6449837	284	0	0
StayInStableSt	6449837	11301	0	0
gen_high_level_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	258	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	737	0	0
T1	36814	10	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	0	0	0
T6	16495	6	0	0
T7	0	4	0	0
T8	0	2	0	0
T10	0	7	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	7	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	8	0	0
T23	0	2	0	0
T31	0	12	0	0
T40	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	36080	0	0
T1	36814	315	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	0	0	0
T6	16495	231	0	0
T7	0	262	0	0
T8	0	80	0	0
T10	0	576	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	1281	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	191	0	0
T23	0	52	0	0
T31	0	198	0	0
T40	0	304	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5828924	0	0
T1	36814	36308	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29315	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	55	0	0
T8	37851	1	0	0
T9	547	0	0	0
T23	0	1	0	0
T26	506	0	0	0
T27	504	0	0	0
T28	769	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T48	421	0	0	0
T55	423	0	0	0
T56	820	0	0	0
T78	0	9	0	0
T79	0	6	0	0
T80	0	1	0	0
T81	0	4	0	0
T82	0	2	0	0
T83	0	7	0	0
T84	0	9	0	0
T85	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	11607	0	0
T1	36814	346	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	0	0	0
T6	16495	221	0	0
T7	0	54	0	0
T10	0	14	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	95	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	68	0	0
T31	0	427	0	0
T40	0	25	0	0
T88	0	3	0	0
T89	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	284	0	0
T1	36814	5	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	0	0	0
T6	16495	3	0	0
T7	0	2	0	0
T10	0	3	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	3	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	1	0	0
T31	0	6	0	0
T40	0	2	0	0
T88	0	1	0	0
T89	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5476135	0	0
T1	36814	34112	0	0
T2	1117	716	0	0
T3	33204	32781	0	0
T4	402	1	0	0
T5	6265	5401	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	24060	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5477711	0	0
T1	36814	34120	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5402	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	24061	0	0
T16	502	102	0	0
T17	9843	9437	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	397	0	0
T1	36814	5	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	0	0	0
T6	16495	3	0	0
T7	0	2	0	0
T8	0	1	0	0
T10	0	4	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	4	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	5	0	0
T23	0	1	0	0
T31	0	6	0	0
T40	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	343	0	0
T1	36814	5	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	0	0	0
T6	16495	3	0	0
T7	0	2	0	0
T8	0	1	0	0
T10	0	3	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	3	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	3	0	0
T23	0	1	0	0
T31	0	6	0	0
T40	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	284	0	0
T1	36814	5	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	0	0	0
T6	16495	3	0	0
T7	0	2	0	0
T10	0	3	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	3	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	1	0	0
T31	0	6	0	0
T40	0	2	0	0
T88	0	1	0	0
T89	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	284	0	0
T1	36814	5	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	0	0	0
T6	16495	3	0	0
T7	0	2	0	0
T10	0	3	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	3	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	1	0	0
T31	0	6	0	0
T40	0	2	0	0
T88	0	1	0	0
T89	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	11301	0	0
T1	36814	341	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	0	0	0
T6	16495	218	0	0
T7	0	52	0	0
T10	0	11	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	89	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	67	0	0
T31	0	421	0	0
T40	0	23	0	0
T88	0	2	0	0
T89	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	258	0	0
T1	36814	5	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T5	6265	0	0	0
T6	16495	3	0	0
T7	0	2	0	0
T10	0	3	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T31	0	6	0	0
T40	0	2	0	0
T88	0	1	0	0
T89	0	3	0	0
T92	0	4	0	0
T93	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T5,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T15
0	1	Covered	T15,T21,T74
1	0	Covered	T15,T21,T196

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T17
0	1	Covered	T1,T5,T17
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T17
1	-	Covered	T1,T5,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T15
DetectSt	168	Covered	T1,T5,T15
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T5,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T15
DebounceSt->IdleSt	163	Covered	T21,T75,T193
DetectSt->IdleSt	186	Covered	T15,T21,T74
DetectSt->StableSt	191	Covered	T1,T5,T17
IdleSt->DebounceSt	148	Covered	T1,T5,T15
StableSt->IdleSt	206	Covered	T1,T5,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T15
0	1	Covered	T1,T5,T15
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T15
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T15
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T75,T193
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T15
DetectSt	-	-	-	-	1	-	-	Covered	T15,T21,T74
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T17
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T15
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T17
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T17
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	2873	0	0
CntIncr_A	6449837	114973	0	0
CntNoWrap_A	6449837	5826788	0	0
DetectStDropOut_A	6449837	277	0	0
DetectedOut_A	6449837	96464	0	0
DetectedPulseOut_A	6449837	1002	0	0
DisabledIdleSt_A	6449837	5305304	0	0
DisabledNoDetection_A	6449837	5307410	0	0
EnterDebounceSt_A	6449837	1452	0	0
EnterDetectSt_A	6449837	1422	0	0
EnterStableSt_A	6449837	1002	0	0
PulseIsPulse_A	6449837	1002	0	0
StayInStableSt	6449837	95373	0	0
gen_high_event_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_high_level_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	913	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	2873	0	0
T1	36814	22	0	0
T2	1117	0	0	0
T3	33204	26	0	0
T5	6265	48	0	0
T6	16495	50	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	20	0	0
T16	502	0	0	0
T17	9843	18	0	0
T21	0	16	0	0
T31	0	26	0	0
T39	0	40	0	0
T59	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	114973	0	0
T1	36814	891	0	0
T2	1117	0	0	0
T3	33204	3536	0	0
T5	6265	1200	0	0
T6	16495	1300	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	3255	0	0
T16	502	0	0	0
T17	9843	585	0	0
T21	0	561	0	0
T31	0	468	0	0
T39	0	1240	0	0
T59	0	732	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5826788	0	0
T1	36814	36296	0	0
T2	1117	716	0	0
T3	33204	32755	0	0
T4	402	1	0	0
T5	6265	5816	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29302	0	0
T16	502	101	0	0
T17	9843	9417	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	277	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T6	16495	0	0	0
T7	22466	0	0	0
T15	29746	1	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	7102	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T74	0	22	0	0
T75	0	8	0	0
T76	0	29	0	0
T193	0	10	0	0
T196	0	7	0	0
T197	0	6	0	0
T198	0	5	0	0
T199	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	96464	0	0
T1	36814	429	0	0
T2	1117	0	0	0
T3	33204	3399	0	0
T5	6265	903	0	0
T6	16495	2065	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	132	0	0
T21	0	314	0	0
T31	0	1191	0	0
T39	0	544	0	0
T59	0	2015	0	0
T92	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	1002	0	0
T1	36814	11	0	0
T2	1117	0	0	0
T3	33204	13	0	0
T5	6265	24	0	0
T6	16495	25	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	9	0	0
T21	0	5	0	0
T31	0	13	0	0
T39	0	20	0	0
T59	0	12	0	0
T92	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5305304	0	0
T1	36814	31113	0	0
T2	1117	716	0	0
T3	33204	10741	0	0
T4	402	1	0	0
T5	6265	2062	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	12862	0	0
T16	502	101	0	0
T17	9843	5342	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5307410	0	0
T1	36814	31124	0	0
T2	1117	717	0	0
T3	33204	10744	0	0
T4	402	2	0	0
T5	6265	2062	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	12865	0	0
T16	502	102	0	0
T17	9843	5343	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	1452	0	0
T1	36814	11	0	0
T2	1117	0	0	0
T3	33204	13	0	0
T5	6265	24	0	0
T6	16495	25	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	10	0	0
T16	502	0	0	0
T17	9843	9	0	0
T21	0	9	0	0
T31	0	13	0	0
T39	0	20	0	0
T59	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	1422	0	0
T1	36814	11	0	0
T2	1117	0	0	0
T3	33204	13	0	0
T5	6265	24	0	0
T6	16495	25	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	10	0	0
T16	502	0	0	0
T17	9843	9	0	0
T21	0	7	0	0
T31	0	13	0	0
T39	0	20	0	0
T59	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	1002	0	0
T1	36814	11	0	0
T2	1117	0	0	0
T3	33204	13	0	0
T5	6265	24	0	0
T6	16495	25	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	9	0	0
T21	0	5	0	0
T31	0	13	0	0
T39	0	20	0	0
T59	0	12	0	0
T92	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	1002	0	0
T1	36814	11	0	0
T2	1117	0	0	0
T3	33204	13	0	0
T5	6265	24	0	0
T6	16495	25	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	9	0	0
T21	0	5	0	0
T31	0	13	0	0
T39	0	20	0	0
T59	0	12	0	0
T92	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	95373	0	0
T1	36814	416	0	0
T2	1117	0	0	0
T3	33204	3386	0	0
T5	6265	879	0	0
T6	16495	2037	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	123	0	0
T21	0	309	0	0
T31	0	1174	0	0
T39	0	524	0	0
T59	0	1996	0	0
T92	0	70	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	913	0	0
T1	36814	9	0	0
T2	1117	0	0	0
T3	33204	13	0	0
T5	6265	24	0	0
T6	16495	22	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	9	0	0
T21	0	5	0	0
T31	0	9	0	0
T39	0	20	0	0
T59	0	5	0	0
T92	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T5,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T5,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T3
0	1	Covered	T23,T200,T201
1	0	Covered	T21,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T3
0	1	Covered	T5,T3,T6
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T3
1	-	Covered	T5,T3,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T3
DetectSt	168	Covered	T1,T5,T3
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T5,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T3
DebounceSt->IdleSt	163	Covered	T21,T33,T89
DetectSt->IdleSt	186	Covered	T21,T23,T200
DetectSt->StableSt	191	Covered	T1,T5,T3
IdleSt->DebounceSt	148	Covered	T1,T5,T3
StableSt->IdleSt	206	Covered	T1,T5,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T5,T3
0	1	Covered	T1,T5,T3
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T3
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T89,T61,T202
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T3
DetectSt	-	-	-	-	1	-	-	Covered	T21,T23,T200
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T3
StableSt	-	-	-	-	-	-	1	Covered	T5,T3,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	899	0	0
CntIncr_A	6449837	47155	0	0
CntNoWrap_A	6449837	5828762	0	0
DetectStDropOut_A	6449837	43	0	0
DetectedOut_A	6449837	16810	0	0
DetectedPulseOut_A	6449837	377	0	0
DisabledIdleSt_A	6449837	5448785	0	0
DisabledNoDetection_A	6449837	5450372	0	0
EnterDebounceSt_A	6449837	476	0	0
EnterDetectSt_A	6449837	425	0	0
EnterStableSt_A	6449837	377	0	0
PulseIsPulse_A	6449837	377	0	0
StayInStableSt	6449837	16399	0	0
gen_high_level_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	342	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	899	0	0
T1	36814	4	0	0
T2	1117	0	0	0
T3	33204	6	0	0
T5	6265	10	0	0
T6	16495	4	0	0
T7	0	6	0	0
T8	0	22	0	0
T10	0	8	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	8	0	0
T23	0	6	0	0
T31	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	47155	0	0
T1	36814	144	0	0
T2	1117	0	0	0
T3	33204	732	0	0
T5	6265	170	0	0
T6	16495	150	0	0
T7	0	390	0	0
T8	0	671	0	0
T10	0	364	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	172	0	0
T23	0	158	0	0
T31	0	208	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5828762	0	0
T1	36814	36314	0	0
T2	1117	716	0	0
T3	33204	32775	0	0
T4	402	1	0	0
T5	6265	5854	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	43	0	0
T23	15192	3	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T98	406	0	0	0
T99	411	0	0	0
T103	433	0	0	0
T200	0	4	0	0
T201	0	3	0	0
T203	0	3	0	0
T204	0	11	0	0
T205	0	4	0	0
T206	0	4	0	0
T207	0	1	0	0
T208	0	8	0	0
T209	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	16810	0	0
T1	36814	116	0	0
T2	1117	0	0	0
T3	33204	246	0	0
T5	6265	145	0	0
T6	16495	150	0	0
T7	0	84	0	0
T8	0	212	0	0
T10	0	313	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	67	0	0
T31	0	209	0	0
T59	0	415	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	377	0	0
T1	36814	2	0	0
T2	1117	0	0	0
T3	33204	3	0	0
T5	6265	5	0	0
T6	16495	2	0	0
T7	0	3	0	0
T8	0	11	0	0
T10	0	4	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	1	0	0
T31	0	4	0	0
T59	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5448785	0	0
T1	36814	35891	0	0
T2	1117	716	0	0
T3	33204	29382	0	0
T4	402	1	0	0
T5	6265	4961	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9303	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5450372	0	0
T1	36814	35903	0	0
T2	1117	717	0	0
T3	33204	29386	0	0
T4	402	2	0	0
T5	6265	4962	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9305	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	476	0	0
T1	36814	2	0	0
T2	1117	0	0	0
T3	33204	3	0	0
T5	6265	5	0	0
T6	16495	2	0	0
T7	0	3	0	0
T8	0	11	0	0
T10	0	4	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	5	0	0
T23	0	3	0	0
T31	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	425	0	0
T1	36814	2	0	0
T2	1117	0	0	0
T3	33204	3	0	0
T5	6265	5	0	0
T6	16495	2	0	0
T7	0	3	0	0
T8	0	11	0	0
T10	0	4	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	3	0	0
T23	0	3	0	0
T31	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	377	0	0
T1	36814	2	0	0
T2	1117	0	0	0
T3	33204	3	0	0
T5	6265	5	0	0
T6	16495	2	0	0
T7	0	3	0	0
T8	0	11	0	0
T10	0	4	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	1	0	0
T31	0	4	0	0
T59	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	377	0	0
T1	36814	2	0	0
T2	1117	0	0	0
T3	33204	3	0	0
T5	6265	5	0	0
T6	16495	2	0	0
T7	0	3	0	0
T8	0	11	0	0
T10	0	4	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	1	0	0
T31	0	4	0	0
T59	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	16399	0	0
T1	36814	112	0	0
T2	1117	0	0	0
T3	33204	243	0	0
T5	6265	140	0	0
T6	16495	147	0	0
T7	0	81	0	0
T8	0	201	0	0
T10	0	309	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	66	0	0
T31	0	205	0	0
T59	0	401	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	342	0	0
T2	1117	0	0	0
T3	33204	3	0	0
T5	6265	5	0	0
T6	16495	1	0	0
T7	0	3	0	0
T8	0	11	0	0
T10	0	4	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	7102	1	0	0
T31	0	4	0	0
T33	0	1	0	0
T89	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T5,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T15
0	1	Covered	T21,T31,T59
1	0	Covered	T15,T21,T31

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T17
0	1	Covered	T1,T5,T17
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T17
1	-	Covered	T1,T5,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T15
DetectSt	168	Covered	T1,T5,T15
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T5,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T15
DebounceSt->IdleSt	163	Covered	T21,T75,T193
DetectSt->IdleSt	186	Covered	T15,T21,T31
DetectSt->StableSt	191	Covered	T1,T5,T17
IdleSt->DebounceSt	148	Covered	T1,T5,T15
StableSt->IdleSt	206	Covered	T1,T5,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T15
0	1	Covered	T1,T5,T15
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T15
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T15
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T75,T193
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T15
DetectSt	-	-	-	-	1	-	-	Covered	T15,T21,T31
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T17
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T15
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T17
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T17
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	3061	0	0
CntIncr_A	6449837	125466	0	0
CntNoWrap_A	6449837	5826600	0	0
DetectStDropOut_A	6449837	406	0	0
DetectedOut_A	6449837	85413	0	0
DetectedPulseOut_A	6449837	879	0	0
DisabledIdleSt_A	6449837	5317167	0	0
DisabledNoDetection_A	6449837	5319277	0	0
EnterDebounceSt_A	6449837	1549	0	0
EnterDetectSt_A	6449837	1512	0	0
EnterStableSt_A	6449837	879	0	0
PulseIsPulse_A	6449837	879	0	0
StayInStableSt	6449837	84449	0	0
gen_high_event_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_high_level_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	793	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	3061	0	0
T1	36814	24	0	0
T2	1117	0	0	0
T3	33204	18	0	0
T5	6265	6	0	0
T6	16495	22	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	26	0	0
T16	502	0	0	0
T17	9843	54	0	0
T21	0	16	0	0
T31	0	24	0	0
T39	0	56	0	0
T59	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	125466	0	0
T1	36814	624	0	0
T2	1117	0	0	0
T3	33204	2187	0	0
T5	6265	96	0	0
T6	16495	770	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	4232	0	0
T16	502	0	0	0
T17	9843	1944	0	0
T21	0	436	0	0
T31	0	586	0	0
T39	0	1764	0	0
T59	0	1497	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5826600	0	0
T1	36814	36294	0	0
T2	1117	716	0	0
T3	33204	32763	0	0
T4	402	1	0	0
T5	6265	5858	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29296	0	0
T16	502	101	0	0
T17	9843	9381	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	406	0	0
T7	22466	0	0	0
T8	37851	0	0	0
T21	7102	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T26	506	0	0	0
T28	769	0	0	0
T31	0	7	0	0
T45	494	0	0	0
T46	403	0	0	0
T47	429	0	0	0
T59	0	20	0	0
T74	0	23	0	0
T75	0	23	0	0
T76	0	25	0	0
T92	0	6	0	0
T114	0	3	0	0
T196	0	8	0	0
T210	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	85413	0	0
T1	36814	930	0	0
T2	1117	0	0	0
T3	33204	4120	0	0
T5	6265	81	0	0
T6	16495	352	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	1435	0	0
T21	0	283	0	0
T39	0	2179	0	0
T149	0	1806	0	0
T195	0	117	0	0
T211	0	876	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	879	0	0
T1	36814	12	0	0
T2	1117	0	0	0
T3	33204	9	0	0
T5	6265	3	0	0
T6	16495	11	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	27	0	0
T21	0	5	0	0
T39	0	28	0	0
T149	0	27	0	0
T195	0	15	0	0
T211	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5317167	0	0
T1	36814	30973	0	0
T2	1117	716	0	0
T3	33204	9772	0	0
T4	402	1	0	0
T5	6265	2796	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	12862	0	0
T16	502	101	0	0
T17	9843	4057	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5319277	0	0
T1	36814	30984	0	0
T2	1117	717	0	0
T3	33204	9772	0	0
T4	402	2	0	0
T5	6265	2796	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	12865	0	0
T16	502	102	0	0
T17	9843	4057	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	1549	0	0
T1	36814	12	0	0
T2	1117	0	0	0
T3	33204	9	0	0
T5	6265	3	0	0
T6	16495	11	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	13	0	0
T16	502	0	0	0
T17	9843	27	0	0
T21	0	9	0	0
T31	0	12	0	0
T39	0	28	0	0
T59	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	1512	0	0
T1	36814	12	0	0
T2	1117	0	0	0
T3	33204	9	0	0
T5	6265	3	0	0
T6	16495	11	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	13	0	0
T16	502	0	0	0
T17	9843	27	0	0
T21	0	7	0	0
T31	0	12	0	0
T39	0	28	0	0
T59	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	879	0	0
T1	36814	12	0	0
T2	1117	0	0	0
T3	33204	9	0	0
T5	6265	3	0	0
T6	16495	11	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	27	0	0
T21	0	5	0	0
T39	0	28	0	0
T149	0	27	0	0
T195	0	15	0	0
T211	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	879	0	0
T1	36814	12	0	0
T2	1117	0	0	0
T3	33204	9	0	0
T5	6265	3	0	0
T6	16495	11	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	27	0	0
T21	0	5	0	0
T39	0	28	0	0
T149	0	27	0	0
T195	0	15	0	0
T211	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	84449	0	0
T1	36814	916	0	0
T2	1117	0	0	0
T3	33204	4108	0	0
T5	6265	78	0	0
T6	16495	339	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	1407	0	0
T21	0	278	0	0
T39	0	2151	0	0
T149	0	1779	0	0
T195	0	102	0	0
T211	0	850	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	793	0	0
T1	36814	10	0	0
T2	1117	0	0	0
T3	33204	6	0	0
T5	6265	3	0	0
T6	16495	9	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	26	0	0
T21	0	5	0	0
T39	0	28	0	0
T149	0	27	0	0
T195	0	15	0	0
T211	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T17,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T17,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T17,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T17,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T3
0	1	Covered	T23,T38,T44
1	0	Covered	T21,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T17,T3
1	-	Covered	T1,T3,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T17,T3
DetectSt	168	Covered	T1,T17,T3
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T17,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T17,T3
DebounceSt->IdleSt	163	Covered	T21,T8,T212
DetectSt->IdleSt	186	Covered	T21,T23,T38
DetectSt->StableSt	191	Covered	T1,T17,T3
IdleSt->DebounceSt	148	Covered	T1,T17,T3
StableSt->IdleSt	206	Covered	T1,T17,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T17,T3
0	1	Covered	T1,T17,T3
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T17,T3
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T17,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T17,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T212,T197
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T17,T3
DetectSt	-	-	-	-	1	-	-	Covered	T21,T23,T38
DetectSt	-	-	-	-	0	1	-	Covered	T1,T17,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T17,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T17,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	849	0	0
CntIncr_A	6449837	46899	0	0
CntNoWrap_A	6449837	5828812	0	0
DetectStDropOut_A	6449837	58	0	0
DetectedOut_A	6449837	16162	0	0
DetectedPulseOut_A	6449837	341	0	0
DisabledIdleSt_A	6449837	5462325	0	0
DisabledNoDetection_A	6449837	5463926	0	0
EnterDebounceSt_A	6449837	446	0	0
EnterDetectSt_A	6449837	403	0	0
EnterStableSt_A	6449837	341	0	0
PulseIsPulse_A	6449837	341	0	0
StayInStableSt	6449837	15799	0	0
gen_high_level_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	318	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	849	0	0
T1	36814	4	0	0
T2	1117	0	0	0
T3	33204	6	0	0
T5	6265	0	0	0
T6	16495	4	0	0
T7	0	10	0	0
T8	0	25	0	0
T10	0	4	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	2	0	0
T21	0	8	0	0
T23	0	8	0	0
T39	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	46899	0	0
T1	36814	112	0	0
T2	1117	0	0	0
T3	33204	750	0	0
T5	6265	0	0	0
T6	16495	108	0	0
T7	0	710	0	0
T8	0	805	0	0
T10	0	318	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	66	0	0
T21	0	144	0	0
T23	0	211	0	0
T39	0	184	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5828812	0	0
T1	36814	36314	0	0
T2	1117	716	0	0
T3	33204	32775	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9433	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	58	0	0
T23	15192	4	0	0
T30	2499	0	0	0
T36	534	0	0	0
T37	501	0	0	0
T38	0	2	0	0
T44	0	5	0	0
T52	504	0	0	0
T53	504	0	0	0
T54	526	0	0	0
T81	0	8	0	0
T84	0	5	0	0
T98	406	0	0	0
T99	411	0	0	0
T103	433	0	0	0
T213	0	3	0	0
T214	0	1	0	0
T215	0	3	0	0
T216	0	6	0	0
T217	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	16162	0	0
T1	36814	151	0	0
T2	1117	0	0	0
T3	33204	233	0	0
T5	6265	0	0	0
T6	16495	193	0	0
T7	0	80	0	0
T8	0	196	0	0
T10	0	20	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	41	0	0
T21	0	67	0	0
T39	0	92	0	0
T40	0	28	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	341	0	0
T1	36814	2	0	0
T2	1117	0	0	0
T3	33204	3	0	0
T5	6265	0	0	0
T6	16495	2	0	0
T7	0	5	0	0
T8	0	12	0	0
T10	0	2	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	1	0	0
T21	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5462325	0	0
T1	36814	35390	0	0
T2	1117	716	0	0
T3	33204	28664	0	0
T4	402	1	0	0
T5	6265	5783	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	8001	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5463926	0	0
T1	36814	35402	0	0
T2	1117	717	0	0
T3	33204	28665	0	0
T4	402	2	0	0
T5	6265	5784	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	8002	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	446	0	0
T1	36814	2	0	0
T2	1117	0	0	0
T3	33204	3	0	0
T5	6265	0	0	0
T6	16495	2	0	0
T7	0	5	0	0
T8	0	13	0	0
T10	0	2	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	1	0	0
T21	0	5	0	0
T23	0	4	0	0
T39	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	403	0	0
T1	36814	2	0	0
T2	1117	0	0	0
T3	33204	3	0	0
T5	6265	0	0	0
T6	16495	2	0	0
T7	0	5	0	0
T8	0	12	0	0
T10	0	2	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	1	0	0
T21	0	3	0	0
T23	0	4	0	0
T39	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	341	0	0
T1	36814	2	0	0
T2	1117	0	0	0
T3	33204	3	0	0
T5	6265	0	0	0
T6	16495	2	0	0
T7	0	5	0	0
T8	0	12	0	0
T10	0	2	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	1	0	0
T21	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	341	0	0
T1	36814	2	0	0
T2	1117	0	0	0
T3	33204	3	0	0
T5	6265	0	0	0
T6	16495	2	0	0
T7	0	5	0	0
T8	0	12	0	0
T10	0	2	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	1	0	0
T21	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	15799	0	0
T1	36814	148	0	0
T2	1117	0	0	0
T3	33204	230	0	0
T5	6265	0	0	0
T6	16495	191	0	0
T7	0	75	0	0
T8	0	184	0	0
T10	0	18	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	39	0	0
T21	0	66	0	0
T39	0	90	0	0
T40	0	26	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	318	0	0
T1	36814	1	0	0
T2	1117	0	0	0
T3	33204	3	0	0
T5	6265	0	0	0
T6	16495	2	0	0
T7	0	5	0	0
T8	0	12	0	0
T10	0	2	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	1	0	0
T33	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0