Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T5,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T15
0	1	Covered	T15,T6,T21
1	0	Covered	T15,T6,T21

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T17
0	1	Covered	T1,T5,T17
1	0	Covered	T6,T66

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T17
1	-	Covered	T1,T5,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T15
DetectSt	168	Covered	T1,T5,T15
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T5,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T15
DebounceSt->IdleSt	163	Covered	T21,T75,T193
DetectSt->IdleSt	186	Covered	T15,T6,T21
DetectSt->StableSt	191	Covered	T1,T5,T17
IdleSt->DebounceSt	148	Covered	T1,T5,T15
StableSt->IdleSt	206	Covered	T1,T5,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T15
0	1	Covered	T1,T5,T15
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T15
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T15
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T75,T193
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T15
DetectSt	-	-	-	-	1	-	-	Covered	T15,T6,T21
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T17
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T15
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T17
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T17
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	2692	0	0
CntIncr_A	6449837	110754	0	0
CntNoWrap_A	6449837	5826969	0	0
DetectStDropOut_A	6449837	280	0	0
DetectedOut_A	6449837	70507	0	0
DetectedPulseOut_A	6449837	839	0	0
DisabledIdleSt_A	6449837	5325613	0	0
DisabledNoDetection_A	6449837	5327727	0	0
EnterDebounceSt_A	6449837	1366	0	0
EnterDetectSt_A	6449837	1326	0	0
EnterStableSt_A	6449837	839	0	0
PulseIsPulse_A	6449837	839	0	0
StayInStableSt	6449837	69586	0	0
gen_high_event_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_high_level_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	744	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	2692	0	0
T1	36814	40	0	0
T2	1117	0	0	0
T3	33204	18	0	0
T5	6265	42	0	0
T6	16495	28	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	46	0	0
T16	502	0	0	0
T17	9843	24	0	0
T21	0	16	0	0
T31	0	26	0	0
T39	0	20	0	0
T59	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	110754	0	0
T1	36814	1300	0	0
T2	1117	0	0	0
T3	33204	2349	0	0
T5	6265	1197	0	0
T6	16495	987	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	7488	0	0
T16	502	0	0	0
T17	9843	756	0	0
T21	0	568	0	0
T31	0	325	0	0
T39	0	710	0	0
T59	0	684	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5826969	0	0
T1	36814	36278	0	0
T2	1117	716	0	0
T3	33204	32763	0	0
T4	402	1	0	0
T5	6265	5822	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29276	0	0
T16	502	101	0	0
T17	9843	9411	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	280	0	0
T2	1117	0	0	0
T3	33204	0	0	0
T6	16495	3	0	0
T7	22466	0	0	0
T15	29746	6	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	7102	1	0	0
T24	492	0	0	0
T25	493	0	0	0
T74	0	10	0	0
T75	0	5	0	0
T76	0	25	0	0
T195	0	8	0	0
T196	0	22	0	0
T198	0	24	0	0
T199	0	25	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	70507	0	0
T1	36814	2355	0	0
T2	1117	0	0	0
T3	33204	3958	0	0
T5	6265	64	0	0
T6	16495	1	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	196	0	0
T21	0	378	0	0
T31	0	1334	0	0
T39	0	173	0	0
T59	0	2063	0	0
T211	0	1290	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	839	0	0
T1	36814	20	0	0
T2	1117	0	0	0
T3	33204	9	0	0
T5	6265	21	0	0
T6	16495	1	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	12	0	0
T21	0	5	0	0
T31	0	13	0	0
T39	0	10	0	0
T59	0	12	0	0
T211	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5325613	0	0
T1	36814	29628	0	0
T2	1117	716	0	0
T3	33204	9772	0	0
T4	402	1	0	0
T5	6265	2733	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	12862	0	0
T16	502	101	0	0
T17	9843	5335	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5327727	0	0
T1	36814	29632	0	0
T2	1117	717	0	0
T3	33204	9772	0	0
T4	402	2	0	0
T5	6265	2733	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	12865	0	0
T16	502	102	0	0
T17	9843	5336	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	1366	0	0
T1	36814	20	0	0
T2	1117	0	0	0
T3	33204	9	0	0
T5	6265	21	0	0
T6	16495	14	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	23	0	0
T16	502	0	0	0
T17	9843	12	0	0
T21	0	9	0	0
T31	0	13	0	0
T39	0	10	0	0
T59	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	1326	0	0
T1	36814	20	0	0
T2	1117	0	0	0
T3	33204	9	0	0
T5	6265	21	0	0
T6	16495	14	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	23	0	0
T16	502	0	0	0
T17	9843	12	0	0
T21	0	7	0	0
T31	0	13	0	0
T39	0	10	0	0
T59	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	839	0	0
T1	36814	20	0	0
T2	1117	0	0	0
T3	33204	9	0	0
T5	6265	21	0	0
T6	16495	1	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	12	0	0
T21	0	5	0	0
T31	0	13	0	0
T39	0	10	0	0
T59	0	12	0	0
T211	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	839	0	0
T1	36814	20	0	0
T2	1117	0	0	0
T3	33204	9	0	0
T5	6265	21	0	0
T6	16495	1	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	12	0	0
T21	0	5	0	0
T31	0	13	0	0
T39	0	10	0	0
T59	0	12	0	0
T211	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	69586	0	0
T1	36814	2326	0	0
T2	1117	0	0	0
T3	33204	3946	0	0
T5	6265	43	0	0
T6	16495	0	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	184	0	0
T21	0	373	0	0
T31	0	1317	0	0
T39	0	163	0	0
T59	0	2044	0	0
T149	0	314	0	0
T211	0	1263	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	744	0	0
T1	36814	11	0	0
T2	1117	0	0	0
T3	33204	6	0	0
T5	6265	21	0	0
T6	16495	0	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	12	0	0
T21	0	5	0	0
T31	0	9	0	0
T39	0	10	0	0
T59	0	5	0	0
T149	0	8	0	0
T211	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T15
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T3,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Covered	T1,T5,T15
1	1	Covered	T1,T3,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T21
0	1	Covered	T44,T214,T218
1	0	Covered	T21,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T21
0	1	Covered	T3,T7,T8
1	0	Covered	T21

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T21
1	-	Covered	T3,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T21
DetectSt	168	Covered	T1,T3,T21
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T3,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T21
DebounceSt->IdleSt	163	Covered	T21,T33,T93
DetectSt->IdleSt	186	Covered	T21,T44,T214
DetectSt->StableSt	191	Covered	T1,T3,T21
IdleSt->DebounceSt	148	Covered	T1,T3,T21
StableSt->IdleSt	206	Covered	T1,T3,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T21
0	1	Covered	T1,T3,T21
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T21
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T93,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T21
DetectSt	-	-	-	-	1	-	-	Covered	T21,T44,T214
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T21
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T21
StableSt	-	-	-	-	-	-	1	Covered	T3,T21,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6449837	843	0	0
CntIncr_A	6449837	45312	0	0
CntNoWrap_A	6449837	5828818	0	0
DetectStDropOut_A	6449837	44	0	0
DetectedOut_A	6449837	14015	0	0
DetectedPulseOut_A	6449837	354	0	0
DisabledIdleSt_A	6449837	5474905	0	0
DisabledNoDetection_A	6449837	5476503	0	0
EnterDebounceSt_A	6449837	442	0	0
EnterDetectSt_A	6449837	402	0	0
EnterStableSt_A	6449837	354	0	0
PulseIsPulse_A	6449837	354	0	0
StayInStableSt	6449837	13623	0	0
gen_high_level_sva.HighLevelEvent_A	6449837	5831944	0	0
gen_not_sticky_sva.StableStDropOut_A	6449837	314	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	843	0	0
T1	36814	12	0	0
T2	1117	0	0	0
T3	33204	4	0	0
T5	6265	0	0	0
T6	16495	0	0	0
T7	0	10	0	0
T8	0	20	0	0
T10	0	2	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	8	0	0
T23	0	4	0	0
T31	0	2	0	0
T40	0	2	0	0
T59	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	45312	0	0
T1	36814	300	0	0
T2	1117	0	0	0
T3	33204	546	0	0
T5	6265	0	0	0
T6	16495	0	0	0
T7	0	760	0	0
T8	0	530	0	0
T10	0	94	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	241	0	0
T23	0	96	0	0
T31	0	48	0	0
T40	0	100	0	0
T59	0	400	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5828818	0	0
T1	36814	36306	0	0
T2	1117	716	0	0
T3	33204	32777	0	0
T4	402	1	0	0
T5	6265	5864	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9435	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	44	0	0
T44	186187	1	0	0
T73	9186	0	0	0
T81	0	6	0	0
T90	655	0	0	0
T141	813	0	0	0
T143	783	0	0	0
T146	0	2	0	0
T203	0	4	0	0
T210	16669	0	0	0
T214	0	2	0	0
T216	0	6	0	0
T217	0	3	0	0
T218	0	1	0	0
T220	0	3	0	0
T221	0	6	0	0
T222	407	0	0	0
T223	496	0	0	0
T224	929	0	0	0
T225	689	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	14015	0	0
T1	36814	482	0	0
T2	1117	0	0	0
T3	33204	108	0	0
T5	6265	0	0	0
T6	16495	0	0	0
T7	0	34	0	0
T8	0	271	0	0
T10	0	75	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	67	0	0
T23	0	8	0	0
T31	0	56	0	0
T40	0	64	0	0
T59	0	731	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	354	0	0
T1	36814	6	0	0
T2	1117	0	0	0
T3	33204	2	0	0
T5	6265	0	0	0
T6	16495	0	0	0
T7	0	5	0	0
T8	0	10	0	0
T10	0	1	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	1	0	0
T23	0	2	0	0
T31	0	1	0	0
T40	0	1	0	0
T59	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5474905	0	0
T1	36814	33972	0	0
T2	1117	716	0	0
T3	33204	28826	0	0
T4	402	1	0	0
T5	6265	5799	0	0
T13	630	229	0	0
T14	828	427	0	0
T15	29746	29322	0	0
T16	502	101	0	0
T17	9843	9239	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5476503	0	0
T1	36814	33977	0	0
T2	1117	717	0	0
T3	33204	28827	0	0
T4	402	2	0	0
T5	6265	5800	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9241	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	442	0	0
T1	36814	6	0	0
T2	1117	0	0	0
T3	33204	2	0	0
T5	6265	0	0	0
T6	16495	0	0	0
T7	0	5	0	0
T8	0	10	0	0
T10	0	1	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	5	0	0
T23	0	2	0	0
T31	0	1	0	0
T40	0	1	0	0
T59	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	402	0	0
T1	36814	6	0	0
T2	1117	0	0	0
T3	33204	2	0	0
T5	6265	0	0	0
T6	16495	0	0	0
T7	0	5	0	0
T8	0	10	0	0
T10	0	1	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	3	0	0
T23	0	2	0	0
T31	0	1	0	0
T40	0	1	0	0
T59	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	354	0	0
T1	36814	6	0	0
T2	1117	0	0	0
T3	33204	2	0	0
T5	6265	0	0	0
T6	16495	0	0	0
T7	0	5	0	0
T8	0	10	0	0
T10	0	1	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	1	0	0
T23	0	2	0	0
T31	0	1	0	0
T40	0	1	0	0
T59	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	354	0	0
T1	36814	6	0	0
T2	1117	0	0	0
T3	33204	2	0	0
T5	6265	0	0	0
T6	16495	0	0	0
T7	0	5	0	0
T8	0	10	0	0
T10	0	1	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	1	0	0
T23	0	2	0	0
T31	0	1	0	0
T40	0	1	0	0
T59	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	13623	0	0
T1	36814	470	0	0
T2	1117	0	0	0
T3	33204	106	0	0
T5	6265	0	0	0
T6	16495	0	0	0
T7	0	29	0	0
T8	0	261	0	0
T10	0	74	0	0
T13	630	0	0	0
T14	828	0	0	0
T15	29746	0	0	0
T16	502	0	0	0
T17	9843	0	0	0
T21	0	66	0	0
T23	0	6	0	0
T31	0	55	0	0
T40	0	63	0	0
T59	0	715	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	5831944	0	0
T1	36814	36332	0	0
T2	1117	717	0	0
T3	33204	32785	0	0
T4	402	2	0	0
T5	6265	5865	0	0
T13	630	230	0	0
T14	828	428	0	0
T15	29746	29326	0	0
T16	502	102	0	0
T17	9843	9437	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6449837	314	0	0
T3	33204	2	0	0
T6	16495	0	0	0
T7	22466	5	0	0
T8	37851	10	0	0
T10	0	1	0	0
T21	7102	0	0	0
T23	0	2	0	0
T24	492	0	0	0
T25	493	0	0	0
T28	769	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T40	0	1	0	0
T45	494	0	0	0
T46	403	0	0	0
T59	0	4	0	0
T89	0	4	0	0