Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T24,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T24,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T24,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T24,T25
1	0	Covered	T4,T1,T5
1	1	Covered	T7,T24,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T24,T25
0	1	Covered	T71,T104,T106
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T24,T25
0	1	Covered	T7,T24,T25
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T24,T25
1	-	Covered	T7,T24,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T24,T25
DetectSt	168	Covered	T7,T24,T25
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T24,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T24,T25
DebounceSt->IdleSt	163	Covered	T25,T55,T71
DetectSt->IdleSt	186	Covered	T71,T104,T106
DetectSt->StableSt	191	Covered	T7,T24,T25
IdleSt->DebounceSt	148	Covered	T7,T24,T25
StableSt->IdleSt	206	Covered	T7,T24,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T24,T25
0	1	Covered	T7,T24,T25
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T24,T25
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T24,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T24,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T25,T71,T31
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T24,T25
DetectSt	-	-	-	-	1	-	-	Covered	T71,T104,T106
DetectSt	-	-	-	-	0	1	-	Covered	T7,T24,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T24,T25
StableSt	-	-	-	-	-	-	0	Covered	T7,T24,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	285	0	0
CntIncr_A	8235605	125061	0	0
CntNoWrap_A	8235605	7597760	0	0
DetectStDropOut_A	8235605	5	0	0
DetectedOut_A	8235605	806	0	0
DetectedPulseOut_A	8235605	127	0	0
DisabledIdleSt_A	8235605	7466467	0	0
DisabledNoDetection_A	8235605	7468787	0	0
EnterDebounceSt_A	8235605	158	0	0
EnterDetectSt_A	8235605	132	0	0
EnterStableSt_A	8235605	127	0	0
PulseIsPulse_A	8235605	127	0	0
StayInStableSt	8235605	679	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8235605	6784	0	0
gen_low_level_sva.LowLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	127	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	285	0	0
T7	3625	4	0	0
T8	22766	0	0	0
T9	608	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	6	0	0
T25	633	5	0	0
T43	0	4	0	0
T44	0	4	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	658	0	0	0
T92	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	125061	0	0
T7	3625	28	0	0
T8	22766	0	0	0
T9	608	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	236	0	0
T25	633	118	0	0
T43	0	154	0	0
T44	0	55	0	0
T45	0	107	0	0
T46	0	69	0	0
T47	0	36	0	0
T48	0	80	0	0
T49	658	0	0	0
T55	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597760	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1216	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	5	0	0
T71	11017	1	0	0
T96	5869	0	0	0
T104	0	1	0	0
T106	0	2	0	0
T109	0	1	0	0
T110	21347	0	0	0
T111	845	0	0	0
T112	522	0	0	0
T113	13374	0	0	0
T114	491	0	0	0
T115	37311	0	0	0
T116	404	0	0	0
T117	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	806	0	0
T7	3625	9	0	0
T8	22766	0	0	0
T9	608	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	23	0	0
T25	633	14	0	0
T43	0	17	0	0
T44	0	12	0	0
T45	0	5	0	0
T46	0	5	0	0
T47	0	4	0	0
T48	0	11	0	0
T49	658	0	0	0
T92	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	127	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	3	0	0
T25	633	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	658	0	0	0
T92	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7466467	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1112	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7468787	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1117	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	158	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	3	0	0
T25	633	3	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	658	0	0	0
T55	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	132	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	3	0	0
T25	633	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	658	0	0	0
T92	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	127	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	3	0	0
T25	633	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	658	0	0	0
T92	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	127	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	3	0	0
T25	633	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	658	0	0	0
T92	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	679	0	0
T7	3625	7	0	0
T8	22766	0	0	0
T9	608	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	20	0	0
T25	633	12	0	0
T43	0	15	0	0
T44	0	10	0	0
T45	0	3	0	0
T46	0	4	0	0
T47	0	3	0	0
T48	0	10	0	0
T49	658	0	0	0
T92	0	5	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6784	0	0
T1	1121	5	0	0
T2	33179	14	0	0
T3	1059	1	0	0
T4	494	7	0	0
T5	492	6	0	0
T6	3067	16	0	0
T7	3625	20	0	0
T13	5766	25	0	0
T14	490	7	0	0
T15	408	0	0	0
T16	0	29	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	127	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	3	0	0
T25	633	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	658	0	0	0
T92	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T17,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T17,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T17,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T21
1	0	Covered	T4,T5,T2
1	1	Covered	T1,T17,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T54
0	1	Covered	T74,T89,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T54
0	1	Unreachable
1	0	Covered	T1,T17,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T17,T21
DetectSt	168	Covered	T1,T17,T54
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T17,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T17,T54
DebounceSt->IdleSt	163	Covered	T21,T57,T73
DetectSt->IdleSt	186	Covered	T74,T89,T90
DetectSt->StableSt	191	Covered	T1,T17,T54
IdleSt->DebounceSt	148	Covered	T1,T17,T21
StableSt->IdleSt	206	Covered	T1,T17,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T17,T21
0	1	Covered	T1,T17,T21
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T17,T54
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T17,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T17,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T57,T73
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T17,T21
DetectSt	-	-	-	-	1	-	-	Covered	T74,T89,T90
DetectSt	-	-	-	-	0	1	-	Covered	T1,T17,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T17,T54
StableSt	-	-	-	-	-	-	0	Covered	T1,T17,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	160	0	0
CntIncr_A	8235605	124000	0	0
CntNoWrap_A	8235605	7597885	0	0
DetectStDropOut_A	8235605	9	0	0
DetectedOut_A	8235605	166118	0	0
DetectedPulseOut_A	8235605	46	0	0
DisabledIdleSt_A	8235605	6107833	0	0
DisabledNoDetection_A	8235605	6110192	0	0
EnterDebounceSt_A	8235605	106	0	0
EnterDetectSt_A	8235605	55	0	0
EnterStableSt_A	8235605	46	0	0
PulseIsPulse_A	8235605	46	0	0
StayInStableSt	8235605	166072	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8235605	6784	0	0
gen_low_level_sva.LowLevelEvent_A	8235605	7600407	0	0
gen_sticky_sva.StableStDropOut_A	8235605	177279	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	160	0	0
T1	1121	2	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	2	0	0
T21	0	3	0	0
T54	0	2	0	0
T57	0	5	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	124000	0	0
T1	1121	90	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	39	0	0
T21	0	207	0	0
T54	0	95	0	0
T57	0	395	0	0
T71	0	54	0	0
T72	0	11	0	0
T73	0	68	0	0
T74	0	84	0	0
T75	0	396	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597885	0	0
T1	1121	718	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	9	0	0
T74	5810	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T133	0	1	0	0
T134	0	3	0	0
T135	0	2	0	0
T136	31989	0	0	0
T137	416	0	0	0
T138	455	0	0	0
T139	427	0	0	0
T140	16537	0	0	0
T141	523	0	0	0
T142	41705	0	0	0
T143	20758	0	0	0
T144	491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	166118	0	0
T1	1121	483	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	309	0	0
T54	0	722	0	0
T71	0	356	0	0
T72	0	23	0	0
T84	0	380	0	0
T85	0	42	0	0
T88	0	147	0	0
T131	0	118	0	0
T132	0	104	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	46	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	1	0	0
T54	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T88	0	1	0	0
T131	0	2	0	0
T132	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6107833	0	0
T1	1121	25	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6110192	0	0
T1	1121	26	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	106	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	1	0	0
T21	0	3	0	0
T54	0	1	0	0
T57	0	5	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	55	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	1	0	0
T54	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T74	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T131	0	2	0	0
T132	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	46	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	1	0	0
T54	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T88	0	1	0	0
T131	0	2	0	0
T132	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	46	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	1	0	0
T54	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T88	0	1	0	0
T131	0	2	0	0
T132	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	166072	0	0
T1	1121	482	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	308	0	0
T54	0	721	0	0
T71	0	355	0	0
T72	0	22	0	0
T84	0	379	0	0
T85	0	41	0	0
T88	0	146	0	0
T131	0	116	0	0
T132	0	103	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6784	0	0
T1	1121	5	0	0
T2	33179	14	0	0
T3	1059	1	0	0
T4	494	7	0	0
T5	492	6	0	0
T6	3067	16	0	0
T7	3625	20	0	0
T13	5766	25	0	0
T14	490	7	0	0
T15	408	0	0	0
T16	0	29	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	177279	0	0
T1	1121	110	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	292	0	0
T54	0	100	0	0
T71	0	88	0	0
T72	0	2199	0	0
T84	0	328	0	0
T85	0	50	0	0
T88	0	174	0	0
T131	0	391	0	0
T132	0	634	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T17,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T17,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T17,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T21
1	0	Covered	T4,T5,T3
1	1	Covered	T1,T17,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T54
0	1	Covered	T54,T74,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T54
0	1	Unreachable
1	0	Covered	T1,T17,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T17,T21
DetectSt	168	Covered	T1,T17,T54
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T17,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T17,T54
DebounceSt->IdleSt	163	Covered	T21,T54,T75
DetectSt->IdleSt	186	Covered	T54,T74,T88
DetectSt->StableSt	191	Covered	T1,T17,T54
IdleSt->DebounceSt	148	Covered	T1,T17,T21
StableSt->IdleSt	206	Covered	T1,T17,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T17,T21
0	1	Covered	T1,T17,T21
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T17,T54
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T17,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T17,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T54,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T17,T21
DetectSt	-	-	-	-	1	-	-	Covered	T54,T74,T88
DetectSt	-	-	-	-	0	1	-	Covered	T1,T17,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T17,T54
StableSt	-	-	-	-	-	-	0	Covered	T1,T17,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	166	0	0
CntIncr_A	8235605	154132	0	0
CntNoWrap_A	8235605	7597879	0	0
DetectStDropOut_A	8235605	13	0	0
DetectedOut_A	8235605	685644	0	0
DetectedPulseOut_A	8235605	43	0	0
DisabledIdleSt_A	8235605	6107833	0	0
DisabledNoDetection_A	8235605	6110192	0	0
EnterDebounceSt_A	8235605	111	0	0
EnterDetectSt_A	8235605	56	0	0
EnterStableSt_A	8235605	43	0	0
PulseIsPulse_A	8235605	43	0	0
StayInStableSt	8235605	685601	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_sticky_sva.StableStDropOut_A	8235605	230028	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	166	0	0
T1	1121	2	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	2	0	0
T21	0	3	0	0
T54	0	6	0	0
T57	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	154132	0	0
T1	1121	47	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	73	0	0
T21	0	42756	0	0
T54	0	176	0	0
T57	0	93	0	0
T71	0	54	0	0
T72	0	47	0	0
T73	0	53	0	0
T74	0	46	0	0
T75	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597879	0	0
T1	1121	718	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	13	0	0
T32	24339	0	0	0
T33	750	0	0	0
T35	543	0	0	0
T47	662	0	0	0
T48	768	0	0	0
T54	2832	1	0	0
T74	0	1	0	0
T88	0	1	0	0
T91	10305	0	0	0
T95	8533	0	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	428	0	0	0
T151	435	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	685644	0	0
T1	1121	202	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	316	0	0
T54	0	47	0	0
T57	0	426	0	0
T71	0	348	0	0
T72	0	93	0	0
T73	0	4	0	0
T85	0	27	0	0
T88	0	62	0	0
T132	0	191	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	43	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T85	0	1	0	0
T88	0	1	0	0
T132	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6107833	0	0
T1	1121	25	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6110192	0	0
T1	1121	26	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	111	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	1	0	0
T21	0	3	0	0
T54	0	4	0	0
T57	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	56	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	1	0	0
T54	0	2	0	0
T57	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T85	0	1	0	0
T132	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	43	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T85	0	1	0	0
T88	0	1	0	0
T132	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	43	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T85	0	1	0	0
T88	0	1	0	0
T132	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	685601	0	0
T1	1121	201	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	315	0	0
T54	0	46	0	0
T57	0	425	0	0
T71	0	347	0	0
T72	0	92	0	0
T73	0	3	0	0
T85	0	26	0	0
T88	0	61	0	0
T132	0	190	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	230028	0	0
T1	1121	438	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	257	0	0
T54	0	272	0	0
T57	0	115	0	0
T71	0	104	0	0
T72	0	2108	0	0
T73	0	83	0	0
T85	0	69	0	0
T88	0	118	0	0
T132	0	544	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T17,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T17,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T21,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T21
1	0	Covered	T4,T5,T2
1	1	Covered	T1,T17,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T21,T54
0	1	Covered	T84,T85,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T21,T54
0	1	Unreachable
1	0	Covered	T1,T21,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T17,T21
DetectSt	168	Covered	T1,T21,T54
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T21,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T21,T54
DebounceSt->IdleSt	163	Covered	T17,T73,T74
DetectSt->IdleSt	186	Covered	T84,T85,T86
DetectSt->StableSt	191	Covered	T1,T21,T54
IdleSt->DebounceSt	148	Covered	T1,T17,T21
StableSt->IdleSt	206	Covered	T1,T21,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T17,T21
0	1	Covered	T1,T17,T21
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T21,T54
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T17,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T21,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T73,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T17,T21
DetectSt	-	-	-	-	1	-	-	Covered	T84,T85,T86
DetectSt	-	-	-	-	0	1	-	Covered	T1,T21,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T21,T54
StableSt	-	-	-	-	-	-	0	Covered	T1,T21,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	150	0	0
CntIncr_A	8235605	149545	0	0
CntNoWrap_A	8235605	7597895	0	0
DetectStDropOut_A	8235605	11	0	0
DetectedOut_A	8235605	240778	0	0
DetectedPulseOut_A	8235605	44	0	0
DisabledIdleSt_A	8235605	6107833	0	0
DisabledNoDetection_A	8235605	6110192	0	0
EnterDebounceSt_A	8235605	96	0	0
EnterDetectSt_A	8235605	55	0	0
EnterStableSt_A	8235605	44	0	0
PulseIsPulse_A	8235605	44	0	0
StayInStableSt	8235605	240734	0	0
gen_high_event_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_sticky_sva.StableStDropOut_A	8235605	1094426	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	150	0	0
T1	1121	2	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	5	0	0
T21	0	2	0	0
T54	0	2	0	0
T57	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	149545	0	0
T1	1121	30	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	195	0	0
T21	0	43233	0	0
T54	0	82	0	0
T57	0	61	0	0
T71	0	31	0	0
T72	0	911	0	0
T73	0	72	0	0
T74	0	17	0	0
T75	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597895	0	0
T1	1121	718	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	11	0	0
T84	7549	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T145	0	1	0	0
T152	0	1	0	0
T153	0	6	0	0
T154	424	0	0	0
T155	12057	0	0	0
T156	156598	0	0	0
T157	402	0	0	0
T158	521	0	0	0
T159	508	0	0	0
T160	3886	0	0	0
T161	15680	0	0	0
T162	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	240778	0	0
T1	1121	221	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	164785	0	0
T54	0	448	0	0
T57	0	329	0	0
T71	0	169	0	0
T72	0	1315	0	0
T75	0	63	0	0
T84	0	97	0	0
T131	0	70	0	0
T132	0	645	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	44	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0
T84	0	1	0	0
T131	0	2	0	0
T132	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6107833	0	0
T1	1121	25	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6110192	0	0
T1	1121	26	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	96	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T17	0	5	0	0
T21	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	55	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T131	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	44	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0
T84	0	1	0	0
T131	0	2	0	0
T132	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	44	0	0
T1	1121	1	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0
T84	0	1	0	0
T131	0	2	0	0
T132	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	240734	0	0
T1	1121	220	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	164784	0	0
T54	0	447	0	0
T57	0	328	0	0
T71	0	168	0	0
T72	0	1314	0	0
T75	0	62	0	0
T84	0	96	0	0
T131	0	68	0	0
T132	0	644	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	1094426	0	0
T1	1121	438	0	0
T2	33179	0	0	0
T3	1059	0	0	0
T5	492	0	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T13	5766	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	27185	0	0
T54	0	395	0	0
T57	0	250	0	0
T71	0	312	0	0
T72	0	27	0	0
T75	0	406	0	0
T84	0	444	0	0
T131	0	511	0	0
T132	0	35	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T21,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T9,T21,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T21,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T34
1	0	Covered	T4,T1,T5
1	1	Covered	T9,T21,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T21,T31
0	1	Covered	T163
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T21,T31
0	1	Covered	T21,T80,T163
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T21,T31
1	-	Covered	T21,T80,T163

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T21,T31
DetectSt	168	Covered	T9,T21,T31
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T9,T21,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T21,T31
DebounceSt->IdleSt	163	Covered	T78,T164
DetectSt->IdleSt	186	Covered	T163
DetectSt->StableSt	191	Covered	T9,T21,T31
IdleSt->DebounceSt	148	Covered	T9,T21,T31
StableSt->IdleSt	206	Covered	T21,T31,T80

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T21,T31
0	1	Covered	T9,T21,T31
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T21,T31
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T21,T31
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T21,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T164
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T21,T31
DetectSt	-	-	-	-	1	-	-	Covered	T163
DetectSt	-	-	-	-	0	1	-	Covered	T9,T21,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T80,T163
StableSt	-	-	-	-	-	-	0	Covered	T9,T21,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	76	0	0
CntIncr_A	8235605	60739	0	0
CntNoWrap_A	8235605	7597969	0	0
DetectStDropOut_A	8235605	1	0	0
DetectedOut_A	8235605	48733	0	0
DetectedPulseOut_A	8235605	36	0	0
DisabledIdleSt_A	8235605	7376594	0	0
DisabledNoDetection_A	8235605	7378909	0	0
EnterDebounceSt_A	8235605	39	0	0
EnterDetectSt_A	8235605	37	0	0
EnterStableSt_A	8235605	36	0	0
PulseIsPulse_A	8235605	36	0	0
StayInStableSt	8235605	48678	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	76	0	0
T9	608	2	0	0
T21	0	4	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T27	571	0	0	0
T31	0	2	0	0
T49	658	0	0	0
T64	502	0	0	0
T78	0	1	0	0
T80	0	4	0	0
T93	421	0	0	0
T94	423	0	0	0
T163	0	6	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	60739	0	0
T9	608	23	0	0
T21	0	94	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T27	571	0	0	0
T31	0	34	0	0
T49	658	0	0	0
T64	502	0	0	0
T78	0	20	0	0
T80	0	12426	0	0
T93	421	0	0	0
T94	423	0	0	0
T163	0	133	0	0
T165	0	78	0	0
T166	0	19	0	0
T167	0	98	0	0
T168	0	140	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597969	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	1	0	0
T163	7811	1	0	0
T165	676	0	0	0
T169	504	0	0	0
T170	523	0	0	0
T171	402	0	0	0
T172	525	0	0	0
T173	857	0	0	0
T174	13893	0	0	0
T175	15413	0	0	0
T176	498	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	48733	0	0
T9	608	41	0	0
T21	0	82	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T27	571	0	0	0
T31	0	42	0	0
T49	658	0	0	0
T64	502	0	0	0
T80	0	80	0	0
T93	421	0	0	0
T94	423	0	0	0
T163	0	216	0	0
T165	0	41	0	0
T166	0	42	0	0
T167	0	39	0	0
T168	0	190	0	0
T177	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	36	0	0
T9	608	1	0	0
T21	0	2	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T27	571	0	0	0
T31	0	1	0	0
T49	658	0	0	0
T64	502	0	0	0
T80	0	2	0	0
T93	421	0	0	0
T94	423	0	0	0
T163	0	2	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	2	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7376594	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7378909	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	39	0	0
T9	608	1	0	0
T21	0	2	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T27	571	0	0	0
T31	0	1	0	0
T49	658	0	0	0
T64	502	0	0	0
T78	0	1	0	0
T80	0	2	0	0
T93	421	0	0	0
T94	423	0	0	0
T163	0	3	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	37	0	0
T9	608	1	0	0
T21	0	2	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T27	571	0	0	0
T31	0	1	0	0
T49	658	0	0	0
T64	502	0	0	0
T80	0	2	0	0
T93	421	0	0	0
T94	423	0	0	0
T163	0	3	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	2	0	0
T177	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	36	0	0
T9	608	1	0	0
T21	0	2	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T27	571	0	0	0
T31	0	1	0	0
T49	658	0	0	0
T64	502	0	0	0
T80	0	2	0	0
T93	421	0	0	0
T94	423	0	0	0
T163	0	2	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	2	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	36	0	0
T9	608	1	0	0
T21	0	2	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T27	571	0	0	0
T31	0	1	0	0
T49	658	0	0	0
T64	502	0	0	0
T80	0	2	0	0
T93	421	0	0	0
T94	423	0	0	0
T163	0	2	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	2	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	48678	0	0
T9	608	39	0	0
T21	0	79	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T27	571	0	0	0
T31	0	40	0	0
T49	658	0	0	0
T64	502	0	0	0
T80	0	77	0	0
T93	421	0	0	0
T94	423	0	0	0
T163	0	214	0	0
T165	0	39	0	0
T166	0	40	0	0
T167	0	37	0	0
T168	0	187	0	0
T177	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	16	0	0
T21	240285	1	0	0
T44	666	0	0	0
T45	735	0	0	0
T61	510	0	0	0
T76	17858	0	0	0
T80	0	1	0	0
T134	0	1	0	0
T163	0	2	0	0
T164	0	1	0	0
T168	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	2	0	0
T182	726	0	0	0
T183	109707	0	0	0
T184	413	0	0	0
T185	424	0	0	0
T186	502	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T11
1	0	Covered	T4,T5,T2
1	1	Covered	T3,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T3,T9,T12
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T11
1	-	Covered	T3,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T11
DetectSt	168	Covered	T3,T9,T11
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T11
DebounceSt->IdleSt	163	Covered	T78,T179,T181
DetectSt->IdleSt	186	Covered	T81
DetectSt->StableSt	191	Covered	T3,T9,T11
IdleSt->DebounceSt	148	Covered	T3,T9,T11
StableSt->IdleSt	206	Covered	T3,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T11
0	1	Covered	T3,T9,T11
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T11
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T179,T181
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T81
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	131	0	0
CntIncr_A	8235605	206783	0	0
CntNoWrap_A	8235605	7597914	0	0
DetectStDropOut_A	8235605	1	0	0
DetectedOut_A	8235605	60409	0	0
DetectedPulseOut_A	8235605	63	0	0
DisabledIdleSt_A	8235605	7049038	0	0
DisabledNoDetection_A	8235605	7051353	0	0
EnterDebounceSt_A	8235605	67	0	0
EnterDetectSt_A	8235605	64	0	0
EnterStableSt_A	8235605	63	0	0
PulseIsPulse_A	8235605	63	0	0
StayInStableSt	8235605	60318	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8235605	2462	0	0
gen_low_level_sva.LowLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	131	0	0
T3	1059	2	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	4	0	0
T24	759	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T37	0	2	0	0
T49	658	0	0	0
T187	0	2	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	206783	0	0
T3	1059	74	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	23	0	0
T11	0	61	0	0
T12	0	33	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	94	0	0
T24	759	0	0	0
T33	0	98	0	0
T34	0	46	0	0
T37	0	13	0	0
T49	658	0	0	0
T187	0	13	0	0
T188	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597914	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	656	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	1	0	0
T81	29840	1	0	0
T132	2585	0	0	0
T166	555	0	0	0
T189	45401	0	0	0
T190	402	0	0	0
T191	423	0	0	0
T192	526	0	0	0
T193	499	0	0	0
T194	817	0	0	0
T195	483	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	60409	0	0
T3	1059	152	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	23	0	0
T11	0	137	0	0
T12	0	87	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	50	0	0
T24	759	0	0	0
T33	0	158	0	0
T34	0	39	0	0
T37	0	40	0	0
T49	658	0	0	0
T187	0	7	0	0
T188	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	63	0	0
T3	1059	1	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	2	0	0
T24	759	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T187	0	1	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7049038	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	4	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7051353	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	4	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	67	0	0
T3	1059	1	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	2	0	0
T24	759	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T187	0	1	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	64	0	0
T3	1059	1	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	2	0	0
T24	759	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T187	0	1	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	63	0	0
T3	1059	1	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	2	0	0
T24	759	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T187	0	1	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	63	0	0
T3	1059	1	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	2	0	0
T24	759	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T187	0	1	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	60318	0	0
T3	1059	151	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	22	0	0
T11	0	135	0	0
T12	0	86	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	48	0	0
T24	759	0	0	0
T33	0	155	0	0
T34	0	37	0	0
T37	0	38	0	0
T49	658	0	0	0
T187	0	6	0	0
T188	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	2462	0	0
T1	1121	0	0	0
T2	33179	0	0	0
T3	1059	1	0	0
T4	494	4	0	0
T5	492	6	0	0
T6	3067	8	0	0
T7	3625	19	0	0
T9	0	1	0	0
T13	5766	0	0	0
T14	490	4	0	0
T15	408	0	0	0
T22	0	6	0	0
T23	0	5	0	0
T93	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	34	0	0
T3	1059	1	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	2	0	0
T24	759	0	0	0
T33	0	1	0	0
T49	658	0	0	0
T80	0	2	0	0
T81	0	2	0	0
T165	0	1	0	0
T187	0	1	0	0
T196	0	1	0	0