Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T6,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T9
1	0	Covered	T4,T1,T5
1	1	Covered	T3,T6,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T12
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T12
0	1	Covered	T3,T12,T33
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T12
1	-	Covered	T3,T12,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T12
DetectSt	168	Covered	T3,T6,T12
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T6,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T12
DebounceSt->IdleSt	163	Covered	T78,T164
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T6,T12
IdleSt->DebounceSt	148	Covered	T3,T6,T12
StableSt->IdleSt	206	Covered	T3,T6,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T12
0	1	Covered	T3,T6,T12
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T164
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T12,T33
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	86	0	0
CntIncr_A	8235605	102628	0	0
CntNoWrap_A	8235605	7597959	0	0
DetectStDropOut_A	8235605	0	0	0
DetectedOut_A	8235605	23146	0	0
DetectedPulseOut_A	8235605	42	0	0
DisabledIdleSt_A	8235605	7283695	0	0
DisabledNoDetection_A	8235605	7286005	0	0
EnterDebounceSt_A	8235605	44	0	0
EnterDetectSt_A	8235605	42	0	0
EnterStableSt_A	8235605	42	0	0
PulseIsPulse_A	8235605	42	0	0
StayInStableSt	8235605	23080	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	86	0	0
T3	1059	2	0	0
T6	3067	2	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	2	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	2	0	0
T24	759	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T49	658	0	0	0
T78	0	1	0	0
T80	0	2	0	0
T165	0	2	0	0
T187	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	102628	0	0
T3	1059	74	0	0
T6	3067	75	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	33	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	47	0	0
T24	759	0	0	0
T33	0	49	0	0
T34	0	46	0	0
T49	658	0	0	0
T78	0	21	0	0
T80	0	6213	0	0
T165	0	78	0	0
T187	0	26	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597959	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	656	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	660	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	23146	0	0
T3	1059	25	0	0
T6	3067	40	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	77	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	42	0	0
T24	759	0	0	0
T33	0	128	0	0
T34	0	215	0	0
T49	658	0	0	0
T80	0	18723	0	0
T81	0	405	0	0
T165	0	41	0	0
T187	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	42	0	0
T3	1059	1	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T49	658	0	0	0
T80	0	1	0	0
T81	0	2	0	0
T165	0	1	0	0
T187	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7283695	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	4	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	223	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7286005	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	4	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	227	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	44	0	0
T3	1059	1	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T49	658	0	0	0
T78	0	1	0	0
T80	0	1	0	0
T165	0	1	0	0
T187	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	42	0	0
T3	1059	1	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T49	658	0	0	0
T80	0	1	0	0
T81	0	2	0	0
T165	0	1	0	0
T187	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	42	0	0
T3	1059	1	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T49	658	0	0	0
T80	0	1	0	0
T81	0	2	0	0
T165	0	1	0	0
T187	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	42	0	0
T3	1059	1	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T49	658	0	0	0
T80	0	1	0	0
T81	0	2	0	0
T165	0	1	0	0
T187	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	23080	0	0
T3	1059	24	0	0
T6	3067	38	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	76	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	40	0	0
T24	759	0	0	0
T33	0	127	0	0
T34	0	213	0	0
T49	658	0	0	0
T80	0	18721	0	0
T81	0	402	0	0
T165	0	39	0	0
T187	0	79	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	17	0	0
T3	1059	1	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T33	0	1	0	0
T49	658	0	0	0
T81	0	1	0	0
T167	0	1	0	0
T178	0	1	0	0
T187	0	1	0	0
T197	0	1	0	0
T198	0	2	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T6,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T9
1	0	Covered	T4,T5,T2
1	1	Covered	T6,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T9
0	1	Covered	T200,T201,T181
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T9
0	1	Covered	T6,T7,T12
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T9
1	-	Covered	T6,T7,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T9
DetectSt	168	Covered	T6,T7,T9
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T6,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T9
DebounceSt->IdleSt	163	Covered	T78,T181,T135
DetectSt->IdleSt	186	Covered	T200,T201,T181
DetectSt->StableSt	191	Covered	T6,T7,T9
IdleSt->DebounceSt	148	Covered	T6,T7,T9
StableSt->IdleSt	206	Covered	T6,T7,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T7,T9
0	1	Covered	T6,T7,T9
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T9
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T181,T135
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T200,T201,T181
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T7,T12
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	131	0	0
CntIncr_A	8235605	10871	0	0
CntNoWrap_A	8235605	7597914	0	0
DetectStDropOut_A	8235605	3	0	0
DetectedOut_A	8235605	4223	0	0
DetectedPulseOut_A	8235605	61	0	0
DisabledIdleSt_A	8235605	7532871	0	0
DisabledNoDetection_A	8235605	7535180	0	0
EnterDebounceSt_A	8235605	67	0	0
EnterDetectSt_A	8235605	64	0	0
EnterStableSt_A	8235605	61	0	0
PulseIsPulse_A	8235605	61	0	0
StayInStableSt	8235605	4136	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8235605	2879	0	0
gen_low_level_sva.LowLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	131	0	0
T6	3067	2	0	0
T7	3625	6	0	0
T8	22766	0	0	0
T9	608	2	0	0
T12	0	4	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	2	0	0
T24	759	0	0	0
T25	633	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T49	658	0	0	0
T71	0	2	0	0
T187	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	10871	0	0
T6	3067	75	0	0
T7	3625	258	0	0
T8	22766	0	0	0
T9	608	23	0	0
T12	0	66	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	47	0	0
T24	759	0	0	0
T25	633	0	0	0
T35	0	47	0	0
T36	0	83	0	0
T37	0	13	0	0
T49	658	0	0	0
T71	0	13	0	0
T187	0	26	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597914	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	660	0	0
T7	3625	1214	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	3	0	0
T88	791	0	0	0
T168	1067	0	0	0
T181	0	1	0	0
T200	489	1	0	0
T201	0	1	0	0
T202	5175	0	0	0
T203	525	0	0	0
T204	2046	0	0	0
T205	3070	0	0	0
T206	524	0	0	0
T207	526	0	0	0
T208	451	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	4223	0	0
T6	3067	243	0	0
T7	3625	112	0	0
T8	22766	0	0	0
T9	608	88	0	0
T12	0	47	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	98	0	0
T24	759	0	0	0
T25	633	0	0	0
T35	0	38	0	0
T36	0	131	0	0
T37	0	37	0	0
T49	658	0	0	0
T71	0	37	0	0
T187	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	61	0	0
T6	3067	1	0	0
T7	3625	3	0	0
T8	22766	0	0	0
T9	608	1	0	0
T12	0	2	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T71	0	1	0	0
T187	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7532871	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	223	0	0
T7	3625	499	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7535180	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	227	0	0
T7	3625	503	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	67	0	0
T6	3067	1	0	0
T7	3625	3	0	0
T8	22766	0	0	0
T9	608	1	0	0
T12	0	2	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T71	0	1	0	0
T187	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	64	0	0
T6	3067	1	0	0
T7	3625	3	0	0
T8	22766	0	0	0
T9	608	1	0	0
T12	0	2	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T71	0	1	0	0
T187	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	61	0	0
T6	3067	1	0	0
T7	3625	3	0	0
T8	22766	0	0	0
T9	608	1	0	0
T12	0	2	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T71	0	1	0	0
T187	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	61	0	0
T6	3067	1	0	0
T7	3625	3	0	0
T8	22766	0	0	0
T9	608	1	0	0
T12	0	2	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T71	0	1	0	0
T187	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	4136	0	0
T6	3067	242	0	0
T7	3625	108	0	0
T8	22766	0	0	0
T9	608	86	0	0
T12	0	44	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	97	0	0
T24	759	0	0	0
T25	633	0	0	0
T35	0	36	0	0
T36	0	130	0	0
T37	0	35	0	0
T49	658	0	0	0
T71	0	35	0	0
T187	0	8	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	2879	0	0
T1	1121	0	0	0
T2	33179	0	0	0
T3	1059	2	0	0
T4	494	6	0	0
T5	492	4	0	0
T6	3067	8	0	0
T7	3625	20	0	0
T9	0	1	0	0
T13	5766	0	0	0
T14	490	6	0	0
T15	408	0	0	0
T22	0	8	0	0
T23	0	3	0	0
T49	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	34	0	0
T6	3067	1	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T36	0	1	0	0
T49	658	0	0	0
T74	0	1	0	0
T80	0	1	0	0
T87	0	1	0	0
T142	0	1	0	0
T187	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T9
1	0	Covered	T4,T1,T5
1	1	Covered	T3,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T9
0	1	Covered	T87,T81,T209
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T9
0	1	Covered	T3,T34,T187
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T9
1	-	Covered	T3,T34,T187

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T9
DetectSt	168	Covered	T3,T6,T9
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T6,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T9
DebounceSt->IdleSt	163	Covered	T78,T81,T178
DetectSt->IdleSt	186	Covered	T87,T81,T209
DetectSt->StableSt	191	Covered	T3,T6,T9
IdleSt->DebounceSt	148	Covered	T3,T6,T9
StableSt->IdleSt	206	Covered	T3,T6,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T9
0	1	Covered	T3,T6,T9
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T9
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T81,T178,T109
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T9
DetectSt	-	-	-	-	1	-	-	Covered	T87,T81,T209
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T34,T187
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	132	0	0
CntIncr_A	8235605	61013	0	0
CntNoWrap_A	8235605	7597913	0	0
DetectStDropOut_A	8235605	3	0	0
DetectedOut_A	8235605	32032	0	0
DetectedPulseOut_A	8235605	61	0	0
DisabledIdleSt_A	8235605	7496414	0	0
DisabledNoDetection_A	8235605	7498728	0	0
EnterDebounceSt_A	8235605	68	0	0
EnterDetectSt_A	8235605	64	0	0
EnterStableSt_A	8235605	61	0	0
PulseIsPulse_A	8235605	61	0	0
StayInStableSt	8235605	31944	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	132	0	0
T3	1059	2	0	0
T6	3067	2	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	2	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T31	0	2	0	0
T34	0	4	0	0
T36	0	4	0	0
T49	658	0	0	0
T74	0	2	0	0
T187	0	4	0	0
T196	0	4	0	0
T210	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	61013	0	0
T3	1059	74	0	0
T6	3067	44	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	23	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T31	0	34	0	0
T34	0	92	0	0
T36	0	166	0	0
T49	658	0	0	0
T74	0	87	0	0
T187	0	26	0	0
T196	0	74	0	0
T210	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597913	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	656	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	660	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	3	0	0
T81	0	1	0	0
T87	600	1	0	0
T131	1301	0	0	0
T209	0	1	0	0
T211	14211	0	0	0
T212	28836	0	0	0
T213	8979	0	0	0
T214	407	0	0	0
T215	7066	0	0	0
T216	5712	0	0	0
T217	19660	0	0	0
T218	613	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	32032	0	0
T3	1059	44	0	0
T6	3067	38	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	41	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T31	0	76	0	0
T34	0	43	0	0
T36	0	87	0	0
T49	658	0	0	0
T74	0	327	0	0
T187	0	10	0	0
T196	0	87	0	0
T210	0	61	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	61	0	0
T3	1059	1	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T31	0	1	0	0
T34	0	2	0	0
T36	0	2	0	0
T49	658	0	0	0
T74	0	1	0	0
T187	0	2	0	0
T196	0	2	0	0
T210	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7496414	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	4	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	531	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7498728	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	4	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	535	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	68	0	0
T3	1059	1	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T31	0	1	0	0
T34	0	2	0	0
T36	0	2	0	0
T49	658	0	0	0
T74	0	1	0	0
T187	0	2	0	0
T196	0	2	0	0
T210	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	64	0	0
T3	1059	1	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T31	0	1	0	0
T34	0	2	0	0
T36	0	2	0	0
T49	658	0	0	0
T74	0	1	0	0
T187	0	2	0	0
T196	0	2	0	0
T210	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	61	0	0
T3	1059	1	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T31	0	1	0	0
T34	0	2	0	0
T36	0	2	0	0
T49	658	0	0	0
T74	0	1	0	0
T187	0	2	0	0
T196	0	2	0	0
T210	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	61	0	0
T3	1059	1	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T31	0	1	0	0
T34	0	2	0	0
T36	0	2	0	0
T49	658	0	0	0
T74	0	1	0	0
T187	0	2	0	0
T196	0	2	0	0
T210	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	31944	0	0
T3	1059	43	0	0
T6	3067	36	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	39	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T31	0	74	0	0
T34	0	41	0	0
T36	0	84	0	0
T49	658	0	0	0
T74	0	325	0	0
T187	0	8	0	0
T196	0	84	0	0
T210	0	60	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	33	0	0
T3	1059	1	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T34	0	2	0	0
T36	0	1	0	0
T49	658	0	0	0
T81	0	1	0	0
T142	0	2	0	0
T166	0	1	0	0
T187	0	2	0	0
T196	0	1	0	0
T210	0	1	0	0
T219	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T6,T7,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T34
1	0	Covered	T4,T1,T5
1	1	Covered	T6,T7,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T34
0	1	Covered	T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T34
0	1	Covered	T6,T34,T187
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T34
1	-	Covered	T6,T34,T187

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T34
DetectSt	168	Covered	T6,T7,T34
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T6,T7,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T34
DebounceSt->IdleSt	163	Covered	T78
DetectSt->IdleSt	186	Covered	T81
DetectSt->StableSt	191	Covered	T6,T7,T34
IdleSt->DebounceSt	148	Covered	T6,T7,T34
StableSt->IdleSt	206	Covered	T6,T7,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T7,T34
0	1	Covered	T6,T7,T34
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T34
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T34
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T34
DetectSt	-	-	-	-	1	-	-	Covered	T81
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T34,T187
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	87	0	0
CntIncr_A	8235605	83125	0	0
CntNoWrap_A	8235605	7597958	0	0
DetectStDropOut_A	8235605	1	0	0
DetectedOut_A	8235605	59589	0	0
DetectedPulseOut_A	8235605	42	0	0
DisabledIdleSt_A	8235605	7327561	0	0
DisabledNoDetection_A	8235605	7329874	0	0
EnterDebounceSt_A	8235605	44	0	0
EnterDetectSt_A	8235605	43	0	0
EnterStableSt_A	8235605	42	0	0
PulseIsPulse_A	8235605	42	0	0
StayInStableSt	8235605	59526	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8235605	6462	0	0
gen_low_level_sva.LowLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	87	0	0
T6	3067	4	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	2	0	0
T24	759	0	0	0
T25	633	0	0	0
T34	0	4	0	0
T49	658	0	0	0
T78	0	1	0	0
T87	0	2	0	0
T187	0	4	0	0
T188	0	2	0	0
T196	0	2	0	0
T210	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	83125	0	0
T6	3067	150	0	0
T7	3625	86	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	47	0	0
T24	759	0	0	0
T25	633	0	0	0
T34	0	92	0	0
T49	658	0	0	0
T78	0	21	0	0
T87	0	24	0	0
T187	0	26	0	0
T188	0	71	0	0
T196	0	37	0	0
T210	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597958	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	658	0	0
T7	3625	1218	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	1	0	0
T81	29840	1	0	0
T132	2585	0	0	0
T166	555	0	0	0
T189	45401	0	0	0
T190	402	0	0	0
T191	423	0	0	0
T192	526	0	0	0
T193	499	0	0	0
T194	817	0	0	0
T195	483	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	59589	0	0
T6	3067	81	0	0
T7	3625	128	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	42	0	0
T24	759	0	0	0
T25	633	0	0	0
T34	0	79	0	0
T49	658	0	0	0
T87	0	75	0	0
T165	0	41	0	0
T187	0	81	0	0
T188	0	38	0	0
T196	0	21	0	0
T210	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	42	0	0
T6	3067	2	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T34	0	2	0	0
T49	658	0	0	0
T87	0	1	0	0
T165	0	1	0	0
T187	0	2	0	0
T188	0	1	0	0
T196	0	1	0	0
T210	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7327561	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	92	0	0
T7	3625	499	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7329874	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	95	0	0
T7	3625	503	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	44	0	0
T6	3067	2	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T34	0	2	0	0
T49	658	0	0	0
T78	0	1	0	0
T87	0	1	0	0
T187	0	2	0	0
T188	0	1	0	0
T196	0	1	0	0
T210	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	43	0	0
T6	3067	2	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T34	0	2	0	0
T49	658	0	0	0
T87	0	1	0	0
T165	0	1	0	0
T187	0	2	0	0
T188	0	1	0	0
T196	0	1	0	0
T210	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	42	0	0
T6	3067	2	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T34	0	2	0	0
T49	658	0	0	0
T87	0	1	0	0
T165	0	1	0	0
T187	0	2	0	0
T188	0	1	0	0
T196	0	1	0	0
T210	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	42	0	0
T6	3067	2	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T34	0	2	0	0
T49	658	0	0	0
T87	0	1	0	0
T165	0	1	0	0
T187	0	2	0	0
T188	0	1	0	0
T196	0	1	0	0
T210	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	59526	0	0
T6	3067	78	0	0
T7	3625	126	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	40	0	0
T24	759	0	0	0
T25	633	0	0	0
T34	0	76	0	0
T49	658	0	0	0
T87	0	74	0	0
T165	0	39	0	0
T187	0	78	0	0
T188	0	36	0	0
T196	0	20	0	0
T210	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6462	0	0
T1	1121	5	0	0
T2	33179	13	0	0
T3	1059	1	0	0
T4	494	11	0	0
T5	492	8	0	0
T6	3067	12	0	0
T7	3625	17	0	0
T13	5766	22	0	0
T14	490	9	0	0
T15	408	0	0	0
T16	0	28	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	20	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T34	0	1	0	0
T49	658	0	0	0
T81	0	1	0	0
T87	0	1	0	0
T178	0	1	0	0
T187	0	1	0	0
T196	0	1	0	0
T219	0	1	0	0
T220	0	2	0	0
T221	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T5,T2
1	1	Covered	T4,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T6,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T9
1	0	Covered	T4,T5,T2
1	1	Covered	T6,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T9
0	1	Covered	T7,T31,T219
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T9
0	1	Covered	T6,T7,T11
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T9
1	-	Covered	T6,T7,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T9
DetectSt	168	Covered	T6,T7,T9
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T6,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T9
DebounceSt->IdleSt	163	Covered	T34,T37,T78
DetectSt->IdleSt	186	Covered	T7,T31,T219
DetectSt->StableSt	191	Covered	T6,T7,T9
IdleSt->DebounceSt	148	Covered	T6,T7,T9
StableSt->IdleSt	206	Covered	T6,T7,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T7,T9
0	1	Covered	T6,T7,T9
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T9
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T37,T222
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T7,T31,T219
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T7,T11
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	138	0	0
CntIncr_A	8235605	56408	0	0
CntNoWrap_A	8235605	7597907	0	0
DetectStDropOut_A	8235605	4	0	0
DetectedOut_A	8235605	17828	0	0
DetectedPulseOut_A	8235605	62	0	0
DisabledIdleSt_A	8235605	7290473	0	0
DisabledNoDetection_A	8235605	7292783	0	0
EnterDebounceSt_A	8235605	72	0	0
EnterDetectSt_A	8235605	66	0	0
EnterStableSt_A	8235605	62	0	0
PulseIsPulse_A	8235605	62	0	0
StayInStableSt	8235605	17741	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	138	0	0
T6	3067	2	0	0
T7	3625	4	0	0
T8	22766	0	0	0
T9	608	2	0	0
T11	0	2	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	4	0	0
T34	0	3	0	0
T36	0	2	0	0
T37	0	1	0	0
T49	658	0	0	0
T71	0	2	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	56408	0	0
T6	3067	75	0	0
T7	3625	172	0	0
T8	22766	0	0	0
T9	608	23	0	0
T11	0	61	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	98	0	0
T34	0	92	0	0
T36	0	83	0	0
T37	0	13	0	0
T49	658	0	0	0
T71	0	13	0	0
T187	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597907	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	660	0	0
T7	3625	1216	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	4	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T31	0	1	0	0
T49	658	0	0	0
T219	0	1	0	0
T223	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	17828	0	0
T6	3067	40	0	0
T7	3625	29	0	0
T8	22766	0	0	0
T9	608	176	0	0
T11	0	23	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	65	0	0
T34	0	40	0	0
T36	0	373	0	0
T49	658	0	0	0
T71	0	5	0	0
T80	0	12508	0	0
T187	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	62	0	0
T6	3067	1	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	1	0	0
T11	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	1	0	0
T49	658	0	0	0
T71	0	1	0	0
T80	0	1	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7290473	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	223	0	0
T7	3625	499	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7292783	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	227	0	0
T7	3625	503	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	72	0	0
T6	3067	1	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	1	0	0
T11	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T71	0	1	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	66	0	0
T6	3067	1	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	1	0	0
T11	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T31	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	1	0	0
T49	658	0	0	0
T71	0	1	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	62	0	0
T6	3067	1	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	1	0	0
T11	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	1	0	0
T49	658	0	0	0
T71	0	1	0	0
T80	0	1	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	62	0	0
T6	3067	1	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	1	0	0
T11	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	1	0	0
T49	658	0	0	0
T71	0	1	0	0
T80	0	1	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	17741	0	0
T6	3067	39	0	0
T7	3625	28	0	0
T8	22766	0	0	0
T9	608	174	0	0
T11	0	22	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	62	0	0
T34	0	38	0	0
T36	0	371	0	0
T49	658	0	0	0
T71	0	4	0	0
T80	0	12506	0	0
T187	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	36	0	0
T6	3067	1	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	1	0	0
T49	658	0	0	0
T71	0	1	0	0
T81	0	2	0	0
T142	0	1	0	0
T167	0	1	0	0
T187	0	1	0	0
T219	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T6,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T9
1	0	Covered	T4,T5,T2
1	1	Covered	T6,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T11
0	1	Covered	T7,T34,T33
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T11
1	-	Covered	T7,T34,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T11
DetectSt	168	Covered	T6,T7,T11
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T6,T7,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T11
DebounceSt->IdleSt	163	Covered	T78,T224,T181
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6,T7,T11
IdleSt->DebounceSt	148	Covered	T6,T7,T11
StableSt->IdleSt	206	Covered	T6,T7,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T7,T11
0	1	Covered	T6,T7,T11
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T11
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T224,T181
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T34,T33
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	93	0	0
CntIncr_A	8235605	89166	0	0
CntNoWrap_A	8235605	7597952	0	0
DetectStDropOut_A	8235605	0	0	0
DetectedOut_A	8235605	96671	0	0
DetectedPulseOut_A	8235605	45	0	0
DisabledIdleSt_A	8235605	7047930	0	0
DisabledNoDetection_A	8235605	7050241	0	0
EnterDebounceSt_A	8235605	48	0	0
EnterDetectSt_A	8235605	45	0	0
EnterStableSt_A	8235605	45	0	0
PulseIsPulse_A	8235605	45	0	0
StayInStableSt	8235605	96603	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8235605	6124	0	0
gen_low_level_sva.LowLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	93	0	0
T6	3067	4	0	0
T7	3625	4	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T31	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T37	0	2	0	0
T49	658	0	0	0
T74	0	2	0	0
T142	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	89166	0	0
T6	3067	119	0	0
T7	3625	172	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	61	0	0
T12	0	33	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T31	0	34	0	0
T33	0	49	0	0
T34	0	46	0	0
T37	0	13	0	0
T49	658	0	0	0
T74	0	87	0	0
T142	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597952	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	658	0	0
T7	3625	1216	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	96671	0	0
T6	3067	161	0	0
T7	3625	341	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	239	0	0
T12	0	38	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T31	0	41	0	0
T33	0	126	0	0
T34	0	129	0	0
T37	0	38	0	0
T49	658	0	0	0
T74	0	39	0	0
T142	0	123	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	45	0	0
T6	3067	2	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T74	0	1	0	0
T142	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7047930	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	92	0	0
T7	3625	499	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7050241	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	95	0	0
T7	3625	503	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	48	0	0
T6	3067	2	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T74	0	1	0	0
T142	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	45	0	0
T6	3067	2	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T74	0	1	0	0
T142	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	45	0	0
T6	3067	2	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T74	0	1	0	0
T142	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	45	0	0
T6	3067	2	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T49	658	0	0	0
T74	0	1	0	0
T142	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	96603	0	0
T6	3067	157	0	0
T7	3625	338	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	237	0	0
T12	0	36	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T31	0	39	0	0
T33	0	125	0	0
T34	0	128	0	0
T37	0	36	0	0
T49	658	0	0	0
T74	0	38	0	0
T142	0	122	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6124	0	0
T1	1121	0	0	0
T2	33179	9	0	0
T3	1059	1	0	0
T4	494	7	0	0
T5	492	5	0	0
T6	3067	12	0	0
T7	3625	17	0	0
T8	0	30	0	0
T13	5766	24	0	0
T14	490	7	0	0
T15	408	0	0	0
T16	0	30	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	21	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T22	503	0	0	0
T23	505	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T49	658	0	0	0
T74	0	1	0	0
T81	0	2	0	0
T142	0	1	0	0
T163	0	1	0	0
T168	0	1	0	0
T178	0	2	0	0
T219	0	1	0	0