Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T5,T2
1	1	Covered	T4,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T11,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T6,T11,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T11,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T21
1	0	Covered	T4,T5,T2
1	1	Covered	T6,T11,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T21
0	1	Covered	T135
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T21
0	1	Covered	T6,T71,T142
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T11,T21
1	-	Covered	T6,T71,T142

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T11,T21
DetectSt	168	Covered	T6,T11,T21
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T6,T11,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T11,T21
DebounceSt->IdleSt	163	Covered	T78,T220,T81
DetectSt->IdleSt	186	Covered	T135
DetectSt->StableSt	191	Covered	T6,T11,T21
IdleSt->DebounceSt	148	Covered	T6,T11,T21
StableSt->IdleSt	206	Covered	T6,T21,T71

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T11,T21
0	1	Covered	T6,T11,T21
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T11,T21
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T11,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T11,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T220,T81,T224
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T11,T21
DetectSt	-	-	-	-	1	-	-	Covered	T135
DetectSt	-	-	-	-	0	1	-	Covered	T6,T11,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T71,T142
StableSt	-	-	-	-	-	-	0	Covered	T6,T11,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	117	0	0
CntIncr_A	8235605	170325	0	0
CntNoWrap_A	8235605	7597928	0	0
DetectStDropOut_A	8235605	2	0	0
DetectedOut_A	8235605	19141	0	0
DetectedPulseOut_A	8235605	54	0	0
DisabledIdleSt_A	8235605	7172256	0	0
DisabledNoDetection_A	8235605	7174568	0	0
EnterDebounceSt_A	8235605	61	0	0
EnterDetectSt_A	8235605	56	0	0
EnterStableSt_A	8235605	54	0	0
PulseIsPulse_A	8235605	54	0	0
StayInStableSt	8235605	19059	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	117	0	0
T6	3067	4	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	2	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	2	0	0
T24	759	0	0	0
T25	633	0	0	0
T49	658	0	0	0
T71	0	2	0	0
T78	0	1	0	0
T81	0	5	0	0
T142	0	4	0	0
T163	0	2	0	0
T166	0	2	0	0
T220	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	170325	0	0
T6	3067	119	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	61	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	47	0	0
T24	759	0	0	0
T25	633	0	0	0
T49	658	0	0	0
T71	0	13	0	0
T78	0	19	0	0
T81	0	132	0	0
T142	0	94	0	0
T163	0	17	0	0
T166	0	19	0	0
T220	0	121086	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597928	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	658	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	2	0	0
T135	13922	2	0	0
T225	732	0	0	0
T226	417	0	0	0
T227	505	0	0	0
T228	35395	0	0	0
T229	500	0	0	0
T230	615	0	0	0
T231	506	0	0	0
T232	5715	0	0	0
T233	41233	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	19141	0	0
T6	3067	205	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	136	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	183	0	0
T24	759	0	0	0
T25	633	0	0	0
T49	658	0	0	0
T71	0	7	0	0
T81	0	92	0	0
T142	0	81	0	0
T163	0	68	0	0
T166	0	125	0	0
T220	0	14162	0	0
T234	0	53	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	54	0	0
T6	3067	2	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T49	658	0	0	0
T71	0	1	0	0
T81	0	2	0	0
T142	0	2	0	0
T163	0	1	0	0
T166	0	1	0	0
T220	0	2	0	0
T234	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7172256	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	92	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7174568	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	95	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	61	0	0
T6	3067	2	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T49	658	0	0	0
T71	0	1	0	0
T78	0	1	0	0
T81	0	3	0	0
T142	0	2	0	0
T163	0	1	0	0
T166	0	1	0	0
T220	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	56	0	0
T6	3067	2	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T49	658	0	0	0
T71	0	1	0	0
T81	0	2	0	0
T142	0	2	0	0
T163	0	1	0	0
T166	0	1	0	0
T220	0	2	0	0
T234	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	54	0	0
T6	3067	2	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T49	658	0	0	0
T71	0	1	0	0
T81	0	2	0	0
T142	0	2	0	0
T163	0	1	0	0
T166	0	1	0	0
T220	0	2	0	0
T234	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	54	0	0
T6	3067	2	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T25	633	0	0	0
T49	658	0	0	0
T71	0	1	0	0
T81	0	2	0	0
T142	0	2	0	0
T163	0	1	0	0
T166	0	1	0	0
T220	0	2	0	0
T234	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	19059	0	0
T6	3067	202	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T11	0	134	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	181	0	0
T24	759	0	0	0
T25	633	0	0	0
T49	658	0	0	0
T71	0	6	0	0
T81	0	89	0	0
T142	0	78	0	0
T163	0	66	0	0
T166	0	123	0	0
T220	0	14159	0	0
T234	0	51	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	25	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T49	658	0	0	0
T71	0	1	0	0
T81	0	1	0	0
T142	0	1	0	0
T198	0	1	0	0
T205	0	2	0	0
T219	0	1	0	0
T220	0	1	0	0
T224	0	1	0	0
T235	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T35,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T35,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T35,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T11
1	0	Covered	T4,T5,T2
1	1	Covered	T35,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Covered	T74,T220,T168
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T36,T37
1	-	Covered	T74,T220,T168

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T36,T37
DetectSt	168	Covered	T35,T36,T37
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T35,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T36,T37
DebounceSt->IdleSt	163	Covered	T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T35,T36,T37
IdleSt->DebounceSt	148	Covered	T35,T36,T37
StableSt->IdleSt	206	Covered	T37,T71,T74

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T35,T36,T37
0	1	Covered	T35,T36,T37
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T37
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T36,T37
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T74,T220,T168
StableSt	-	-	-	-	-	-	0	Covered	T35,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	61	0	0
CntIncr_A	8235605	83589	0	0
CntNoWrap_A	8235605	7597984	0	0
DetectStDropOut_A	8235605	0	0	0
DetectedOut_A	8235605	44947	0	0
DetectedPulseOut_A	8235605	30	0	0
DisabledIdleSt_A	8235605	7245535	0	0
DisabledNoDetection_A	8235605	7247851	0	0
EnterDebounceSt_A	8235605	31	0	0
EnterDetectSt_A	8235605	30	0	0
EnterStableSt_A	8235605	30	0	0
PulseIsPulse_A	8235605	30	0	0
StayInStableSt	8235605	44903	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8235605	6053	0	0
gen_low_level_sva.LowLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	61	0	0
T35	543	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T55	13813	0	0	0
T56	142786	0	0	0
T57	2195	0	0	0
T71	0	2	0	0
T74	0	2	0	0
T78	0	1	0	0
T95	8533	0	0	0
T127	17287	0	0	0
T168	0	4	0	0
T198	0	2	0	0
T205	0	4	0	0
T220	0	4	0	0
T236	547	0	0	0
T237	504	0	0	0
T238	4415	0	0	0
T239	502	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	83589	0	0
T35	543	47	0	0
T36	0	83	0	0
T37	0	13	0	0
T55	13813	0	0	0
T56	142786	0	0	0
T57	2195	0	0	0
T71	0	34	0	0
T74	0	87	0	0
T78	0	21	0	0
T95	8533	0	0	0
T127	17287	0	0	0
T168	0	140	0	0
T198	0	17	0	0
T205	0	158	0	0
T220	0	80724	0	0
T236	547	0	0	0
T237	504	0	0	0
T238	4415	0	0	0
T239	502	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597984	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	44947	0	0
T35	543	39	0	0
T36	0	158	0	0
T37	0	37	0	0
T55	13813	0	0	0
T56	142786	0	0	0
T57	2195	0	0	0
T71	0	38	0	0
T74	0	41	0	0
T95	8533	0	0	0
T127	17287	0	0	0
T168	0	300	0	0
T198	0	40	0	0
T201	0	1	0	0
T205	0	55	0	0
T220	0	42402	0	0
T236	547	0	0	0
T237	504	0	0	0
T238	4415	0	0	0
T239	502	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	30	0	0
T35	543	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T55	13813	0	0	0
T56	142786	0	0	0
T57	2195	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T95	8533	0	0	0
T127	17287	0	0	0
T168	0	2	0	0
T198	0	1	0	0
T201	0	1	0	0
T205	0	2	0	0
T220	0	2	0	0
T236	547	0	0	0
T237	504	0	0	0
T238	4415	0	0	0
T239	502	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7245535	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	531	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7247851	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	535	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	31	0	0
T35	543	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T55	13813	0	0	0
T56	142786	0	0	0
T57	2195	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T78	0	1	0	0
T95	8533	0	0	0
T127	17287	0	0	0
T168	0	2	0	0
T198	0	1	0	0
T205	0	2	0	0
T220	0	2	0	0
T236	547	0	0	0
T237	504	0	0	0
T238	4415	0	0	0
T239	502	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	30	0	0
T35	543	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T55	13813	0	0	0
T56	142786	0	0	0
T57	2195	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T95	8533	0	0	0
T127	17287	0	0	0
T168	0	2	0	0
T198	0	1	0	0
T201	0	1	0	0
T205	0	2	0	0
T220	0	2	0	0
T236	547	0	0	0
T237	504	0	0	0
T238	4415	0	0	0
T239	502	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	30	0	0
T35	543	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T55	13813	0	0	0
T56	142786	0	0	0
T57	2195	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T95	8533	0	0	0
T127	17287	0	0	0
T168	0	2	0	0
T198	0	1	0	0
T201	0	1	0	0
T205	0	2	0	0
T220	0	2	0	0
T236	547	0	0	0
T237	504	0	0	0
T238	4415	0	0	0
T239	502	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	30	0	0
T35	543	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T55	13813	0	0	0
T56	142786	0	0	0
T57	2195	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T95	8533	0	0	0
T127	17287	0	0	0
T168	0	2	0	0
T198	0	1	0	0
T201	0	1	0	0
T205	0	2	0	0
T220	0	2	0	0
T236	547	0	0	0
T237	504	0	0	0
T238	4415	0	0	0
T239	502	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	44903	0	0
T35	543	37	0	0
T36	0	156	0	0
T37	0	35	0	0
T55	13813	0	0	0
T56	142786	0	0	0
T57	2195	0	0	0
T71	0	36	0	0
T74	0	40	0	0
T95	8533	0	0	0
T127	17287	0	0	0
T168	0	297	0	0
T198	0	39	0	0
T199	0	83	0	0
T205	0	52	0	0
T220	0	42400	0	0
T236	547	0	0	0
T237	504	0	0	0
T238	4415	0	0	0
T239	502	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6053	0	0
T1	1121	0	0	0
T2	33179	11	0	0
T3	1059	0	0	0
T4	494	4	0	0
T5	492	8	0	0
T6	3067	11	0	0
T7	3625	16	0	0
T8	0	31	0	0
T13	5766	28	0	0
T14	490	8	0	0
T15	408	1	0	0
T16	0	35	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	15	0	0
T74	5810	1	0	0
T90	0	1	0	0
T136	31989	0	0	0
T137	416	0	0	0
T138	455	0	0	0
T139	427	0	0	0
T140	16537	0	0	0
T141	523	0	0	0
T142	41705	0	0	0
T143	20758	0	0	0
T144	491	0	0	0
T168	0	1	0	0
T178	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T201	0	1	0	0
T205	0	1	0	0
T209	0	1	0	0
T220	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T5,T2
1	1	Covered	T4,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T9
1	0	Covered	T4,T5,T2
1	1	Covered	T3,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T9
0	1	Covered	T205,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T9
0	1	Covered	T3,T6,T34
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T9
1	-	Covered	T3,T6,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T9
DetectSt	168	Covered	T3,T6,T9
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T6,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T9
DebounceSt->IdleSt	163	Covered	T35,T78,T197
DetectSt->IdleSt	186	Covered	T205,T90
DetectSt->StableSt	191	Covered	T3,T6,T9
IdleSt->DebounceSt	148	Covered	T3,T6,T9
StableSt->IdleSt	206	Covered	T3,T6,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T9
0	1	Covered	T3,T6,T9
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T9
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T197,T199
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T9
DetectSt	-	-	-	-	1	-	-	Covered	T205,T90
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T34
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	140	0	0
CntIncr_A	8235605	88314	0	0
CntNoWrap_A	8235605	7597905	0	0
DetectStDropOut_A	8235605	2	0	0
DetectedOut_A	8235605	12763	0	0
DetectedPulseOut_A	8235605	64	0	0
DisabledIdleSt_A	8235605	7446230	0	0
DisabledNoDetection_A	8235605	7448539	0	0
EnterDebounceSt_A	8235605	75	0	0
EnterDetectSt_A	8235605	66	0	0
EnterStableSt_A	8235605	64	0	0
PulseIsPulse_A	8235605	64	0	0
StayInStableSt	8235605	12673	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	140	0	0
T3	1059	4	0	0
T6	3067	4	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	2	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	2	0	0
T24	759	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	4	0	0
T49	658	0	0	0
T71	0	2	0	0
T80	0	6	0	0
T196	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	88314	0	0
T3	1059	148	0	0
T6	3067	119	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	23	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	47	0	0
T24	759	0	0	0
T34	0	46	0	0
T35	0	47	0	0
T36	0	166	0	0
T49	658	0	0	0
T71	0	13	0	0
T80	0	18639	0	0
T196	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597905	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	654	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	658	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	2	0	0
T90	0	1	0	0
T197	23590	0	0	0
T205	3070	1	0	0
T206	524	0	0	0
T207	526	0	0	0
T208	451	0	0	0
T240	422	0	0	0
T241	432	0	0	0
T242	402	0	0	0
T243	402	0	0	0
T244	3252	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	12763	0	0
T3	1059	167	0	0
T6	3067	126	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	88	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	187	0	0
T24	759	0	0	0
T34	0	86	0	0
T36	0	178	0	0
T49	658	0	0	0
T71	0	37	0	0
T74	0	112	0	0
T80	0	7180	0	0
T196	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	64	0	0
T3	1059	2	0	0
T6	3067	2	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T49	658	0	0	0
T71	0	1	0	0
T74	0	2	0	0
T80	0	3	0	0
T196	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7446230	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	4	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	92	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7448539	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	4	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	95	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	75	0	0
T3	1059	2	0	0
T6	3067	2	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	658	0	0	0
T71	0	1	0	0
T80	0	3	0	0
T196	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	66	0	0
T3	1059	2	0	0
T6	3067	2	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T49	658	0	0	0
T71	0	1	0	0
T74	0	2	0	0
T80	0	3	0	0
T196	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	64	0	0
T3	1059	2	0	0
T6	3067	2	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T49	658	0	0	0
T71	0	1	0	0
T74	0	2	0	0
T80	0	3	0	0
T196	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	64	0	0
T3	1059	2	0	0
T6	3067	2	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T49	658	0	0	0
T71	0	1	0	0
T74	0	2	0	0
T80	0	3	0	0
T196	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	12673	0	0
T3	1059	165	0	0
T6	3067	123	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	86	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	186	0	0
T24	759	0	0	0
T34	0	85	0	0
T36	0	175	0	0
T49	658	0	0	0
T71	0	35	0	0
T74	0	109	0	0
T80	0	7176	0	0
T196	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	37	0	0
T3	1059	2	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T49	658	0	0	0
T74	0	1	0	0
T80	0	2	0	0
T81	0	2	0	0
T163	0	4	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T7,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T7,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T7,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T9
1	0	Covered	T4,T5,T2
1	1	Covered	T3,T7,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T34
0	1	Covered	T80,T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T34
0	1	Covered	T3,T80,T74
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T34
1	-	Covered	T3,T80,T74

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T34
DetectSt	168	Covered	T3,T7,T34
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T7,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T34
DebounceSt->IdleSt	163	Covered	T78
DetectSt->IdleSt	186	Covered	T80,T166
DetectSt->StableSt	191	Covered	T3,T7,T34
IdleSt->DebounceSt	148	Covered	T3,T7,T34
StableSt->IdleSt	206	Covered	T3,T7,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T34
0	1	Covered	T3,T7,T34
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T34
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T34
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T34
DetectSt	-	-	-	-	1	-	-	Covered	T80,T166
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T80,T74
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	77	0	0
CntIncr_A	8235605	14321	0	0
CntNoWrap_A	8235605	7597968	0	0
DetectStDropOut_A	8235605	2	0	0
DetectedOut_A	8235605	2529	0	0
DetectedPulseOut_A	8235605	36	0	0
DisabledIdleSt_A	8235605	7454990	0	0
DisabledNoDetection_A	8235605	7457299	0	0
EnterDebounceSt_A	8235605	39	0	0
EnterDetectSt_A	8235605	38	0	0
EnterStableSt_A	8235605	36	0	0
PulseIsPulse_A	8235605	36	0	0
StayInStableSt	8235605	2475	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8235605	6082	0	0
gen_low_level_sva.LowLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	77	0	0
T3	1059	4	0	0
T6	3067	0	0	0
T7	3625	2	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	2	0	0
T24	759	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T49	658	0	0	0
T74	0	2	0	0
T78	0	1	0	0
T80	0	4	0	0
T114	0	2	0	0
T163	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	14321	0	0
T3	1059	148	0	0
T6	3067	0	0	0
T7	3625	86	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	47	0	0
T24	759	0	0	0
T33	0	49	0	0
T34	0	46	0	0
T49	658	0	0	0
T74	0	87	0	0
T78	0	19	0	0
T80	0	12426	0	0
T114	0	35	0	0
T163	0	116	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597968	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	654	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1218	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	2	0	0
T80	38701	1	0	0
T98	104669	0	0	0
T166	0	1	0	0
T210	35613	0	0	0
T245	402	0	0	0
T246	507	0	0	0
T247	5171	0	0	0
T248	48562	0	0	0
T249	10935	0	0	0
T250	502	0	0	0
T251	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	2529	0	0
T3	1059	183	0	0
T6	3067	0	0	0
T7	3625	40	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	42	0	0
T24	759	0	0	0
T33	0	41	0	0
T34	0	129	0	0
T49	658	0	0	0
T74	0	199	0	0
T80	0	42	0	0
T114	0	39	0	0
T163	0	89	0	0
T167	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	36	0	0
T3	1059	2	0	0
T6	3067	0	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T49	658	0	0	0
T74	0	1	0	0
T80	0	1	0	0
T114	0	1	0	0
T163	0	2	0	0
T167	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7454990	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	4	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	499	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7457299	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	4	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	503	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	39	0	0
T3	1059	2	0	0
T6	3067	0	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T49	658	0	0	0
T74	0	1	0	0
T78	0	1	0	0
T80	0	2	0	0
T114	0	1	0	0
T163	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	38	0	0
T3	1059	2	0	0
T6	3067	0	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T49	658	0	0	0
T74	0	1	0	0
T80	0	2	0	0
T114	0	1	0	0
T163	0	2	0	0
T166	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	36	0	0
T3	1059	2	0	0
T6	3067	0	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T49	658	0	0	0
T74	0	1	0	0
T80	0	1	0	0
T114	0	1	0	0
T163	0	2	0	0
T167	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	36	0	0
T3	1059	2	0	0
T6	3067	0	0	0
T7	3625	1	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	1	0	0
T24	759	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T49	658	0	0	0
T74	0	1	0	0
T80	0	1	0	0
T114	0	1	0	0
T163	0	2	0	0
T167	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	2475	0	0
T3	1059	180	0	0
T6	3067	0	0	0
T7	3625	38	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T21	0	40	0	0
T24	759	0	0	0
T33	0	39	0	0
T34	0	127	0	0
T49	658	0	0	0
T74	0	198	0	0
T80	0	41	0	0
T114	0	37	0	0
T163	0	86	0	0
T167	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6082	0	0
T1	1121	0	0	0
T2	33179	15	0	0
T3	1059	2	0	0
T4	494	9	0	0
T5	492	5	0	0
T6	3067	13	0	0
T7	3625	20	0	0
T8	0	34	0	0
T13	5766	27	0	0
T14	490	8	0	0
T15	408	0	0	0
T16	0	35	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	17	0	0
T3	1059	1	0	0
T6	3067	0	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T49	658	0	0	0
T74	0	1	0	0
T80	0	1	0	0
T163	0	1	0	0
T167	0	1	0	0
T197	0	1	0	0
T199	0	1	0	0
T205	0	1	0	0
T224	0	1	0	0
T252	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T11,T34,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T11,T34,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T11,T34,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T34,T33
1	0	Covered	T4,T1,T5
1	1	Covered	T11,T34,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T34,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T34,T33
0	1	Covered	T11,T34,T33
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T34,T33
1	-	Covered	T11,T34,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T34,T33
DetectSt	168	Covered	T11,T34,T33
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T11,T34,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T34,T33
DebounceSt->IdleSt	163	Covered	T114,T78,T181
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T34,T33
IdleSt->DebounceSt	148	Covered	T11,T34,T33
StableSt->IdleSt	206	Covered	T11,T34,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T34,T33
0	1	Covered	T11,T34,T33
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T34,T33
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T34,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T34,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T114,T181,T253
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T34,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T34,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T34,T33
StableSt	-	-	-	-	-	-	0	Covered	T11,T34,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	110	0	0
CntIncr_A	8235605	3937	0	0
CntNoWrap_A	8235605	7597935	0	0
DetectStDropOut_A	8235605	0	0	0
DetectedOut_A	8235605	6417	0	0
DetectedPulseOut_A	8235605	53	0	0
DisabledIdleSt_A	8235605	7409705	0	0
DisabledNoDetection_A	8235605	7412020	0	0
EnterDebounceSt_A	8235605	57	0	0
EnterDetectSt_A	8235605	53	0	0
EnterStableSt_A	8235605	53	0	0
PulseIsPulse_A	8235605	53	0	0
StayInStableSt	8235605	6338	0	0
gen_high_level_sva.HighLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	110	0	0
T11	794	4	0	0
T12	735	0	0	0
T17	1357	0	0	0
T33	0	4	0	0
T34	2071	4	0	0
T37	0	2	0	0
T38	8230	0	0	0
T52	641	0	0	0
T65	502	0	0	0
T66	515	0	0	0
T71	0	2	0	0
T74	0	2	0	0
T78	0	1	0	0
T114	0	1	0	0
T187	0	2	0	0
T254	0	2	0	0
T255	415	0	0	0
T256	4406	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	3937	0	0
T11	794	122	0	0
T12	735	0	0	0
T17	1357	0	0	0
T33	0	98	0	0
T34	2071	92	0	0
T37	0	13	0	0
T38	8230	0	0	0
T52	641	0	0	0
T65	502	0	0	0
T66	515	0	0	0
T71	0	34	0	0
T74	0	87	0	0
T78	0	20	0	0
T114	0	35	0	0
T187	0	13	0	0
T254	0	56	0	0
T255	415	0	0	0
T256	4406	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597935	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6417	0	0
T11	794	160	0	0
T12	735	0	0	0
T17	1357	0	0	0
T33	0	58	0	0
T34	2071	79	0	0
T37	0	41	0	0
T38	8230	0	0	0
T52	641	0	0	0
T65	502	0	0	0
T66	515	0	0	0
T71	0	39	0	0
T74	0	40	0	0
T165	0	41	0	0
T187	0	55	0	0
T192	0	73	0	0
T254	0	72	0	0
T255	415	0	0	0
T256	4406	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	53	0	0
T11	794	2	0	0
T12	735	0	0	0
T17	1357	0	0	0
T33	0	2	0	0
T34	2071	2	0	0
T37	0	1	0	0
T38	8230	0	0	0
T52	641	0	0	0
T65	502	0	0	0
T66	515	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T165	0	1	0	0
T187	0	1	0	0
T192	0	1	0	0
T254	0	1	0	0
T255	415	0	0	0
T256	4406	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7409705	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	662	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7412020	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	57	0	0
T11	794	2	0	0
T12	735	0	0	0
T17	1357	0	0	0
T33	0	2	0	0
T34	2071	2	0	0
T37	0	1	0	0
T38	8230	0	0	0
T52	641	0	0	0
T65	502	0	0	0
T66	515	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T78	0	1	0	0
T114	0	1	0	0
T187	0	1	0	0
T254	0	1	0	0
T255	415	0	0	0
T256	4406	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	53	0	0
T11	794	2	0	0
T12	735	0	0	0
T17	1357	0	0	0
T33	0	2	0	0
T34	2071	2	0	0
T37	0	1	0	0
T38	8230	0	0	0
T52	641	0	0	0
T65	502	0	0	0
T66	515	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T165	0	1	0	0
T187	0	1	0	0
T192	0	1	0	0
T254	0	1	0	0
T255	415	0	0	0
T256	4406	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	53	0	0
T11	794	2	0	0
T12	735	0	0	0
T17	1357	0	0	0
T33	0	2	0	0
T34	2071	2	0	0
T37	0	1	0	0
T38	8230	0	0	0
T52	641	0	0	0
T65	502	0	0	0
T66	515	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T165	0	1	0	0
T187	0	1	0	0
T192	0	1	0	0
T254	0	1	0	0
T255	415	0	0	0
T256	4406	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	53	0	0
T11	794	2	0	0
T12	735	0	0	0
T17	1357	0	0	0
T33	0	2	0	0
T34	2071	2	0	0
T37	0	1	0	0
T38	8230	0	0	0
T52	641	0	0	0
T65	502	0	0	0
T66	515	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T165	0	1	0	0
T187	0	1	0	0
T192	0	1	0	0
T254	0	1	0	0
T255	415	0	0	0
T256	4406	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6338	0	0
T11	794	157	0	0
T12	735	0	0	0
T17	1357	0	0	0
T33	0	56	0	0
T34	2071	76	0	0
T37	0	39	0	0
T38	8230	0	0	0
T52	641	0	0	0
T65	502	0	0	0
T66	515	0	0	0
T71	0	37	0	0
T74	0	39	0	0
T165	0	39	0	0
T187	0	53	0	0
T192	0	71	0	0
T254	0	70	0	0
T255	415	0	0	0
T256	4406	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	26	0	0
T11	794	1	0	0
T12	735	0	0	0
T17	1357	0	0	0
T33	0	2	0	0
T34	2071	1	0	0
T38	8230	0	0	0
T52	641	0	0	0
T65	502	0	0	0
T66	515	0	0	0
T74	0	1	0	0
T168	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0
T219	0	1	0	0
T224	0	2	0	0
T252	0	1	0	0
T255	415	0	0	0
T256	4406	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T12,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T6,T12,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T12,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T12
1	0	Covered	T4,T1,T5
1	1	Covered	T6,T12,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T12,T33
0	1	Covered	T257
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T12,T33
0	1	Covered	T33,T36,T142
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T12,T33
1	-	Covered	T33,T36,T142

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T12,T33
DetectSt	168	Covered	T6,T12,T33
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T6,T12,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T12,T33
DebounceSt->IdleSt	163	Covered	T78
DetectSt->IdleSt	186	Covered	T257
DetectSt->StableSt	191	Covered	T6,T12,T33
IdleSt->DebounceSt	148	Covered	T6,T12,T33
StableSt->IdleSt	206	Covered	T6,T33,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T12,T33
0	1	Covered	T6,T12,T33
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T12,T33
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T12,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T12,T33
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T12,T33
DetectSt	-	-	-	-	1	-	-	Covered	T257
DetectSt	-	-	-	-	0	1	-	Covered	T6,T12,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T36,T142
StableSt	-	-	-	-	-	-	0	Covered	T6,T12,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8235605	83	0	0
CntIncr_A	8235605	43583	0	0
CntNoWrap_A	8235605	7597962	0	0
DetectStDropOut_A	8235605	1	0	0
DetectedOut_A	8235605	4850	0	0
DetectedPulseOut_A	8235605	40	0	0
DisabledIdleSt_A	8235605	7080930	0	0
DisabledNoDetection_A	8235605	7083245	0	0
EnterDebounceSt_A	8235605	42	0	0
EnterDetectSt_A	8235605	41	0	0
EnterStableSt_A	8235605	40	0	0
PulseIsPulse_A	8235605	40	0	0
StayInStableSt	8235605	4786	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8235605	6784	0	0
gen_low_level_sva.LowLevelEvent_A	8235605	7600407	0	0
gen_not_sticky_sva.StableStDropOut_A	8235605	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	83	0	0
T6	3067	2	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	2	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	4	0	0
T35	0	2	0	0
T36	0	4	0	0
T49	658	0	0	0
T74	0	2	0	0
T78	0	1	0	0
T114	0	2	0	0
T142	0	4	0	0
T196	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	43583	0	0
T6	3067	44	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	33	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	98	0	0
T35	0	47	0	0
T36	0	166	0	0
T49	658	0	0	0
T74	0	87	0	0
T78	0	20	0	0
T114	0	35	0	0
T142	0	94	0	0
T196	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7597962	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	660	0	0
T7	3625	1220	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	1	0	0
T108	23071	0	0	0
T179	167932	0	0	0
T257	788	1	0	0
T258	761	0	0	0
T259	496	0	0	0
T260	19210	0	0	0
T261	4656	0	0	0
T262	640	0	0	0
T263	5125	0	0	0
T264	676	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	4850	0	0
T6	3067	38	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	192	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	84	0	0
T35	0	39	0	0
T36	0	88	0	0
T49	658	0	0	0
T74	0	200	0	0
T114	0	39	0	0
T142	0	172	0	0
T163	0	79	0	0
T196	0	102	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	40	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	658	0	0	0
T74	0	1	0	0
T114	0	1	0	0
T142	0	2	0	0
T163	0	2	0	0
T196	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7080930	0	0
T1	1121	720	0	0
T2	33179	32687	0	0
T3	1059	658	0	0
T4	494	93	0	0
T5	492	91	0	0
T6	3067	531	0	0
T7	3625	499	0	0
T13	5766	5365	0	0
T14	490	89	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7083245	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	535	0	0
T7	3625	503	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	42	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	658	0	0	0
T74	0	1	0	0
T78	0	1	0	0
T114	0	1	0	0
T142	0	2	0	0
T196	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	41	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	658	0	0	0
T74	0	1	0	0
T114	0	1	0	0
T142	0	2	0	0
T163	0	2	0	0
T196	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	40	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	658	0	0	0
T74	0	1	0	0
T114	0	1	0	0
T142	0	2	0	0
T163	0	2	0	0
T196	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	40	0	0
T6	3067	1	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	1	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T49	658	0	0	0
T74	0	1	0	0
T114	0	1	0	0
T142	0	2	0	0
T163	0	2	0	0
T196	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	4786	0	0
T6	3067	36	0	0
T7	3625	0	0	0
T8	22766	0	0	0
T9	608	0	0	0
T12	0	190	0	0
T14	490	0	0	0
T15	408	0	0	0
T16	19907	0	0	0
T24	759	0	0	0
T25	633	0	0	0
T33	0	81	0	0
T35	0	37	0	0
T36	0	85	0	0
T49	658	0	0	0
T74	0	198	0	0
T114	0	37	0	0
T142	0	169	0	0
T163	0	76	0	0
T196	0	100	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	6784	0	0
T1	1121	5	0	0
T2	33179	14	0	0
T3	1059	1	0	0
T4	494	7	0	0
T5	492	6	0	0
T6	3067	16	0	0
T7	3625	20	0	0
T13	5766	25	0	0
T14	490	7	0	0
T15	408	0	0	0
T16	0	29	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	7600407	0	0
T1	1121	721	0	0
T2	33179	32701	0	0
T3	1059	659	0	0
T4	494	94	0	0
T5	492	92	0	0
T6	3067	667	0	0
T7	3625	1225	0	0
T13	5766	5366	0	0
T14	490	90	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8235605	15	0	0
T33	750	1	0	0
T35	543	0	0	0
T36	0	1	0	0
T47	662	0	0	0
T48	768	0	0	0
T81	0	1	0	0
T91	10305	0	0	0
T95	8533	0	0	0
T127	17287	0	0	0
T142	0	1	0	0
T151	435	0	0	0
T163	0	1	0	0
T166	0	1	0	0
T220	0	1	0	0
T224	0	1	0	0
T236	547	0	0	0
T237	504	0	0	0
T252	0	1	0	0
T265	0	1	0	0